SN65220, SN65240, SN75240
ZHCSNT1J – FEBRUARY 1997 – REVISED AUGUST 2022
SNx52x0 USB 端口瞬态抑制器
1 特性
3 说明
• 旨在保护亚微米 3V 或 5V 电路免受
瞬态噪声的影响
• 端口 ESD 保护功能超越了：
– 15kV 人体放电模型
– 2kV 机器模型
• 采用 WCSP 芯片级封装
• 关断电压：6V（最小值）
• 低电流泄漏：6V 时的最大值为 1µA
• 低电容：35pF（典型值）
SN65220 器件为双路单向瞬态电压抑制器，SN65240
和 SN75240 器件为四路单向瞬态电压抑制器 (TVS)。
这些器件为通用串行总线 (USB) 低速和全速端口提供
电瞬态噪声保护。35pF 的输入电容使其不适合用于高
速 USB 2.0 应用。
2 应用
SN65220、SN65240 和 SN75240 器件的 ESD 性能是
在系统级别上根据 IEC61000-4-2 进行测量的；但是，
系统设计会影响这些测试的结果。为了达到高符合性标
准，需要周密的电路板设计和布局布线技术。
所有带线缆的 I/O 都容易遭受来自各种信号源的电瞬态
噪声影响。这些瞬态噪声如果具有足够的幅度和持续时
间，就有可能导致 USB 收发器或 USB ASIC 受到损
坏。
• USB 全速主机、HUB 或外设
• 端口
器件信息(1)
器件型号
封装
SN65220
SN65240
SN75240
(1)
封装尺寸（标称值）
SOT-23 (6)
2.90mm × 1.60mm
DSBGA (4)
0.925mm × 0.925mm
PDIP (8)
9.09mm × 6.35mm
TSSOP (8)
3.00mm × 4.40mm
如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
7.5
USB
Transceiver
D+
A
15 k
GND
SN65220 or ½
SNx5240
0
-2.5
-7.5
B
简化版原理图
2.5
-5
15 k
27
Current – A
5
27
D-
-10
-10
-5
0
5
10
Voltage – V
15
TVS 电流与电压间的关系
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLS266
SN65220, SN65240, SN75240
www.ti.com.cn
ZHCSNT1J – FEBRUARY 1997 – REVISED AUGUST 2022
Table of Contents
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information....................................................4
7.5 Electrical Characteristics.............................................4
7.6 Typical Characteristics................................................ 5
8 Parameter Measurement Information............................ 5
9 Detailed Description........................................................6
9.1 Overview..................................................................... 6
9.2 Functional Block Diagram........................................... 6
9.3 Feature Description.....................................................7
9.4 Device Functional Modes............................................7
10 Application and Implementation.................................. 8
10.1 Application Information............................................. 8
10.2 Typical Application.................................................... 8
11 Power Supply Recommendations..............................10
12 Layout...........................................................................10
12.1 Layout Guidelines................................................... 10
12.2 Layout Example...................................................... 10
13 Device and Documentation Support..........................11
13.1 接收文档更新通知................................................... 11
13.2 支持资源..................................................................11
13.3 Trademarks............................................................. 11
13.4 Electrostatic Discharge Caution.............................. 11
13.5 术语表..................................................................... 11
14 Mechanical, Packaging, and Orderable
Information.................................................................... 11
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision I (April 2021) to Revision J (August 2022)
Page
• Updated the SN65220, SN65240, and SN75240 suppressors in the Device Comparison table........................3
Changes from Revision H (May 2015) to Revision I (April 2021)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式......................................................................................... 1
• 将简化版原理图 图中的电阻单位从 O 更改为 Ω ................................................................................................1
• Updated the units from O to Ω in the Typical Application Schematic for ESD Protection of USB Transceivers
figure ..................................................................................................................................................................8
• Updated the units from O to Ω in the Layout Example of a 4-Layer Board With SN65220 figure................... 10
Changes from Revision G (August 2008) to Revision H (May 2015)
Page
• 添加了引脚配置和功能 部分、ESD 表、热性能信息 表、特性说明 部分、器件功能模式、应用和实施 部分、
电源相关建议 部分、布局 部分、器件和文档支持 部分以及机械、封装和可订购信息 部分............................... 1
2
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5 Device Comparison Table
PRODUCT
SUPPRESSORS
TA - RANGE
PACKAGE
SN65220
2
–40°C to 85°C
SN65240
4
–40°C to 85°C
SN75240
4
0°C to 70°C
WCSP-4
SOT23-6
DIP-8
TSSOP-8
DIP-8
TSSOP-8
6 Pin Configuration and Functions
1
GND
2
NC
3
SADI
NC
6
A
5
GND
4
B
GND
C
GND
D
8
7
6
5
1
2
3
4
A
GND
B
GND
图 6-2. P, PW Package,s 8-Pin PDIP, TSSOP (Top
View)
图 6-1. DBV Package, 6-Pin SOT-23 (Top View)
表 6-1. Pin Functions
PIN
TYPE
DESCRIPTION
NAME
DBV
P, PW
A
6
8
Analog input
Transient suppressor input – Line 1
B
4
6
Analog input
Transient suppressor input – Line 2
C
—
2
Analog input
Transient suppressor input – Line 3
D
—
4
Analog input
Transient suppressor input – Line 4
GND
2, 5
1, 3, 5, 7
Power
NC
1, 3
—
—
Local device ground
Internally not connected
A
A1
A2
GND
B
B1
B2
GND
图 6-3. YZB Package, 4-Pin DSBGA (Top View)
表 6-2. Pin Functions
PIN
TYPE
DESCRIPTION
NO.
NAME
A1
A
Analog input
Transient suppressor input – Line 1
B1
B
Analog input
Transient suppressor input – Line 2
A2, B2
GND
Power
Local device ground
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
60
W
Peak forward surge current
3
A
Peak reverse surge current
–9
A
150
°C
PD(peak)
Peak power dissipation
IFSM
IRSM
Tstg
Storage temperature
(1)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under 节 7.3 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
V(ESD)
(1)
(2)
Electrostatic discharge
pins(1)
UNIT
±15000
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins(2)
V
±2000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
TA
Ambient temperature
SN75240
SN65220, SN65240
MAX UNIT
0
70
–40
85
°C
7.4 Thermal Information
SN65220
THERMAL METRIC(1)
SN65240, SN75240
DBV
(SOT-23)
YZB
(DSBGA)
6 PINS
4 BALLS
P
(PDIP)
PW
(TSSOP)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
199.5
170
67.5
185.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
159.7
1.8
57.9
68.8
°C/W
RθJB
Junction-to-board thermal resistance
51.1
43.5
44.5
114.0
°C/W
ψJT
Junction-to-top characterization parameter
41
9.2
36.2
9.9
°C/W
ψJB
Junction-to-board characterization parameter
50.5
43.5
44.5
112.3
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
4
TEST CONDITIONS
Ilkg
Leakage current
VI = 6 V at A, B, C, or D terminals
V(BR)
Breakdown voltage
VI = 1 mA at A, B, C, or D terminals
CIN
Input capacitance to ground
VI = 0.4 sin (4E6πt) + 0.5 V
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MIN
TYP
MAX
1
6.5
7
35
8
UNIT
µA
V
pF
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ZHCSNT1J – FEBRUARY 1997 – REVISED AUGUST 2022
7.6 Typical Characteristics
TA = 25°C unless otherwise noted.
7.5
5
TVS Current – A
2.5
0
-2.5
-5
-7.5
-10
-10
-5
0
5
TVS Voltage – V
10
15
图 7-1. Transient-Voltage-Suppressor Current vs Voltage
8 Parameter Measurement Information
ILK
VI
DUT
图 8-1. Measurement of Leakage Current
II
VBR
DUT
图 8-2. Measurement of Breakdown Voltage
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9 Detailed Description
9.1 Overview
The SN65220, SN65240, and SN75240 devices integrate multiple unidirectional transient voltage suppressors
(TVS). 图 9-1 shows the equivalent circuit diagram of a single TVS diode.
For positive transient voltages, only the Q1 transistor determines the switching characteristic. When the input
voltage reaches the Zener voltage, VZ, Zener diode D1 conducts; therefore, allowing for the base-emitter
voltage, VBE, to increase. At VIN = VZ + VBE, the transistor starts conducting. From then on, its on-resistance
decreases linearly with increasing input voltage.
For negative transient voltages, only diode D2 determines the switching characteristic. Here, switching occurs
when the input voltage exceeds the diode forward voltage, VFW.
7.5
5
Current – A
A,B,C or D
D1
Q1
D2
R1
GND
2.5
VFW
VZ
VBE
0
-2.5
-5
Measured
from A,B,C
or D to GND
-7.5
-10
-10
-5
0
5
10
Voltage – V
15
图 9-1. TVS Structure and Current — Voltage Characteristic
9.2 Functional Block Diagram
SN65240
SN75240
A C
SN65220
A
GND
GND
GND
GND
GND
GND
B
6
B
D
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9.3 Feature Description
The SN65220, SN65240, and SN75240 family of unidirectional transient voltage suppressors provide transient
protection to Universal Serial Bus low and full−speed ports. These TVS diodes provide a minimum breakdown
voltage of 6.5-V to protect USB transceivers and USB ASICs typically implemented in 3-V or 5-V digital CMOS
technology.
9.4 Device Functional Modes
TVS diodes possess two functional modes, a high-impedance and a conducting mode.
During normal operating conditions, that is in the absence of high voltage transients, the breakdown voltage of
TVS diodes is not exceeded and the devices remain high-impedance.
In the presence of high-voltage transients the breakdown voltage is exceeded. The TVS diodes then conduct
and become low-impedance. In this mode excessive transient energy is shunted directly to local circuit ground,
preventing USB transceivers from electrical damage.
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10 Application and Implementation
备注
以下应用部分中的信息不属于 TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
10.1 Application Information
The USB has become a popular solution to connect PC peripherals. The USB allows devices to be hot-plugged
in and out of the existing PC system without rebooting or turning off the PC. Because frequent human interaction
with the USB system occurs as a result of its attractive hot-plugging ability, there is the possibility for large ESD
strikes and damage to crucial system elements. The ESD protection included on the existing hardware is
typically in the 2-kV to 4-kV range for the human body model (HBD) and 200-V to 300-V for the machine model
(MM). The ESD voltage levels found in a normal USB operating environment can exceed these levels. The
SN75240, SN65240, and SN65220 devices will increase the robustness of the existing USB hardware to ESD
strikes common to the environment in which USB is likely to be used.
10.2 Typical Application
图 10-1 shows a typical USB system and application of the SN75240, SN65240, and SN65220 devices.
Connections to pin A from the D+ data line, pin B from the D– data line, and the device grounds from the GND
line that already exists are necessary to increase the amount of ESD protection provided to the USB port.
The design of the suppressor gives it very low maximum current leakage of 1 μA, a very low typical capacitance
of 35 pF, and a standoff voltage minimum of 6 V. Because of these levels, the SN75240, SN65240, and
SN65220 devices will provide added protection to the USB system hardware during ESD events without
introducing the high capacitance and current leakage levels typical of external transient voltage suppressors.
The addition of an SN75240, SN65240, or SN65220 device is beneficial to both full-speed and low-speed USB
1.1 bandwidth standards.
USB down stream
transceiver
USB hub port
transceiver
1.5 k(1)
27
D+
D+
A
27
A
15 k
GND
SN65220 or ½
SNx5240
GND
SN65220 or ½
SNx5240
15 k
1.5 k(2)
B
D-
D-
B
1) Full-speed only 27
2) Low-speed only
27
图 10-1. Typical Application Schematic for ESD Protection of USB Transceivers
8
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10.2.1 Design Requirements
For this design example, use the parameters listed in 表 10-1 as design parameters.
表 10-1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Minimum breakdown voltage (TVS)
6.5 V
Maximum supply voltage (USB transceiver)
5.5 V
Typical junction capacitance (TVS)
35 pF
Maximum data rate (USB transceiver)
12 Mbps
10.2.2 Detailed Design Procedure
To effectively protect USB transceivers, use TVS diodes with breakdown voltages close to 6 V, such as the
SN65220, SN65240, or SN75220 devices.
Because of the TVS junction capacitance of 35 pF, apply these TVS diodes only to USB transceivers with fullspeed capability that is 12 Mbps maximum.
Place the TVS diodes as close to the board connector as possible to prevent transient energies from entering
further board space.
Connect the TVS diode between the data lines (D+, D–) and local circuit ground (GND).
Because noise transient represents high-speed frequencies, ensure low-inductance return paths for the transient
currents by providing a solid ground plane and using two VIAs connecting the TVS terminals to ground.
10.2.3 Application Curve
Ipk
I(A)
90%
Ipk
10%
Ipk
tr
Time
图 10-2. HBM Curve
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11 Power Supply Recommendations
Unlike other semiconductor components that require a supply voltage to operate, the SN65220, SN65240, and
SN75240 transient suppressors are combinations of multiple p-n diodes, activated by transient voltages.
Therefore, these transient suppressors do not require external voltage supplies.
12 Layout
12.1 Layout Guidelines
The multiple ground pins provided lower the connection resistance to ground. In order to improve circuit
operation, a connection to all ground pins must be provided on the system printed circuit board. Without proper
device connection to ground, the speed and protection capability of the device will be degraded.
• The ground termination pads should be connected directly to a ground plane on the board for optimum
performance. A single trace ground conductor will not provide an effective path for fast rise-time transient
events including ESD due to parasitic inductance.
• Nominal inductive values of a PCB trace are approximately 20 nH/cm. This value may seem small, but an
apparent short length of trace may be sufficient to produce significant L(di/dt) effects with fast rise-time ESD
spikes.
• Mount the TVS as close as possible to the I/O socket to reduce radiation originating from the transient as it is
routed to ground.
备注
Direct connective paths of the traces are taken to the suppressor mounting pads to minimize parasitic
inductance in the surge-current conductive path, thus minimizing L(di/dt) effects.
12.2 Layout Example
VIA to Power Ground Plane
USB
Connector
VIA to Power Supply Plane
GND
USB
Transceiver
15 k
27
NC
27
SN65220
A
GND
GND
NC
B
D+
D-
15 k
VBUS
图 12-1. Layout Example of a 4-Layer Board With SN65220
10
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13 Device and Documentation Support
13.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
13.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
13.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
13.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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23-May-2025
PACKAGING INFORMATION
Orderable part number
(1)
Status
Material type
(1)
(2)
Package | Pins
Package qty | Carrier
RoHS
(3)
Lead finish/
Ball material
MSL rating/
Peak reflow
(4)
(5)
Op temp (°C)
Part marking
(6)
SN65220DBVR
Active
Production
SOT-23 (DBV) | 6
3000 | LARGE T&R
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 85
SADI
SN65220DBVR.A
Active
Production
SOT-23 (DBV) | 6
3000 | LARGE T&R
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 85
SADI
SN65220DBVRG4
Active
Production
SOT-23 (DBV) | 6
3000 | LARGE T&R
-
Call TI
Call TI
-40 to 85
SN65220DBVT
Obsolete
Production
SOT-23 (DBV) | 6
-
-
Call TI
Call TI
-40 to 85
SADI
SN65240P
Active
Production
PDIP (P) | 8
50 | TUBE
Yes
NIPDAU
N/A for Pkg Type
-40 to 85
SN65240P
SN65240P.A
Active
Production
PDIP (P) | 8
50 | TUBE
Yes
NIPDAU
N/A for Pkg Type
-40 to 85
SN65240P
SN65240PW
Obsolete
Production
TSSOP (PW) | 8
-
-
Call TI
Call TI
-40 to 85
A65240
SN65240PWR
Active
Production
TSSOP (PW) | 8
2000 | LARGE T&R
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 85
A65240
SN65240PWR.A
Active
Production
TSSOP (PW) | 8
2000 | LARGE T&R
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 85
A65240
SN75240P
Active
Production
PDIP (P) | 8
50 | TUBE
Yes
NIPDAU
N/A for Pkg Type
0 to 70
SN75240P
SN75240P.A
Active
Production
PDIP (P) | 8
50 | TUBE
Yes
NIPDAU
N/A for Pkg Type
0 to 70
SN75240P
SN75240PW
Obsolete
Production
TSSOP (PW) | 8
-
-
Call TI
Call TI
0 to 70
A75240
Status: For more details on status, see our product life cycle.
(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance,
reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional
waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.
(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.
(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum
column width.
(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown.
Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.
(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.
Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two
combined represent the entire part marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-May-2025
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and
makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers
and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN65220 :
• Automotive : SN65220-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-May-2025
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
B0 W
Reel
Diameter
Cavity
A0
B0
K0
W
P1
A0
Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
SN65220DBVR
SOT-23
DBV
6
3000
178.0
9.0
SN65240PWR
TSSOP
PW
8
2000
330.0
12.4
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3.23
3.17
1.37
4.0
8.0
Q3
7.0
3.6
1.6
8.0
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-May-2025
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN65220DBVR
SOT-23
DBV
6
3000
180.0
180.0
18.0
SN65240PWR
TSSOP
PW
8
2000
356.0
356.0
35.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-May-2025
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name
Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
SN65240P
P
PDIP
8
50
506
13.97
11230
4.32
SN65240P.A
P
PDIP
8
50
506
13.97
11230
4.32
SN75240P
P
PDIP
8
50
506
13.97
11230
4.32
SN75240P.A
P
PDIP
8
50
506
13.97
11230
4.32
Pack Materials-Page 3
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
B
6
2X 0.95
1.9
0.1 C
A
3.05
2.75
5
2
4
6X
0.2
0.50
0.25
C A B
3
4X 0 -15
(1.1)
0.15
TYP
0.00
1.45
0.90
4X 4 -15
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214840/G 08/2024
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2
5
3
4
2X (0.95)
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214840/G 08/2024
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2
5
3
4
2X(0.95)
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/G 08/2024
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
PW0008A
TSSOP - 1.2 mm max height
SCALE 2.800
SMALL OUTLINE PACKAGE
C
6.6
TYP
6.2
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
6X 0.65
8
1
3.1
2.9
NOTE 3
2X
1.95
4
5
B
4.5
4.3
NOTE 4
SEE DETAIL A
8X
0.30
0.19
0.1
C A
1.2 MAX
B
(0.15) TYP
0.25
GAGE PLANE
0 -8
0.15
0.05
0.75
0.50
DETAIL A
TYPICAL
4221848/A 02/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
8X (0.45)
SYMM
1
8
(R0.05)
TYP
SYMM
6X (0.65)
5
4
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221848/A 02/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
8X (0.45)
SYMM
(R0.05) TYP
1
8
SYMM
6X (0.65)
5
4
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221848/A 02/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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