SN65472DREP

SN65472-EP www.ti.com SLRS061 – SEPTEMBER 2013 DUAL PERIPHERAL DRIVER Check for Samples: SN65472-EP FEATURES 1 • • • • • • • Characterized for Use up to 300 mA High-Voltage Outputs No Output Latch-Up at 55 V (After Conducting 300 mA) Medium-Speed Switching Circuit Flexibility for Varied Applications and Choice of Logic Function TTL-Compatible Diode-Clamped Inputs Standard Supply Voltages SUPPORTS INDUSTRIAL APPLICATIONS • • • • • • • Controlled Baseline One Assembly and Test Site One Fabrication Site Available in Extended (–40°C to 125°C) Temperature Ranges (1) Extended Product Life Cycle Extended Product-Change Notification Product Traceability D PACKAGE (TOP VIEW) 1A 1B 1Y GND (1) 1 8 2 7 3 6 4 5 VCC 2B 2A 2Y Custom temperature ranges available DESCRIPTION/ORDERING INFORMATION The SN65472 dual peripheral driver is functionally interchangeable with series SN75452B and series SN75462 peripheral drivers, but is designed for use in systems that require higher breakdown voltages than either of those series can provide at the expense of slightly slower switching speeds than series 75452B (limits are the same as series SN75462). Typical applications include high-speed logic buffers, power drivers, relay drivers, lamp drivers, MOS drivers, line drivers, and memory drivers. The SN65472 is a dual peripheral NAND driver (assuming positive logic), with the output of the logic gates internally connected to the bases of the npn output transistors. This device is characterized for operation from -40°C to 125°C. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated SN65472-EP SLRS061 – SEPTEMBER 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) TJ PACKAGE -40°C to 125°C (1) (2) (2) SOIC − D ORDERABLE PART NUMBER TOP-SIDE MARKING VID NUMBER Tape of 75 SN65472DEP 65472 V62/13618-01XE-T Reel of 2500 SN65472DREP 65472 V62/13618-01XE For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. LOGIC SYMBOL LOGIC DIAGRAM (POSITIVE LOGIC) 3 1 & 1A 1 3 2 1Y 1A 1Y 2 1B 1B 6 2A 5 5 7 6 2Y 2Y 2A 2B 7 2B This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 4 GND Table 1. FUNCTION TABLE (EACH DRIVER) INPUTS A (1) Y (1) B L L H (Off state) L H H (Off state) H L H (Off state) H H L (On state) positive logic: Y = AB or A + B SCHEMATIC (EACH DRIVER) VCC 4 kΩ 1.6 kΩ 1.6 kΩ 130 Ω Y A B 500 Ω 1 kΩ 1 kΩ GND Resistor values shown are nominal. 2 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: SN65472-EP SN65472-EP www.ti.com SLRS061 – SEPTEMBER 2013 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN MAX (2) UNIT VCC Supply voltage range 7 V VI Input voltage 5.5 V Inter-emitter voltage (3) 5.5 V Off-state output voltage 70 V 400 mA 500 mA VO IO Continuous collector or output current (4) Peak collector or output current (tw ≤ 10 ms, duty cycle ≤ 50%) (4) TJ Absolute maximum junction temperature range –40 150 °C Tstg Storage temperature range –65 150 °C (1) (2) (3) (4) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Voltage values are with respect to the network GND, unless otherwise specified. This is the voltage between two emitters, A and B. Both halves of these dual circuits may conduct rated current simultaneously; however, power dissipation averaged over a short time interval must fall within the continuous dissipation rating. THERMAL INFORMATION SN65472-EP THERMAL METRIC (1) D UNITS 8 PINS Junction-to-ambient thermal resistance (2) θJA 115.3 (3) θJCtop Junction-to-case (top) thermal resistance θJB Junction-to-board thermal resistance (4) 56.2 ψJT Junction-to-top characterization parameter (5) 13.5 ψJB Junction-to-board characterization parameter (6) 55.6 (7) N/A θJCbot (1) (2) (3) (4) (5) (6) (7) Junction-to-case (bottom) thermal resistance 59.7 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer RECOMMENDED OPERATING CONDITIONS VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage TA Operating free-air temperature range TJ Operating virtual junction temperature MIN NOM MAX UNIT 4.75 5 5.25 V 2.1 V 0.8 V -40 85 °C -40 125 °C Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: SN65472-EP 3 SN65472-EP SLRS061 – SEPTEMBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS These specifications apply for -40°C ≤ TJ ≤ 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX -1.2 -1.5 V 270 µA UNIT VIK Input clamp voltage VCC = 4.75 V, II = – 12 mA IOH High-level output current VCC = 4.75 V, VIH = 2 V, VOH = 70 V VOL Low level output voltage II Input current at maximum input voltage VCC = 5.25 V, VI = 5.5 V 1 mA IIH High-level input current VCC = 5.25 V, VI = 2.4 V 44 µA IIL Low-level input current VCC = 5.25 V, VI = 0.4 V -1 -1.6 mA ICCH Supply current, outputs high VCC = 5.25 V, VI = 5 V 13 17 mA ICCL Supply current, outputs low VCC = 5.25 V, VI = 0 61 76 mA (1) VCC = 4.75 V, VIL= 0.8 V, IOL = 100 mA 0.25 0.4 VCC = 4.75 V, VIL= 0.8 V, IOL = 300 mA 0.5 0.75 V All typical values are at VCC = 5 V, TA = 25°C. SWITCHING CHARACTERISTICS VCC = 5 V, TA = 25°C, over operating free-air temperature range (unless otherwise noted) TYP MAX tPLH Propagation delay time, low-to-high-level output PARAMETER IO ≈ 200 mA, CL = 15 pF, RL = 50 Ω, see Figure 2 45 65 ns tPHL Propagation delay time, high-to-low-level output IO ≈ 200 mA, CL = 15 pF, RL = 50 Ω, see Figure 2 30 50 ns tTLH Transition time, low-to-high-level output IO ≈ 200 mA, CL = 15 pF, RL = 50 Ω, see Figure 2 13 25 ns tTHL Transition time, high-to-low-level output IO ≈ 200 mA, CL = 15 pF, RL = 50 Ω, see Figure 2 10 20 ns VOH High level output voltage after switching VS = 55 V, IO ≈ 300 mA, see Figure 3 4 TEST CONDITIONS Submit Documentation Feedback MIN VS - 18 UNIT mV Copyright © 2013, Texas Instruments Incorporated Product Folder Links: SN65472-EP SN65472-EP www.ti.com SLRS061 – SEPTEMBER 2013 1000000 Estimated Life (Hours) 100000 Wirebond Voiding Fail Mode 10000 1000 80 85 90 95 100 105 110 115 120 125 130 135 140 145 150 Junction Temperature (°C) (1) See Datasheet for Absolute Maximum and minimum Recommended Operating Conditions. (2) Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect life). Figure 1. SN65472-EP Wirebond Life Derating Chart Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: SN65472-EP 5 SN65472-EP SLRS061 – SEPTEMBER 2013 www.ti.com PARAMETER MEASUREMENT INFORMATION Input 2.4 V 10 V RL = 50 Ω ’472 0.5 µs Output Pulse Generator (see Note A) ≤ 5 ns ≤ 10 ns 90% Input ’472 Circuit Under Test 3V 90% 50% 50% 10% 10% tPHL GND CL = 15 pF (see Note B) SUB 0V tPLH 90% 90% 50% 10% Output VOH 50% 10% VOL tTHL tTLH VOLTAGE WAVEFORMS TEST CIRCUIT NOTES: A. The pulse generator has the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω. B. CL includes probe and jig capacitance. Figure 2. Switching Times VS = 55 V Input 2.4 V 2 mH 5V 40 µs 1N3064 ’472 Pulse Generator (see Note A) 180 Ω Output Input ’472 90% 50% 3V 90% 50% 10% Circuit Under Test GND ≤ 10 ns ≤ 5 ns 10% 0V VOH SUB CL = 15 pF (see Note B) Output VOL VOLTAGE WAVEFORMS TEST CIRCUIT NOTES: A. The pulse generator has the following characteristics: PRR ≤ 12.5 kHz, ZO ≈ 50 Ω. B. CL includes probe and jig capacitance. Figure 3. Latch-Up Test 6 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: SN65472-EP PACKAGE OPTION ADDENDUM www.ti.com 2-Oct-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) SN65472DEP ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 65472 SN65472DREP ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 65472 V62/13618-01XE ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 65472 V62/13618-01XE-T ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 65472 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 2-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN65472DREP Package Package Pins Type Drawing SOIC D 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 6.4 B0 (mm) K0 (mm) P1 (mm) 5.2 2.1 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 2-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65472DREP SOIC D 8 2500 340.5 338.1 20.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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