SN65DP141
SLLSES6C – FEBRUARY 2016 – REVISED DECEMBER 2021
SN65DP141 DisplayPort Linear Redriver
1 Features
3 Description
•
The SN65DP141 is an asynchronous, protocolagnostic, low latency, four-channel linear equalizer
optimized for use up to 12 Gbps and compensates
for losses due to board traces and cables.
•
•
•
•
•
•
•
•
•
•
•
Supports VESA DisplayPort 1.4a,
2.0, and eDP 1.4
Quad channel linear redriver supporting data rates
up to 12 Gbps including DisplayPort RBR, HBR,
HBR2, HBR3, and UHBR10
Protocol agnostic
Transparent to DP link training
Position independent on the link suitable for
source, sink, and cable applications
15-dB analog equalization at 6 GHz
Output linear dynamic range: 1200 mV
Bandwidth: >20 GHz
Better than 16-dB return loss at 6 GHz
2.5-V or 3.3-V ±5% single power supply option
Low power consumption with 80 mW per channel
at 2.5 V VCC
GPIO or I2C control
The device is transparent to DisplayPort (DP) link
training such a way that a DP source and a sink can
perform effective link training overcoming traditional
aux snooping re-drivers’ shortcomings. Additionally,
the device is position independent. It can be placed
inside source, cable or sink effectively providing a
negative loss component to the overall link budget.
Linear equalization inside SN65DP141 also increases
link margin when used with a receiver implementing
Decision Feedback Equalization (DFE).
SN65DP141 allows independent channel control for
equalization, gain, dynamic range using both I2C and
GPIO configurations.
2 Applications
Device Information(1)
Tablets
Notebooks
Desktops
Docking stations
PART NUMBER
SN65DP141
(1)
PACKAGE
WQFN (38)
BODY SIZE (NOM)
7.00 mm × 5.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
.
.
DP0
DP141
OUTP0
DP1
OUTP1
DP2
OUTP2
DP3
OUTP3
GPU
ML0
ML1
ML2
DisplayPort Connector
•
•
•
•
x
AUXp
AUXn
HPD
ML3
AUXp
AUXn
x
x
GPU
DP141
DP141
HPD
Copyright © 2016, Texas Instruments Incorporated
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN65DP141
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SLLSES6C – FEBRUARY 2016 – REVISED DECEMBER 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics.............................................6
6.6 Switching Characteristics............................................7
6.7 Switching Characteristics, I2C Interface......................8
6.8 Typical Characteristics................................................ 9
7 Parameter Measurement Information.......................... 10
8 Detailed Description......................................................14
8.1 Overview................................................................... 14
8.2 Functional Block Diagram......................................... 14
8.3 Feature Description...................................................15
8.4 Device Functional Modes..........................................16
8.5 Register Maps...........................................................17
9 Application and Implementation.................................. 23
9.1 Application Information............................................. 23
9.2 Typical Application.................................................... 23
10 Power Supply Recommendations..............................25
11 Layout........................................................................... 26
11.1 Layout Guidelines................................................... 26
11.2 Layout Example...................................................... 27
12 Device and Documentation Support..........................28
12.1 Receiving Notification of Documentation Updates..28
12.2 Support Resources................................................. 28
12.3 Trademarks............................................................. 28
12.4 Electrostatic Discharge Caution..............................28
12.5 Glossary..................................................................28
13 Mechanical, Packaging, and Orderable
Information.................................................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (September 2021) to Revision C (December 2021)
Page
• Changed the I2C_EN pin Type from internal pull-up to internal pull-down ........................................................ 3
Changes from Revision A (October 2016) to Revision B (September 2021)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Updated the features from: Supports VESA DisplayPort 1.3, and eDP 1.4. to: Supports VESA DisplayPort
1.4a, 2.0, and eDP 1.4........................................................................................................................................1
• Updated the features from: including DisplayPort RBR, HBR, HBR2, and HBR3 to: including DisplayPort
RBR, HBR, HBR2, HBR3, and UHBR10............................................................................................................ 1
• Updated the DP bit rates from: RBR to HBR3 (1.6 Gbps, 2.7 Gbps, 5.4 Gbps and 8.1 Gbps ... to: RBR to
UHBR10 (1.6 Gbps, 2.7 Gbps, 5.4 Gbps, 8.1 Gbps and 10.0 Gbps … in the Overview section......................14
• Updated Operating data rate from HBR3 (8.1 Gbps) to UHBR10 (10 Gbps)................................................... 23
Changes from Revision * (February 2016) to Revision A (October 2016)
Page
• Replaced Figure 9-2 ........................................................................................................................................ 24
2
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VCC
PWD#
RX_GAIN
EQ_MODE/_ADD2
EQ1/ADD1
EQ0/ADD0
VCC
5 Pin Configuration and Functions
38
37
36
35
34
33
32
IN0_P
1
31
OUT0_P
IN0_N
2
30
OUT0_N
VCC
3
29
VCC
IN1_P
4
28
OUT1_P
IN1_N
5
27
OUT1_N
VCC
6
26
VCC
25
VCC
Thermal
Pad
9
23
OUT2_N
VCC
10
22
VCC
IN3_P
11
21
OUT3_P
IN3_N
12
20
OUT3_N
13
14
15
16
17
18
19
VCC
IN2_N
REXT
OUT2_P
TX_DC_GAIN/CS
24
I2C_EN
8
DRV_PK#/SCL
IN2_P
SDA
7
VCC
VCC
It is required for the thermal pad to be soldered to ground for better thermal performance.
Figure 5-1. RLJ Package 38 Pins (WQFN) Top View
Table 5-1. Pin Functions
PIN
NAME
NO.
TYPE(1)
DESCRIPTION
DIFFERENTIAL HIGH-SPEED I/O
IN0_P
1
I
IN0_N
2
I
IN1_P
4
I
IN1_N
5
I
IN2_P
8
I
IN2_N
9
I
IN3_P
11
I
IN3_N
12
I
OUT0_P
31
O
OUT0_N
30
O
OUT1_P
28
O
OUT1_N
27
O
OUT2_P
24
O
OUT2_N
23
O
OUT3_P
21
O
OUT3_N
20
O
Differential input, lane 0 (with 50 Ω termination to input common mode)
Differential input, lane 1 (with 50 Ω termination to input common mode)
Differential input, lane 2 (with 50 Ω termination to input common mode)
Differential input, lane 3 (with 50 Ω termination to input common mode)
Differential output, lane 0
Differential output, lane 1
Differential output, lane 2
Differential output, lane 3
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Table 5-1. Pin Functions (continued)
PIN
NAME
NO.
TYPE(1)
DESCRIPTION
CONTROL SIGNALS
15
I
GPIO mode:
(with 200-kΩ internal HIGH: disable Driver peaking
pull-up)
LOW: enables Driver 6-dB AC peaking
I2C mode:
I2C CLK. Connect a 10-kΩ pull-up resistor
externally.
35
I
GPIO mode:
(with 200-kΩ Internal
HIGH: Trace mode
pull-down, 2.5 V/3.3
LOW: Cable mode
V CMOS )
I2C mode:
ADD2 along with pins ADD1 and ADD0
comprise the three bits of I2C slave
address. ADD2:ADD1:ADD0:XXX
33
I
GPIO mode:
(2.5 V/3.3 V CMOS - Working with RX_GAIN and EQ1 to determine the
3-state)
receiver DC and AC gain.
I2C mode:
ADD0 along with pins ADD1 and ADD2
comprise the three bits of I2C slave
address. ADD2:ADD1:ADD0:XXX
EQ1/ADD1
34
I
GPIO mode:
(2.5 V/3.3 V CMOS - Working with RX_GAIN and EQ0 to determine the
3-state)
receiver DC and AC gain.
I2C mode:
ADD1 along with pins ADD0 and ADD2
comprise the three bits of I2C slave
address ADD2:ADD1:ADD0:XXX
I2C_EN
16
I
Configures the device operation for I2C or GPIO mode:
(with 200-kΩ internal HIGH: enables I2C mode
pull-down)
LOW: enables GPIO mode
PWD#
37
I
(with 200-kΩ Internal HIGH: Normal Operation
pull-up, 2.5 V/3.3 V LOW: Power downs the device, inputs off and outputs disabled, resets I2C
CMOS)
REXT
18
DRV_PK#/SCL
EQ_MODE/ ADD2
EQ0/ADD0
RX_GAIN
36
SDA
14
TX_DC_GAIN/CS
17
I (analog)
External Bias Resistor: 1,200 Ω to GND
I
GPIO mode:
(2.5 V/3.3 V CMOS - Working with EQ0 and EQ1 to determine the
3-state)
receiver DC and AC gain.
I/O (open drain)
GPIO mode:
No action needed.
I
GPIO mode:
(with 200-kΩ Internal
HIGH: 6 dB DC gain for transmitter
pull-down, 2.5 V/3.3
LOW: 0 dB DC gain for transmitter
V CMOS)
I2C mode:
No action needed
I2C mode:
I2C data. Connect a 10-kΩ pull-up resistor
externally.
I2C mode:
HIGH: acts as Chip Select
LOW: disables I2C interface
POWER SUPPLY
GND Center Pad
VCC
(1)
4
3, 6, 7, 10, 13,
19, 22, 25, 26,
29, 32, 38
Ground
The ground center pad is the metal contact at the bottom of the package. This pad must be
connected to the GND plane. At least 15 PCB vias are recommended to minimize inductance
and provide a solid ground. Refer to the package drawing (RLJ-package) for the via placement.
Power
Power supply 2.5 V ±5%, 3.3 V ±5%
I = input, O = output
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
MAX
UNIT
Supply voltage range
VCC
–0.3
4
V
Differential voltage between INx_P and INx_N
VIN, DIFF
–2.5
2.5
V
Voltage at INx_P and INx_N,
VIN+, IN–
–0.5
VCC + 0.5
V
–0.5
VCC + 0.5
V
Voltage on control IO pins,VIO
Continuous current at high speed differential data
inputs(differential)
IN+, IN–
–25
25
mA
Continuous current at high speed differential data
outputs
IOUT+, IOUT–
–25
25
mA
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC
V(ESD)
(1)
(2)
Electrostatic discharge
JS-001(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101(2)
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. .
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
12
Gbps
2.375
2.5/3.3
3.465
V
DR
Operating data rate
VCC
Supply voltage
TC
Junction temperature
–10
125
°C
TA
Operating free-air temperature
–40
85
°C
CMOS DC SPECIFICATIONS
VIH
Input high voltage
0.8 x VCC
V
V(MID)
Input middle voltage
VCC x 0.4
VCC x 0.6
V
VIL
Input low voltage
–0.5
0.2 x VCC
V
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6.4 Thermal Information
SN65DP141
THERMAL
METRIC(1)
UNIT
RLJ (WQFN)
38 PINS
RθJA
Junction-to-ambient thermal resistance
36.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
22.3
°C/W
RθJB
Junction-to-board thermal resistance
10.7
°C/W
ψJT
Junction-to-top characterization parameter
0.3
°C/W
ψJB
Junction-to-board characterization parameter
10.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.9
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOD = Low, VCC = 3.3 V and all 4 channels
active
450
625
mW
VOD = Low, VCC = 2.5 V and all 4 channels
active
317
475
mW
VOD = High, VCC = 3.3 V and all 4 channels
active
697
925
mW
VOD = High, VCC = 2.5 V and all 4 channels
active
485
675
mW
POWER CONSUMPTION
PDL
Device Power dissipation
PDH
Device Power dissipation
PDOFF
Device power with all 4 channels
switched off
Refer to I2C section for device configuration
10
mW
CMOS DC SPECIFICATIONS
IIH
High level input current
VIN = 0.9 × VCC
-40
17
40
µA
IIL
Low level input current
VIN = 0.1 × VCC
-40
17
40
µA
CML INPUTS (IN[3:0]_P, IN[3:0]_N)
RIN
Differential input resistance
INx_P to INx_N
VIN
Input linear dynamic range
Gain = 0.5
VICM
Input common mode voltage
Internally biased
SCD11
Input differential to common
mode conversion
SDD11
Differential input return loss
100
Ω
1200
mVpp
VCC – 0.8
V
100 MHz to 6 GHz
-20
dB
100 MHz to 6 GHz
-15
dB
CML OUTPUTS (OUT[3:0]_P, OUT[3:0]_N)
VOD
6
Output linear dynamic range
RL = 100 Ω, VOD = HIGH
1200
mVpp
RL = 100 Ω, VOD = LOW
600
mVpp
10
mVpp
VOS
Output offset voltage
VOCM
Output common mode voltage
RL = 100 Ω, 0 V applied at inputs
VCM(RIP)
Common mode output ripple
K28.5 pattern at 12 Gbps on all 4 channels,
No interconnect loss, VOD = HIGH
VOD(RIP)
Differential path output ripple
K28.5 pattern at 12 Gbps on all channels, No
interconnect loss, VIN = 1200 mVpp.
VOC(SS)
Change in steady-state common
mode output voltage between
logic states
VCC – 0.4
10
±10
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V
20
mVRMS
20
mVpp
mV
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6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CML OUTPUTS (OUT[3:0]_P, OUT[3:0]_N)
tR
Rise time (1)
Input signal with 30 ps rise time, 20% to 80%,
See Figure 7-3
31
ps
tF
Fall time (1)
Input signal with 30 ps fall time, 20% to 80%,
See Figure 7-3
32
ps
SDD22
Differential output return loss
6 GHz (12 Gbps)
-14
dB
4.05 GHz (HBR3, 8.1 Gbps)
–9.33
dB
4.05 GHz (HBR3, 8.1 Gbps)
–6.35
dB
–3.5
dB
65
ps
65
ps
8
ps
1.35 GHz (HBR, 2.7Gbps)
tPLH
Low-to-high propagation delay
tPHL
High-to-low propagation delay
See Figure 7-2
tSK(O)
Inter-Pair (lane to lane) output skew (2) All outputs terminated with 100 Ω,
See Figure 7-4
tSK(PP)
Part-to-part skew (3)
All outputs terminated with 100 Ω
rOT
Single ended output resistance
Single ended on-chip termination to VCC,
Outputs are AC coupled
rOM
Output termination mismatch at 1 MHz
'rOM
50
50
ps
Ω
5%
§ rp - rn ·
2x ¨
¸ x 100
rp ¹
© rn
Channel-to-channel isolation
Frequency at 6 GHz
45
dB
Output referred noise(4)
10 MHz to 6 GHz, No other noise source present,
VOD = LOW
35
400
µVRMS
10 MHz to 6 GHz, No other noise source present,
VOD = HIGH
500
µVRMS
15
dB
EQUALIZATION
G
At 6 GHz input signal
Equalization Gain, EQ = MAX
V(pre)
Output pre-cursor pre-emphasis
Input signal with 3.75 pre-cursor and measure it on
the output signal,
See Figure 7-5
3.75
dB
V(pst)
Output post-cursor pre-emphasis
Input signal with 12 dB post-cursor and measure it
on the output signal,
See Figure 7-5
12
dB
(1)
(2)
(3)
(4)
Rise and Fall measurements include board and channel effects of the test environment, refer to Figure 7-1 and Figure 7-3.
tSK(O) is the magnitude of the time difference between the channels.
tSK(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same
All noise sources added.
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6.7 Switching Characteristics, I2C Interface
over operating free-air temperature range (unless otherwise noted)
PARAMETER
8
MIN
TYP
MAX
UNIT
400
KHz
fSCL
SCL clock frequency
tBUF
Bus free time between START and STOP conditions
1.3
µs
tHDSTA
"Hold time after repeated START condition.
After this period, the first clock pulse is generated
0.6
µs
tLOW
Low period of the SCL clock
1.3
µs
tHIGH
High period of the SCL clock
0.6
µs
tSUSTA
Setup time for a repeated START condition
0.6
µs
tHDDAT
Data HOLD time
0
µs
tSUDAT
Data setup time
100
µs
tR
Rise time of both SDA and SCL signals
300
µs
tF
Fall time of both SDA and SCL signals
300
µs
tSUSTO
Setup time for STOP condition
0.6
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6.8 Typical Characteristics
0
0
−5
−10
−10
−20
Amplitude (dB)
Amplitude (dB)
−15
−20
−25
−30
−40
−30
−50
−35
−60
−40
−45
0
2
4
6
8
Frequency (GHz)
10
12
−70
14
0
2
4
6
8
Frequency (GHz)
10
12
G002
Figure 6-1. Differential Input Return Loss
14
G003
Figure 6-2. Differential to Common Mode Conversion
0
0
−5
−5
−10
−10
Amplitude (dB)
Amplitude (dB)
−15
−15
−20
−25
−20
−25
−30
−30
−35
−35
−40
−40
0
2
4
6
8
Frequency (GHz)
10
12
14
−45
0
G004
Figure 6-3. Differential Output Return Loss
2
4
6
8
Frequency (GHz)
10
12
14
G005
Figure 6-4. Common Mode Output Return Loss
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7 Parameter Measurement Information
OUT+
50
OUT-
50
VOCM
1pF
Copyright © 2016, Texas Instruments Incorporated
Figure 7-1. Common Mode Output Voltage Test Circuit
SPACE
VID = 0 V
IN
tPLH
tPHL
VOD = 0 V
OUT
Figure 7-2. Propagation Delay Input to Output
SPACE
80%
80%
VOD
20%
20%
tr
tf
Figure 7-3. Output Rise and Fall Times
SPACE
10
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OUTx
t SK(0)
OUTy
Figure 7-4. Output Inter-Pair Skew
SPACE
V1
V3
V2
0V
V5
Not drawn to scale
V6
V4
Figure 7-5. V(pre) and V(post) (test pattern is 1111111100000000 (8-1s, 8-0s))
SPACE
TEST CHANNEL
CHARACTERIZATION
BOARD
SN65DP141
PATTERN
GENERATOR
OSCILLOSCOPE
L= 2"
RX+EQ
OUT
L= 2"
Figure 7-6. Receive Side Performance Test Circuit
SPACE
TEST CHANNEL
CHARACTERIZATION BOARD
SN65DP141
PATTERN
GENERATOR
L= 2"
OUT
L= 2"
OSCILLOSCOPE
Figure 7-7. Transmit Side Performance Test Circuit
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VCC
IN+
R = 50
T(SE)
Gain
Stage
+EQ
VCC
RBBDC
R = 50
T(SE)
INLine End Termination
VBB
ESD
Self-Biasing Network
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Figure 7-8. Equivalent Input Circuit
SPACE
VCC
VCC
48 k
ESD
IN
ESD
48 k
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Figure 7-9. 3-Level Input Biasing Network
Figure 7-10. Two – Wire Serial Interface Data Transfer
12
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Figure 7-11. Two – Wire Serial Interface Timing Diagram
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8 Detailed Description
8.1 Overview
The SN65DP141 is an asynchronous, protocol-agnostic, low latency, four-channel linear equalizer optimized for
use up to 12 Gbps. The characteristics of this device make it transparent to DisplayPort (DP) link training. It
supports all the available DP bit rates from RBR to UHBR10 (1.6 Gbps, 2.7 Gbps, 5.4 Gbps, 8.1 Gbps, and 10.0
Gbps respectively). Additionally, the SN65DP141 is configurable to a trace or cable mode, and hence improves
its performance depending on the type of channel it is being used. Its transparency to the DP link training
makes the SN65DP141 a position independent device, suitable for source/sink or cable applications, effectively
providing a negative loss component to the overall link budget, in order to compensate the signal degradation
over the channel.
The SN65DP141 is configurable by means of I2C and GPIOs, allowing independent channel control for
activation, equalization, gain, and dynamic range.
8.2 Functional Block Diagram
VCC
GND
VCC
VBB
50
50
Input Buffer with
Selectable Equalizer
50
Output Driver
50
IN[3:0]_P
OUT[3:0]_P
IN[3:0]_N
OUT[3:0]_P
Power-On
Reset
Band-Gap Voltage
Reference and Bias
Current Generation
Power-OnReset
1.2K
200K
200K
DRV_PK#/SCL
DRV_PK#/SCL
SDA
SDA
PWD#
VOD/CS
200K
General Setting
3 Bit Register
4 Bit Register
1 Bit Register
1 Bit Register
EQ Control
Channel Enable
2 Bit Register
AC Gain
VOD Swing
DC Gain
I2C_EN
I2C_EN
PWD#
EQ0/ADD0
EQ0/ADD0
VOD/CS
EQ1/ADD1
EQ1/ADD1
GAIN
GAIN
6 Bit Register
EQ_MODE/ADD2
2-Wire Interface and Control Logic
EQ_MODE/ADD2
200K
200K
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8.3 Feature Description
8.3.1 DC and AC Independent Gain Control
Besides the functional block diagram, the behavior of the SN65DP141 can be described as it is shown in Figure
8-1; where the input stage first applies a DC gain (0 dB or –6 dB) and then equalizes the signal, which is driven
to the output stage where the SN65DP141 applies an output DC gain (0 dB or 6 dB).
RX_GAIN(EQ_DC_GAIN)
EQUALIZATION(EQ_AC_GAIN)
TX_GAIN(TX_DC_GAIN)
INx_P
OUTx_P
Up to 15dB
0dB or -6dB
INx_N
0dB or 6dB
OUTx_N
Figure 8-1. DP141 Signal Chain Gain Control
8.3.2 Two-Wire Serial Interface and Control Logic
The SN65DP141 uses a 2-wire serial interface for digital control. The two circuit inputs, SDA and SCL, are
driven, respectively, by the serial data and serial clock from a microcontroller, for example. The SDA and SCK
pins require external 10 kΩ pull-ups to VCC.
The 2-wire interface allows write access to the internal memory map to modify control registers and read access
to read out control and status signals. The SN65DP141 is a slave device only which means that it cannot initiate
a transmission itself; it always relies on the availability of the SCK signal for the duration of the transmission. The
master device provides the clock signal as well as the START and STOP commands. The protocol for a data
transmission is as follows:
1. START command
2. 7 bit slave address (0000ADD [2:0]) followed by an eighth bit which is the data direction bit (R/W). A zero
indicates a WRITE and a 1 indicates a READ. The ADD [2:0] address bits change with the status of the
ADD2, ADD1, and ADD0 device pins, respectively. If the pins are left floating or pulled down, the 7 bit slave
address is 0000000.
3. 8-bit register address
4. 8-bit register data word
5. STOP command
Regarding timing, the SN65DP141 is I2C compatible. The typical timing is shown in Figure 7-11 and a complete
data transfer is shown in Figure 7-10. Parameters for these figures are defined in the I2C Interface section of the
Switching Characteristics.
8.3.3 Bus Idle
Both SDA and SCL lines remain HIGH
8.3.4 Start Data Transfer
A change in the state of the SDA line, from HIGH to LOW, while the SCL line is HIGH, defines a START
condition (S). Each data transfer is initiated with a START condition.
8.3.5 Stop Data Transfer
A change in the state of the SDA line from LOW to HIGH while the SCL line is HIGH defines a STOP condition
(P). Each data transfer is terminated with a STOP condition; however, if the master still wishes to communicate
on the bus, it can generate a repeated START condition and address another slave without first generating a
STOP condition.
8.3.6 Data Transfer
The number of data bytes transferred between a START and a STOP condition is not limited and is determined
by the master device. The receiver acknowledges the transfer of data.
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8.3.7 Acknowledge
Each receiving device, when addressed, is obliged to generate an acknowledge bit. The transmitter releases the
SDA line and a device that acknowledges must pull down the SDA line during the acknowledge clock pulse in
such a way that the SDA line is stable LOW during the HIGH period of the acknowledge clock pulse. Setup and
hold times must be taken into account. When a slave-receiver doesn’t acknowledge the slave address, the data
line must be left HIGH by the slave. The master can then generate a STOP condition to abort the transfer. If the
slave-receiver does acknowledge the slave address but some time later in the transfer cannot receive any more
data bytes, the master must abort the transfer. This is indicated by the slave generating the not acknowledge on
the first byte to follow. The slave leaves the data line HIGH and the master generates the STOP condition.
8.4 Device Functional Modes
8.4.1 TRACE and CABLE Equalization Modes
The SN65DP141 is optimized for both trace and cable application at its input. The device pin EQ_MODE sets
the EQ gain curve profile suitable for these two use cases.
8.4.2 Control Modes
The SN65DP141 features two control modes: GPIO and I2C, and the selection between these two modes is by
means of the I2C_EN terminal, which activates the GPIO when tied to LOW; otherwise, the I2C mode is active
due to its internal pull-up resistance.
8.4.3 GPIO MODE
Device Pins RX_GAIN, EQ1 and EQ0 determines receiver DC and AC gain as shown in Table 8-1 and Table 8-2.
Table 8-1. EQ Pin Settings
EQ1
EQ0
EQ Setting
GND
GND
000
GND
HiZ
000
GND
VCC
001
HiZ
GND
010
HiZ
HiZ
011
HiZ
VCC
100
VCC
GND
101
VCC
HiZ
110
VCC
VCC
111
Table 8-2. RX DC and AC GAIN Settings
EQ Configuration
16
EQ Gain
EQ Setting
RX_GAIN
EQ_DC_GAIN (dB)
000 - 111
LOW
–6
1-9
000 - 111
HiZ
–6
7 - 17
000 - 111
HIGH
0
1-9
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8.4.4 I2C Mode
Table 8-3. I2C Control Settings Description for RX DC and AC GAIN
EQ_MODE
EQ_DC GAIN
RX_GAIN
EQ_Setting
DC GAIN (dB)
AC GAIN (dB)
00
000 to 111
–6
1 to 9
Short Input Cable; Large Input Swing
0
0
1
0
1
1
APPLICATION
11
000 to 111
–6
7 to 17
Long Input Cable; Large Input Swing
01
000 to 111
0
1 to 9
Short Input Cable; Small Input Swing
11
000 to 111
0
2 to 10
Short Input Cable, Small Input Swing
00
000 to 111
–6
1 to 9
Short Input Trace; Large Input Swing
11
000 to 111
–6
7 to 17
Long Input Trace; Large Input Swing
01
000 to 111
0
1 to 9
Short Input Trace; Small Input Swing
11
000 to 111
0
2 to 10
Short Input Trace, Small Input Swing
8.5 Register Maps
8.5.1 Register 0x00 (General Device Settings) (offset = 00000000) [reset = 00000000]
Figure 8-2. Register 0x00 (General Device Settings)
7
6
5
4
3
2
SW_GPIO
PWRDOWN
SYNC_01
SYNC_23
SYNC_ALL
EQ_MODE
R/W
R/W
R/W
R/W
R/W
R/W
1
0
RSVD
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-4. Register 0x00 (General Device Settings)
Bit
Field
Type
Reset
Description
SW_GPIO
R/W
0
Switching logic is controlled by GPIO or I2C:
0 = I2C control
1 = GPIO control
6
PWRDOWN
R/W
0
Power down the device:
0 = Normal operation
1 = Powerdown
5
SYNC_01
R/W
0
All settings from channel 1 will be used for channel 0 and 1:
0 = Channel 0 tracking channel 1 settings
1 = No tracking tracking
4
SYNC_ 23
R/W
0
All settings from channel 2 will be used for channel 2 and 3:
0 = Channel 3 tracking channel 2 settings
1 = No channel tracking
3
SYNC_ALL
R/W
0
All settings from channel 1 will be used on all channels:
0 = All channels tracking channel 1
1 = No channel tracking
Overwrites SYNC_01 and SYNC_23
2
EQ_MODE
R/W
0
Set EQ mode:
0 = Cable mode
1 = Trace mode
R/W
0
R/W
0
7
1
0
RSVD
For TI use only
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8.5.2 Register 0x01 (Channel Enable) (offset = 00000000) [reset = 00000000]
Figure 8-3. Register 0x01 (Channel Enable)
7
6
5
4
R
R
R
R
3
2
1
0
LN_EN_CH3
LN_EN_CH2
LN_EN_CH1
LN_EN_CH0
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-5. Register 0x01 (Channel Enable)
Bit
18
Type
Reset
7
Field
R
0
6
R
0
5
R
0
4
R
0
Description
3
LN_EN_CH3
R/W
0
Channel 3 enable:
0 = Enable
1 = Disable
2
LN_EN_CH2
R/W
0
Channel 3 enable:
0 = Enable
1 = Disable
1
LN_EN_CH1
R/W
0
Channel 1 enable:
0 = Enable
1 = Disable
0
LN_EN_CH0
R/W
0
Channel 0 enable:
0 = Enable
1 = Disable
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8.5.3 Register 0x02 (Channel 0 Control Settings) (offset = 00000000) [reset = 00000000]
Figure 8-4. Register 0x02 (Channel 0 Control Settings)
7
6
5
4
3
2
1
0
RSVD
EQ Setting
EQ Setting
EQ Setting
TX_GAIN
EQ_DC_GAIN
RX_GAIN
RX_GAIN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-6. Register 0x02 (Channel 0 Control Settings)
Bit
Field
Type
Reset
7
RSVD
R/W
0
Description
6
EQ Setting
R/W
0
5
EQ Setting
R/W
0
4
EQ Setting
R/W
0
3
TX GAIN
R/W
0
Channel [0] TX_DC_GAIN control:
0 = Set 0 dB DC gain for transmitter
1 = Set 6 dB DC gain for transmitter
2
EQ_DC_GAIN
R/W
0
Channel [0] EQ DC gain:
0 = Set EQ DC gain to -6 dB
1 = Set EQ DC gain to -0 dB
1
RX_GAIN
R/W
0
0
RX_GAIN
R/W
0
Equivalent to RX_GAIN control pin for channel [0].
00: RX_GAIN = Low
01: RX_GAIN = HiZ
11: RX_GAIN = High
Equalizer adjustment setting:
000 = Minimum equalization setting
111 = Maximum equalization setting
8.5.4 Register 0x03 (Channel 0 Enable Settings) (offset = 00000000) [reset = 00000000]
Figure 8-5. Register 0x03 (Channel 0 Enable Settings)
7
6
R
5
R
4
R
3
R
R
2
1
0
DRV_PEAK
EQ_EN
DRV_EN
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-7. Register 0x03 (Channel 0 Enable Settings)
Bit
Field
Type
Reset
7
R
0
6
R
0
5
R
0
4
R
0
3
Description
R
0
2
DRV_PEAK
R/W
0
Channel [0] driver peaking:
0 = Disables driver Peaking
1 = Enables driver 6 db AC Peaking"
1
EQ_EN
R/W
0
Channel [0] EQ stage enable:
0 = Enable
1 = Disable
0
RSVDRV_EN
R/W
0
Channel [0] driver stage enable:
0 = Enable
1 = Disable
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8.5.5 Register 0x05 (Channel 1 Control Settings) (offset = 00000000) [reset = 00000000]
Figure 8-6. Register 0x05 (Channel 1 Control Settings)
7
6
5
4
3
2
1
0
RSVD
EQ Setting
EQ Setting
EQ Setting
TX_GAIN
EQ_DC_GAIN
RX_GAIN
RX_GAIN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-8. Register 0x05 (Channel 1 Control Settings)
Bit
Field
Type
Reset
7
RSVD
R/W
0
Description
6
EQ Setting
R/W
0
5
EQ Setting
R/W
0
4
EQ Setting
R/W
0
3
TX_GAIN
R/W
0
Channel [1] TX_DC_GAIN control:
0 = Set 0 dB DC gain for transmitter
1 = Set 6 dB DC gain for transmitter
2
EQ_DC_GAIN
R/W
0
Channel [1] EQ DC gain:
0 = Set EQ DC gain to -6 dB
1 = Set EQ DC gain to -0 dB
1
RX_GAIN
R/W
0
0
RX_GAIN
R/W
0
Equivalent to RX_GAIN control pin for channel [1].
00: RX_GAIN = Low
01: RX_GAIN = HiZ
11: RX_GAIN = High
Equalizer adjustment setting:
000 = Minimum equalization setting
111 = Maximum equalization setting
8.5.6 Register 0x06 (Channel 1 Enable Settings) (offset = 00000000) [reset = 00000000]
Figure 8-7. Register 0x06 (Channel 1 Enable Settings)
7
6
R
R
5
4
R
3
R
R
2
1
0
DRV_PEAK
EQ_EN
DRV_EN
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-9. Register 0x06 (Channel 1 Enable Settings)
Bit
Field
Type
Reset
7
R
0
6
R
0
5
R
0
4
R
0
3
20
Description
R
0
2
DRV_PEAK
R/W
0
Channel [1] driver peaking:
0 = Disables driver Peaking
1 = Enables driver 6 db AC Peaking
1
EQ_EN
R/W
0
Channel [1] EQ stage enable:
0 = Enable
1 = Disable
0
DRV_EN
R/W
0
Channel [1] driver stage enable:
0 = Enable
1 = Disable
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8.5.7 Register 0x08 (Channel 2 Control Settings) (offset = 00000000) [reset = 00000000]
Figure 8-8. Register 0x08 (Channel 2 Control Settings)
7
6
5
4
3
2
1
0
RSVD
EQ Setting
EQ Setting
EQ Setting
TX_GAIN
EQ_DC_GAIN
RX_GAIN
RX_GAIN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-10. Register 0x08 (Channel 2 Control Settings)
Bit
Field
Type
Reset
7
RSVD
R/W
0
Description
6
EQ Setting
R/W
0
5
EQ Setting
R/W
0
4
EQ Setting
R/W
0
3
TX_GAIN
R/W
0
Channel [2] TX_DC_GAIN control:
0 = Set 0 dB DC gain for transmitter
1 = Set 6 dB DC gain for transmitter
2
EQ_DC_GAIN
R/W
0
Channel [2] EQ DC gain:
0 = Set EQ DC gain to -6 dB
1 = Set EQ DC gain to -0 dB
1
RX_GAIN
R/W
0
0
RX_GAIN
R/W
0
Equivalent to RX_GAIN control pin for channel [2].
00: RX_GAIN = Low
01: RX_GAIN = HiZ
11: RX_GAIN = High
Equalizer adjustment setting:
000 = Minimum equalization setting
111 = Maximum equalization setting
8.5.8 Register 0x09 (Channel 2 Enable Settings) (offset = 00000000) [reset = 00000000]
Figure 8-9. Register 0x09 (Channel 2 Enable Settings)
7
6
R
5
R
4
R
3
R
R
2
1
0
DRV_PEAK
EQ_EN
DRV_EN
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-11. Register 0x09 (Channel 2 Enable Settings)
Bit
Field
Type
Reset
7
R
0
6
R
0
5
R
0
4
R
0
3
Description
R
0
2
DRV_PEAK
R/W
0
Channel [2] driver peaking:
0 = Disables driver Peaking
1 = Enables driver 6 db AC Peaking
1
EQ_EN
R/W
0
Channel [2] driver stage enable:
0 = Enable
1 = Disable
0
DRV_EN
R/W
0
Channel [2] driver stage enable:
0 = Enable
1 = Disable
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8.5.9 Register 0x0B (Channel 3 Control Settings) (offset = 00000000) [reset = 00000000]
Figure 8-10. Register 0x0B (Channel 3 Control Settings)
7
6
5
4
3
2
1
0
RSVD
EQ Setting
EQ Setting
EQ Setting
TX_GAIN
EQ_DC_GAIN
RX_GAIN
RX_GAIN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-12. Register 0x0B (Channel 3 Control Settings)
Bit
Field
Type
Reset
7
RSVD
R/W
0
Description
6
EQ Setting
R/W
0
5
EQ Setting
R/W
0
4
EQ Setting
R/W
0
3
TX_GAIN
R/W
0
Channel [3] TX_DC_GAIN control:
0 = Set 0 dB DC gain for transmitter
1 = Set 6 dB DC gain for transmitter
2
EQ_DC_GAIN
R/W
0
Channel [3] EQ DC gain:
0 = Set EQ DC gain to -6 dB
1 = Set EQ DC gain to -0 dB
1
RX_GAIN
R/W
0
0
RX_GAIN
R/W
0
Equivalent to RX_GAIN control pin for channel [3].
00: RX_GAIN = Low
01: RX_GAIN = HiZ
11: RX_GAIN = High
Equalizer adjustment setting:
000 = Minimum equalization setting
111 = Maximum equalization setting
8.5.10 Register 0x0C (Channel 3 Control Settings) (offset = 00000000) [reset = 00000000]
Figure 8-11. Register 0x0C (Channel 3 Enable Settings)
7
6
R
5
R
4
R
3
R
R
2
1
0
DRV_PEAK
EQ_EN
DRV_EN
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-13. Register 0x0C (Channel 3 Enable Settings)
Bit
Field
Type
Reset
7
R
0
6
R
0
5
R
0
4
R
0
3
22
Description
R
0
2
DRV_PEAK
R/W
0
Channel [3] driver peaking:
0 = Disables driver Peaking
1 = Enables driver 6db AC Peaking
1
EQ_EN
R/W
0
Channel [3] EQ stage enable:
0 = Enable
1 = Disable
0
RSVDRV_EN
R/W
0
Channel [3] driver stage enable:
0 = Enable
1 = Disable
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The SN65DP141 can be used in Source, Sink, cable, and dongle applications, where the device is transparent
to the DisplayPort link layer. For illustrating purposes, this section shows the implementation of a DisplayPort
dongle, Figure 9-1 shows an example of the SN65DP141 on a dongle board, where the AUX channel is directly
connected from source to sink, meanwhile the power can be provided either way from the DP source or an
external power source.
9.2 Typical Application
POWER SOURCE
3P3V
DP SOURCE
DP SINK
ML0_IN
ML0_OUT
ML1_IN
ML1_OUT
ML2_IN
ML3_IN
ML2_OUT
DP141
ML3_OUT
3P3V
AUX
HPD
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Figure 9-1. SN65DP141 Application Diagram
9.2.1 Design Requirements
The SN65DP141 can be designed into many types of applications. All applications have certain requirements for
the system to work properly. The voltage rails are required to support the lowest possible power consumption.
Configure the device by using I2C. The GPIO configuration is provided as I2C is not available in all cases.
Because sources may have different naming conventions, confirm the link between source and sink is correctly
mapped through the SN65DP141.
Table 9-1. Design Parameters
PARAMETER
VALUE
Operating data rate
UHBR10 (10 Gbps)
Supply voltage
3.3 V
Main link input voltage
VID = 75 mVpp to 1.2 Vpp
Control pin Low
1 KΩ pulled to GND
Control pin Mid
No Connect
Control pin Low
1 KΩ pulled to High
Main link AC decoupling capacitor
75 to 200 nF, recommend 100 nF
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First approach for GAIN configuration: It is highly recommend that DC GAIN be set to 1, this leads the output to
preserve the input amplitude (GAIN = 1):
• For GPIO implementation: Use a pull-up resistor on the GAIN terminal (pin 36), refer to the schematic in
Figure 9-2.
• For I2C implementation: write a 1 to the bit 2 of the registers 0x02, 0x05, 0x08 and 0x0B. Refer to Section
8.3.2 for a detailed description of the I2C interface
9.2.2 Detailed Design Procedure
Designing in the SN65DP141 requires the following:
• Determine the loss profile on the DP input and output channels and cables.
• Based upon the loss profile and signal swing, determine the optimal configuration for the SN65DP141, to
pass electrical compliance (Equalization mode, EQ Gain, DC gain, and AC Gain).
• See Figure 9-2 for information on using the AC coupling capacitors and control pin resistors, as well as for
recommended decouple capacitors from VCC pins to ground.
• Configure the TheSN65DP141 using the GPIO terminals or the I2C interface:
– GPIO – Using the terminals EQ_MODE, EQ1, EQ1, and gain.
– I2C – Refer to the I2C Register Maps and the Two-Wire Serial Interface and Control Logic sections for a
detailed configuration procedures.
• The thermal pad must be connected to ground.
3P3V
C1
LP1
C2
10uF
BOARD_3P3V
3P3V
Place near DP141
C3
0.1uF
C4
0.1uF
C5
0.1uF
C6
0.1uF
0.1uF
C7
C8
0.1uF
C9
0.1uF
0.1uF
C10
C11
0.1uF
0.1uF
LP2
FB1
220 @ 100MHZ
C14
SRC_DP_ML0N
0.1uF
0201
0201
0.1uF
C15
SRC_DP_ML1P
C18
SRC_DP_ML1N
0.1uF
0201
0201
0.1uF
C20
SRC_DP_ML2P
C22
SRC_DP_ML2N
0.1uF
0201
0201
0.1uF
C24
SRC_DP_ML3P
C26
SRC_DP_ML3N
141_DP_IN0P
141_DP_IN0N
1
2
141_DP_IN1P
141_DP_IN1N
4
5
141_DP_IN2P
141_DP_IN2N
8
9
141_DP_IN3P
141_DP_IN3N
11
12
BOARD_3P3V
0.1uF
0201
R10
1K
SDA
DRV_PK#/SCL
I2C_EN
VOD/CS
14
15
16
17
EQ0/ADD0
EQ1/ADD1
EQ_MODE/ADD2
33
34
35
36
C13
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
SRC_DP_ML0P
3
6
7
10
13
19
25
26
29
32
38
22
Connecting to DP Receiver
U1
0201
0.1uF
C12
IN0_P
IN0_N
OUT0_P
OUT0_N
IN1_P
IN1_N
OUT1_P
OUT1_N
IN2_P
IN2_N
OUT2_P
OUT2_N
IN3_P
IN3_N
OUT3_P
OUT3_N
SDA
DRV_PK#/SCL
I2C_EN
VOD/CS
31
30
141_DP_OUT0P
141_DP_OUT0N
C16
28
27
141_DP_OUT1P
141_DP_OUT1N
C17
24
23
141_DP_OUT2P
141_DP_OUT2N
21
20
141_DP_OUT3P
141_DP_OUT3N
C19
C21
C23
C25
REXT
PWD#
PwPd
DP141
SNK_DP_ML0P
0.1uF
0201
0201
0.1uF
SNK_DP_ML0N
0.1uF
0201
0201
0.1uF
SNK_DP_ML1N
0.1uF
0201
0201
0.1uF
SNK_DP_ML2N
0.1uF
0201
SNK_DP_ML3N
SNK_DP_ML0P
SNK_DP_ML0N
SNK_DP_ML1P
SNK_DP_ML1P
SNK_DP_ML1N
SNK_DP_ML2P
SNK_DP_ML2P
SNK_DP_ML2N
SNK_DP_ML3P
SNK_DP_ML3P
18
C27
R1
EQ0/ADD0
EQ1/ADD1
EQ_MODE/ADD2
GAIN
0201
0.1uF
37
PWD#
SNK_DP_ML3N
1.2K
39
NOTE: ALL DIFF PAIRS ARE
ROUTEDTO 90 OHMS
DIFFERENTIAL AND 50 OHMS
COMMON MODE. ALL OTHER
TRACES ARE 50 OHM.
NOTE:Min of 15 Vias
recommended for GND Pad
connection
3P3V
3P3V
SILKSCREEN:
SDA
PWD#
Device disable/I2C Reset if asserted low
SW1
B3SN-3012
R18
0R
J2
1
DRV_PK#/SCL 2
3
HDR3X1 M .1
I2C_EN
HDR3X1 M .1
R11
DNI, 1K
J3
1
2
3
VOD/CS
HDR3X1 M .1
R12
DNI, 1K
BOARD_3P3V
R7
DNI, 1K
1
2
3
HDR3X1 M .1
R13
DNI, 1K
EQ1/ADD1
HDR3X1 M .1
R14
DNI, 1K
C28
1uF
R9
DNI, 1K
J5
1
2
3
EQ0/ADD0
BOARD_3P3V
R8
DNI, 1K
J4
J6
1
2
3
1
EQ_MODE/ADD2 2
3
HDR3X1 M .1
R15
DNI, 1K
HDR3X1 M .1
R16
DNI, 1K
BOARD_3P3V
Value of the cap to vary
depending on power rail
ramp-up time
5V
R28
DRV_PK#/SCL 1
3
SDA
5
7
9
2
4
6
8
10
1
2
3
4
5
VBUS
DD+
ID
GND
Shield1
Shield2
Shield3
Shield4
Shield5
Shield6
6
7
8
9
10
11
BOARD_3P3V
USB2_micAB_Recept
U2
8
1
C29
3
10uF
VIN
L1
SW
VOS
7
1uH
EN
J12
MODE
GND
9
2
Header 5x2 0.1" Shroud RA thru-hole
175K
5V
J13
J8
6
3
J1
BOARD_3P3V
R6
DNI, 1K
PG
2
1
2
3
BOARD_3P3V
R5
DNI, 1K
PwPd
4
BOARD_3P3V
R4
DNI, 1K
J0
EN
1
BOARD_3P3V
R3
1K
R2
1K
FB
5
C30
4
1
DP_PWR
2
DP_PWR_SRC 3
22uF
HDR3X1 M .1
TPS62082DSGT
Figure 9-2. SN65DP141 Application Schematic
24
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9.2.3 Application Curves
0
0.25
3 meter
6 meter
6 meter (See Note A)
3 meter
6 meter
6 meter (See Note A)
−5
0.2
−10
Magnitude (dB)
Amplitude (mV)
−15
0.15
0.1
−20
−25
−30
−35
0.05
−40
0
0
200
400
600
800 1k 1.2k 1.4k 1.6k 1.8k
Time (ps)
−45
2k
0
2
4
6
Frequency (GHz)
8
10
G006
G007
With SN65DP141 -> EQ = 4, VOD = High, ACGain = HiZ,
DCGain = Low
With SN65DP141 -> EQ = 4, VOD = High, ACGain = HiZ,
DCGain = Low
Figure 9-3. Cable Mode – Symbol Response
Figure 9-4. Cable Mode – Frequency Domain
0.35
0
3 meter
6 meter
6 meter (See Note A)
0.3
3 meter
6 meter
6 meter (See Note A)
−5
−10
−15
Magnitude (dB)
Amplitude (mV)
0.25
0.2
0.15
−20
−25
−30
−35
0.1
−40
0.05
−45
0
0
200
400
600
800 1k
1k
Time (ps)
1k
2k
2k
2k
−50
0
G008
2
4
6
Frequency (GHz)
8
10
G009
With SN65DP141 -> EQ = 7, VOD = High, ACGain = High,
DCGain = Low
With SN65DP141 -> EQ = 7, VOD = High, ACGain = High,
DCGain = Low
Figure 9-5. Trace Mode – Symbol Response
Figure 9-6. Trace Mode – Frequency Domain
10 Power Supply Recommendations
To minimize the power supply noise floor, provide good decoupling near the SN65DP141 power pins. It is
recommended to place one 0.01-μF ceramic capacitor at each power pin, and two 0.1-μF ceramic capacitors on
each power node. The distance between the SN65DP141 and capacitors should be minimized to reduce loop
inductance and provide optimal noise filtering. Placing the capacitor underneath the SN65DP141 on the bottom
of the PCB is often a good choice. A 100-pF ceramic capacitor can be put at each power pin to optimize the EMI
performance.
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11 Layout
11.1 Layout Guidelines
•
•
•
•
•
•
•
•
•
•
•
•
Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance.
Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power/ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also
the power and ground plane of each power system can be placed closer together, thus increasing the high
frequency bypass capacitance significantly.
The control pin pull-up and pull-down resistors are shown in application section for reference. If a high level is
needed then only uses the pull up. If a low level is needed only use the pull down.
Place passive components within the signal path, such as source-matching resistors or ac-coupling
capacitors, next to each other. Routing as in case a) creates wider trace spacing than in b); the resulting
discontinuity, however, is limited to a far narrower area.
When routing traces next to a via or between an array of vias, make sure that the via clearance section does
not interrupt the path of the return current on the ground plane below.
Avoid metal layers and traces underneath or between the pads off the DisplayPort connectors for better
impedance matching. Otherwise they will cause the differential impedance to drop below 75 Ω and fail the
board during TDR testing.
Use solid power and ground planes for 100 Ω impedance control and minimum power noise.
For a multi-layer PCB, it is recommended to keep one common GND layer underneath the device and
connect all ground terminals directly to this plane. For 100 Ω differential impedance, use the smallest trace
spacing possible, which is usually specified by the PCB vendor.
Keep the trace length as short as possible to minimize attenuation.
Place bulk capacitors (that is, 10 μF) close to power sources, such as voltage regulators or where the power
is supplied to the PCB.
Layer 1: DP Signal layer
5 to 10 mils
Layer 2: Ground plane
20 to 40 mils
Layer 3: Power plane
5 to 10 mils
Layer 4: Control signal layer
Figure 11-1. PCB Stack
26
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SN65DP141
SLLSES6C – FEBRUARY 2016 – REVISED DECEMBER 2021
11.2 Layout Example
Figure 11-2. Example Layout (Top)
Figure 11-3. Example Layout (Top)
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27
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
28
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PACKAGE OPTION ADDENDUM
www.ti.com
17-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN65DP141RLJR
ACTIVE
WQFN
RLJ
38
3000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
DP141
SN65DP141RLJT
ACTIVE
WQFN
RLJ
38
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
DP141
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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