SN65DP159RSBT

Product Folder Order Now Support & Community Tools & Software Technical Documents SN65DP159, SN75DP159 SLLSEJ2G – JULY 2015 – REVISED MARCH 2020 SNx5DP159 6-Gbps AC-Coupled TMDS™ to HDMI™ Level Shifter Retimer 1 Features 3 Description • The SNx5DP159 device is a dual mode[1] DisplayPort to transition-minimized differential signal (TMDS) retimer supporting digital video interface (DVI) 1.0 and high-definition multimedia interface (HDMI) 1.4b and 2.0b output signals. The SNx5DP159 device supports the dual mode standard version 1.1 type 1 and type 2 through the DDC link or AUX channel. The SNx5DP159 device supports data rate up to 6-Gbps per data lane to support Ultra HD (4K × 2K / 60-Hz) 8-bits per color high-resolution video and HDTV with 16-bit color depth at 1080p (1920 × 1080 / 60-Hz). The SNx5DP159 device can automatically configure itself as a re-driver at data rates 3.4 Gbps – 75- to 150-Ω differential near end termination 2 Gbps < DR < 3.4 Gbps – 150- to 300-Ω differential near end termination DR < 2 Gbps – no termination Note: If left floating will be in automatic select mode. Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: SN65DP159 SN75DP159 Submit Documentation Feedback 7 SN65DP159, SN75DP159 SLLSEJ2G – JULY 2015 – REVISED MARCH 2020 www.ti.com Pin Functions (continued) PIN SIGNAL NAME SWAP/POL (1) RGZ RSB 1 N/A (1) DESCRIPTION (2) I/O I 3 level (2) Input lane SWAP and polarity control pin when I2C_EN/PIN = Low SWAP/POL = H receive lane polarity swap (retimer mode only) SWAP/POL = L receive lanes swap (retimer and redriver mode) SWAP/POL = No Connect normal working SUPPLY AND GROUND PINS VCC 13, 43 11, 37 P 3.3-V power supply VDD 14, 23, 24, 37, 48 12, 19, 20, 31, 40 P 1.1-V power supply GND 7, 19, 41, 30, 15, 35 G Ground Thermal Pad Connected to ground 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature (unless otherwise noted) Supply voltage (3) (1) (2) MIN MAX UNIT VCC –0.3 4 V VDD –0.3 1.4 V 1.56 V Main link input (IN_Dx AC-coupled mode), AUX_SRCp, AUX_SRCn differential voltage Voltage TMDS outputs ( OUT_Dx) –0.3 4 V HPD_SRC, Vsadj, SDA_CTL, SCL_CTL, OE, HDMI_SEL/A1, EQ_SEL/A0, I2C_EN/PIN, SLEW_CTL, TX_TERM_CTL, SDA_SRC, SCL_SRC –0.3 4 V –0.3 6 V HPD_SNK, SDA_SNK, SCL_SNK Continuous power dissipation See Thermal Information Storage temperature, Tstg (1) (2) (3) –65 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential voltages, are with respect to network ground terminal. Tested in accordance with JEDEC Standard 22, Test Method A114-B. 7.2 ESD Ratings V(ESD) (1) (2) 8 Electrostatic discharge VALUE UNIT Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) ±500 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: SN65DP159 SN75DP159 SN65DP159, SN75DP159 www.ti.com SLLSEJ2G – JULY 2015 – REVISED MARCH 2020 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX 3 3.3 3.6 1.00 1.1 1.27 UNIT GENERAL PARAMETERS VCC Supply voltage VDD V TCASE Case temperature for RSB package 93.5 °C TCASE Case temperature for RGZ package 92.7 °C TA Operating free-air temperature SN75DP159 0 85 SN65DP159 –40 85 75 1200 0 2 °C MAIN LINK DIFFERENTIAL PINS VID_PP Peak-to-peak input differential voltage VIC Input common mode voltage CAC AC coupling capacitance dR Data rate VSADJ TMDS-compliant swing voltage bias resistor 75 100 0.25 (1) 4.5 Control pins –0.3 200 5 7.06 mv V nF Gbps 7.5 kΩ 3.6 V CONTROL PINS VI-DC DC input voltage Low-level input voltage at OE 0.8 VIL (2) Low-level input voltage at SLEW_CTL, PRE_SEL, EQ_SEL/A0, TX_TERM_CTL, SWAP/POL 0.3 VIM (2) No connect input voltage at SLEW_CTL, PRE_SEL, EQ_SEL/A0, TX_TERM_CTL, SWAP/POL VIH (2) High-level input voltage at SLEW_CTL, OE TX_TERM_CTL, SWAP/POL (3) 1 , PRE_SEL, EQ_SEL/A0, Low-level output voltage VOH High-level output voltage 2.4 IIH High-level input current IIL IOS IOZ High impedance output current ROEPU Pullup resistance on OE pin (2) (3) 1.4 2.6 VOL (1) 1.2 V V V 0.4 V –30 30 µA Low-level input current –10 10 µA Short circuit output current –50 50 mA 10 µA 150 250 kΩ V Best transmit eye with minimum intra-pair skew, largest vertical and horizontal eye opening, maintaining HDMI compliant output swing can be achieved with resistors around 6.4k. Using smaller resistors may lead to compliance failures. These values are based upon a microcontroller driving the control pins. The pullup/pulldown/floating resistor configuration will set the internal bias to the proper voltage level which will not match the values shown here. This value is based upon a microcontroller driving the OE pin. A passive reset circuit using an external capacitor and the internal pullup resistor will set OE pin properly, but may have a different value than shown due to internal biasing. 7.4 Thermal Information THERMAL METRIC (1) SNx5DP159 SNx5DP159 RGZ (VQFN) RSB (WQFN) 48 PINS 40 PINS UNIT RθJA Junction-to-ambient thermal resistance 31.1 37.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance (High-K board (2)) 18.2 23.1 °C/W RθJB Junction-to-board thermal resistance (High-K board (2)) 8.1 9.9 °C/W ψJT Junction-to-top characterization parameter 0.4 0.3 °C/W ψJB Junction-to-board characterization parameter 8.1 3.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 3.2 3.2 °C/W (1) (2) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Test conditions for ΨJB and ΨJT are clarified in TI document Semiconductor and IC Package Thermal Metrics. Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: SN65DP159 SN75DP159 Submit Documentation Feedback 9 SN65DP159, SN75DP159 SLLSEJ2G – JULY 2015 – REVISED MARCH 2020 www.ti.com 7.5 Power Supply Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX (2) UNIT PD1 Device power dissipation (Retimer operation) OE = H, VCC = 3.3 V/3.6 V, VDD = 1.1 V/1.27 V IN_Dx: VID_PP = 1200 mV, 6Gbps TMDS pattern, VI = 3.3 V, I2C_EN/PIN = L, PRE_SEL= H, EQ_CTL= H, SDA_CTL/CLK_CTL = 0 V, VSadj = 7.06 kΩ 435 600 mW PD2 Device power dissipation (Redriver operation) OE = H, VCC = 3.3 V/3.6 V, VDD = 1.1 V/1.27 V IN_Dx: VID_PP = 1200 mV, 6Gbps TMDS pattern, VI = 3.3 V, I2C_EN/PIN = L, PRE_SEL= H, EQ_CTL= H, SDA_CTL/CLK_CTL = 0 V, VSadj = 7.06 kΩ 215 400 mW PSD1 Device power in power down OE = L, VCC = 3.3 V/3.6 V, VDD = 1.1 V/1.27 V, VSadj = 7.06 kΩ 10 30 mW ICC1 VCC supply current (TMDS 6Gpbs retimer mode) OE = H, VCC= 3.3 V/3.6 V, VDD = 1.1V/1.27 V, VSadj = 7.06 kΩ IN_Dx: VID_PP = 1200 mV, 6Gbps TMDS pattern I2C_EN/PIN = L, PRE_SEL = H, EQ_CTL = H, SDA_CTL/CLK_CTL = 0 V, SLEW_CTL = H 35 50 mA IDD1 VDD supply current (TMDS 6Gpbs retimer mode) OE = H, VCC = 3.3 V/3.6 V, VDD = 1.1 V/1.27 V, VSadj = 7.06 kΩ IN_Dx: VID_PP = 1200 mV, 6Gbps TMDS pattern I2C_EN/PIN = L, PRE_SEL = H, EQ_CTL = H, SDA_CTL/CLK_CTL = 0 V, SLEW_CTL = H 295 325 mA ICC2 VCC supply current (TMDS 6Gpbs redriver mode) OE = H, VCC = 3.3 V/3.465 V, VDD = 1.1 V/1.27 V, VSadj = 7.06 kΩ IN_Dx: VID_PP = 1200 mV, 6Gbps TMDS pattern I2C_EN/PIN = L, PRE_SEL = H, EQ_CTL = H, SDA_CTL/CLK_CTL = 0 V, SLEW_CTL = H 8 20 mA IDD2 VDD supply current (TMDS 6Gpbs redriver mode) OE = H, VCC = 3.3 V/3.465 V, VDD = 1.1 V/1.27 V, VSadj = 7.06 kΩ IN_Dx: VID_PP = 1200 mV, 6Gbps TMDS pattern I2C_EN/PIN = L, PRE_SEL = H, EQ_CTL = H, SDA_CTL/CLK_CTL = 0 V, SLEW_CTL = H 170 250 mA ISD1 Power-down current OE = L, VCC = 3.3 V/3.465 V, VDD = 1.1 V/1.27 V, VSadj = 7.06 kΩ 3.3-V rail 2 5 ISD1 Power-down current OE = L, VCC = 3.3 V/3.465 V, VDD = 1.1 V/1.27 V, VSadj = 7.06 kΩ 1.1-V rail 3.5 10 (1) (2) 10 mA The typical rating is simulated at 3.3-V VCC and 1.1-V VDD and at 27°C temperature unless otherwise noted The maximum rating is simulated at 3.6-V VCC and 1.27-V VDD and at 85°C temperature unless otherwise noted Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: SN65DP159 SN75DP159 SN65DP159, SN75DP159 www.ti.com SLLSEJ2G – JULY 2015 – REVISED MARCH 2020 7.6 Differential Input Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DR_RX_DATA Ddata lanes data rate 0.25 6 Gbps DR_RX_CLK Clock lanes clock rate 25 340 MHz tRX_DUTY Input clock duty circle 40% tCLK_JIT Input clock jitter tolerance tDATA_JIT Input data jitter tolerance Test the TTP2, see Figure 10 TRX_INTRA Input intra-pair skew tolerance Test at TTP2 when DR = 1.6-Gbps, see Figure 10 TRX_INTER Input inter-pair skew tolerance EQH(D) Fixed EQ gain for data lane IN_D(0,1,2)n/p EQ_SEL/A0 = H; Fixed EQ gain, test at 6-Gbps 15 dB EQL(D) Fixed EQ gain for data lane IN_D(0,1,2)n/p EQ_SEL/A0 = L; Fixed EQ gain, test at 6-Gbps 7.5 dB EQZ(D) Adaptive EQ gain for data lane IN_D(0,1,2)n/p EQ_SEL/A0 = Z; adaptive EQ EQ(c) EQ gain for clock lane IN_CLKn/p EQ_SEL/A0 = H,L,NC RINT Input differential termination impedance VITERM Input termination voltage OE = H VID_PP Input differential voltage (peak to peak) Tested at TTP2, check Figure 10 50% 60% 0.3 Tbit 150 ps 112 ps 1.8 2 Product Folder Links: SN65DP159 SN75DP159 15 dB 120 Ω 1200 mVPP 3 80 Copyright © 2015–2020, Texas Instruments Incorporated ns 100 0.7 75 V Submit Documentation Feedback 11 SN65DP159, SN75DP159 SLLSEJ2G – JULY 2015 – REVISED MARCH 2020 www.ti.com 7.7 HDMI and DVI TMDS Output Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH TEST CONDITIONS Single-ended high level output voltage VOH Single-ended high level output voltage VOL Single-ended low level output voltage MIN Data rate ≤ 1.65-Gbps; PRE_SEL = NC; TX_TERM_CTL = H; SLEW_CTL = H; OE = H; DR = 750Mbps, VSadj = 7.06-kΩ TYP VCC – 10 MAX VCC + 10 mV 1.65-Gbps < Data rate ≤ 3.4-Gbps; PRE_SEL = NC; TX_TERM_CTL = H; SLEW_CTL = H; OE = H; DR = 2.97-Gbps, VSadj = 7.06-kΩ VCC – 200 VCC + 10 3.4-Gbps < Data rate < 6 Gbps; PRE_SEL = NC; TX_TERM_CTL = L; SLEW_CTL = H; OE = H; DR = 6Gbps, VSadj = 7.06-kΩ VCC – 400 VCC + 10 Data rate ≤ 1.65-Gbps; PRE_SEL = NC; TX_TERM_CTL = H; SLEW_CTL = H; OE = H; DR = 750Mbps, VSadj = 7.06-kΩ VCC – 600 VCC – 400 1.65-Gbps < Data rate ≤ 3.4-Gbps; PRE_SEL = NC; TX_TERM_CTL = H; SLEW_CTL = H; OE = H; DR = 2.97-Gbps, VSadj = 7.06-kΩ VCC – 700 VCC – 400 VCC – 1000 VCC – 400 mV mV Single-ended low level output voltage 3.4-Gbps < Data rate < 6-Gbps; PRE_SEL = NC; TX_TERM_CTL = L; SLEW_CTL = H; OE = H; DR = 6Gbps VSWING_DA Single-ended output voltage swing on data lane PRE_SEL = NC; TX_TERM_CTL = H/NC/L; SLEW_CTL = H; OE = H; DR = 270-Mbs/2.97/6Gbps VSadj = 7.06-kΩ 400 500 600 Data rate ≤ 3.4-Gbps; PRE_SEL = NC; TX_TERM_CTL = H; SLEW_CTL = H; OE = H; VSadj = 7.06-kΩ 400 500 600 Data rate > 3.4-Gbps; PRE_SEL = NC; TX_TERM_CTL = NC; SLEW_CTL = H; OE = H; VSadj = 7.06-kΩ 200 Single-ended output voltage swing on clock lane ΔVSWING Change in single-end output voltage swing per 100 Ω ΔVsadj ΔVOCM(SS) Change in steady state output common mode voltage between logic levels VOD(PP) Output differential voltage before preemphasis VOD(SS) mV mV VOL VSWING_CLK UNIT mV 300 400 20 mV –5 5 mV Vsadj = 7.06-kΩ; PRE_SEL = Z, See Figure 8 800 1200 mV Steady-state output differential voltage Vsadj = 7.06-kΩ; PRE_SEL = L, See Figure 9 600 1050 mV ILEAK Failsafe condition leakage current VCC = 0-V; VDD = 0-V; output pulled to 3.3 V through 50-Ω resistors 45 µA IOS Short circuit current limit Main link output shorted to GND 50 mA RTERM Source termination resistance for HDMI 2.0 150 Ω 12 Submit Documentation Feedback 75 Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: SN65DP159 SN75DP159 SN65DP159, SN75DP159 www.ti.com SLLSEJ2G – JULY 2015 – REVISED MARCH 2020 7.8 AUX, DDC, and I2C Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN CIO Input capacitance CAC AUX AC coupling capacitance 75 DR(AUX) Data rate of the AUX channel input 0.8 VI-DC(AUX) DC input voltage on AUX channel, AUX_SRCp/n: 100-kΩ pull up to 3.6 V but differential common mode is 2 V or less. VAUX_DIFF_PP_TX Peak-to-peak differential voltage at TX pins VAUX_DIFF_PP_RX Peak-to-peak differential voltage at RX pins VAUX_DC_CM AUX channel DC common mode voltage IAUX_SHORT AUX channel short circuit current limit VI-DC VIL VIH TYP AUX data rate = 1-MHz MAX UNIT 10 pF 200 nF 1.2 Mbps -0.5 3.6 V VAUX_DIFF_PP = 2 × |VAUXP – VAUXN| 0.29 1.38 V VAUX_DIFF_PP = 2 × |VAUXP – VAUXN| 0.14 1.36 V 0 2 V 90 mA SCL/SDA_SNK DC input voltage –0.3 5.6 V SCL/SDA_CTL, SCL/SDA_SRC DC input voltage -0.3 3.6 V SCL/SDA_SNK, SCL/SDA_SRC Low level input voltage 0.3 x VCC V SCL/SDA_CTL Low level input voltage 0.3 x VCC V 1 SCL/SDA_SNK high level input voltage 3 V SCL/SDA_SRC high level input voltage 0.7 x VCC V SCL/SDA_CTL high level input voltage 0.7 x VCC V I0 = 3-mA and VCC > 2-V 0.4 V I0 = 3-mA and VCC < 2-V 0.2 VCC V VOL SCL/SDA_CTL, SCL/SDA_SRC lowlevel output voltage fSCL SCL clock frequency fast I2C mode for local I2C control 400 kHz Cbus Total capacitive load for each bus line (DDC and local I2C pins) 400 pF MAX UNIT 7.9 HPD Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIH High-level input voltage HPD_SNK VIL Low-level input voltage HPD_SNK VOH High-level output voltage IOH = –500-µA; HPD_SRC VOL Low-level output voltage IOL = 500-µA; HPD_SRC ILEAK Failsafe condition leakage current IH_HPD MIN TYP 2.1 V 0.8 V 2.4 3.6 V 0 0.1 V VCC = 0-V; VDD = 0-V; HPD_SNK = 5-V 40 μA High-level input current Device powered; VIH = 5-V; IH_HPD includes RpdHPD resistor current 40 μA IL_HPD Low-level input current Device powered; VIL = 0.8-V; IL_HPD includes RpdHPD resistor current 30 RpdHPD HPD input termination to GND VCC = 0-V Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: SN65DP159 SN75DP159 150 190 220 Submit Documentation Feedback kΩ 13 SN65DP159, SN75DP159 SLLSEJ2G – JULY 2015 – REVISED MARCH 2020 www.ti.com 7.10 HDMI and DVI Main Link Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT REDRIVER MODE DR Data rate (Automatic Mode) 250 1000 Mbps DR Data rate (full redriver mode) 250 6000 Mbps tPLH Propagation delay time (low to high) 250 600 ps tPHL Propagation delay time (high to low) 250 800 ps tT1 Transition time (rise and fall time); measured at 20% and 80% levels for data lanes. TMDS clock meets tT3 for all three times. tT2 tT3 SLEW_CTL = H; TX_TERM_CTL = L; PRE_SEL = NC; OE = H; DR = 6 Gbps 45 SLEW_CTL = L; TX_TERM_CTL = NC; PRE_SEL = NC; OE = H; DR = 6 Gbps 65 SLEW_CTL = NC; TX_TERM_CTL = NC; PRE_SEL = NC; OE = H; DR = 6 Gbps; CLK 150MHz ps 100 tSK1(T) Intra-pair output skew SLEW_CTL = NC; TX_TERM_CTL = NC; PRE_SEL = NC; OE = H; DR = 6 Gbps; 40 ps tSK2(T) Inter-pair output skew SLEW_CTL = NC; TX_TERM_CTL = NC; PRE_SEL = NC; OE = H; DR = 6 Gbps; 100 ps tJITD1(1.4b) Total output data jitter DR = 2.97 Gbps, HDMI_SEL/A1 = NC, EQ_SEL/A0 = NC; PRE_SEL = NC; SLEW_CTL = H OE = H. See Figure 10 at TTP3 0.2 Tbit 3.4Gbps < Rbit ≤ 3.712Gps SLEW_CTL = H; TX_TERM_CTL = NC; PRE_SEL = NC; OE = H 0.4 Tbit 3.712Gbps < Rbit < 5.94Gbps SLEW_CTL = H; TX_TERM_CTL = NC; PRE_SEL = NC; OE = H -0.033 2Rbit2 +0.23 12 Rbit + 0.1998 Tbit 5.94Gbps ≤ Rbit ≤ 6.0Gbps SLEW_CTL = H; TX_TERM_CTL = NC; PRE_SEL = NC; OE = H 0.8 Tbit 0.25 Tbit 0.3 Tbit tJITD1(2.0) Total output data jitter tJITC1(1.4b) Total output clock jitter CLK = 297 MHz tJITC1(2.0) Total output clock jitter DR = 6Gbps: CLK = 150 MHz RETIMER MODE dR Data rate (Full retimer mode) 0.25 6 Gbps dR Data rate (Automatic mode) 1.0 6 Gbps 1.25 Gbps dXVR Automatic redriver to retimer crossover fCROSSOVER Crossover frequency hysteresis PLLBW Data retimer PLL bandwidth tACQ Input clock frequency detection and retimer acquisition time IJT1 Input clock jitter tolerance tDCD 14 250 .4 MHz 1 180 45 SLEW_CTL = L; TX_TERM_CTL = NC; PRE_SEL = NC; OE = H; DR = 6 Gbps 65 SLEW_CTL = NC; TX_TERM_CTL = NC; PRE_SEL = NC; OE = H; DR = 6 Gbps; CLK = 150 MHz MHz μs 0.3 SLEW_CTL = H; TX_TERM_CTL = L; PRE_SEL = NC; OE = H; DR = 6 Gbps OUT_CLK ± duty cycle Submit Documentation Feedback 1.0 Tested when data rate > 1.0 Gbps Transition time (rise and fall time); measured at 20% and 80% levels for data lanes. TMDS clock meets tT3 for all three times. tT3 .75 Default loop bandwidth setting tT1 tT2 Measured with input signal applied from 0 to 200 mVpp Tbit ps 100 40% 50% 60% Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: SN65DP159 SN75DP159 SN65DP159, SN75DP159 www.ti.com SLLSEJ2G – JULY 2015 – REVISED MARCH 2020 HDMI and DVI Main Link Switching Characteristics (continued) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER tSK_INTER TEST CONDITIONS MIN TYP MAX UNIT Inter-pair output skew Default setting for internal inter-pair skew adjust, HDMI_SEL/A1 = NC 0.2 Tch 0.15 Tbit tJITC1(1.4b) Total output clock jitter CLK = 297 MHz 0.25 Tbit tJITC1(2.0) Total output clock jitter DR = 6Gbps: CLK = 150 MHz 0.3 Tbit 3.4 Gbps < Rbit ≤ 3.712 Gbps 0.4 tSK_INTRA tJITD2 Total output data jitter See 3.712 Gbps < Rbit < 5.94 Gbps (1) 5.94 Gbps ≤ Rbit ≤ 6.0 Gbps 3.4 Gbps < Rbit ≤ 3.712 Gbps Total TMDS data lanes output differential voltage VOD_range 3.712 Gbps < Rbit < 5.94 Gbps 5.94 Gbps ≤ Rbit ≤ 6.0 Gbps (1) (2) Tbit 0.6 335 See (2) mV 150 2 –0.0332Rbit + 0.2312 Rbit + 0.1998 –19.66 × (Rbit2) + (106.74 × Rbit) + 209.58 Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: SN65DP159 SN75DP159 Submit Documentation Feedback 15 SN65DP159, SN75DP159 SLLSEJ2G – JULY 2015 – REVISED MARCH 2020 www.ti.com 7.11 AUX Switching Characteristics (Only for RGZ Package) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 0.4 UNIT UIMAN Manchester transaction unit interval 0.6 µs tAUXjitter_TX Cycle-to-cycle jitter time at transmit pins 0.08 UIMAN tAUXjitter_RX Cycle-to-cycle jitter time receive pins 0.05 UIMAN 7.12 HPD Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN tPD(HPD) Propagation delay from HPD_SNK to HPD_SRC; rising edge and falling edge See Figure 14; not valid during switching time tT(HPD) HPD logical disconnected timeout See Figure 15 TYP MAX UNIT 40 120 ns 2 ms 7.13 DDC and I2C Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP UNIT 300 ns 300 ns Rise time of both SDA and SCL signals tf Fall time of both SDA and SCL signals tHIGH Pulse duration, SCL high 0.6 μs tLOW Pulse duration, SCL low 1.3 μs tSU1 Setup time, SDA to SCL 100 ns Setup time, SCL to start condition 0.6 μs tHD,STA Hold time, start condition to SCL 0.6 μs tST,STO Setup time, SCL to stop condition 0.6 μs t(BUF) Bus free time between stop and start condition. 1.3 μs tPLH1 Source-to-sink: 100-kbps pattern; Propagation delay time, low-to-high-level output Cb(Sink) = 400-pF (1); See Figure 18 360 ns tPHL1 Propagation delay time, high-to-low-level output 230 ns tPLH2 Sink to Source: 100-kbps pattern; Propagation delay time, low-to-high-level output Cb(Source) = 100-pF (1); See Figure 19 250 ns tPHL2 Propagation delay time, high-to-low-level output 200 ns tST, (1) 16 STA Vcc = 3.3-V MAX tr Cb = total capacitance of one bus line in pF. Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: SN65DP159 SN75DP159 SN65DP159, SN75DP159 www.ti.com SLLSEJ2G – JULY 2015 – REVISED MARCH 2020 7.14 Typical Characteristics 200 350 180 300 160 140 200 Current (mA) Current (mA) 250 1.1 V 3.3 V 150 120 1.1 V 3.3 V 100 80 60 100 40 50 20 0 0 0 0.5 1 1.5 2 2.5 3 3.5 4 Data Rate (Gbps) 4.5 5 5.5 0 6 0.5 1 1.5 2 D001 Figure 1. Current vs Data Rate in Retimer Mode 2.5 3 3.5 4 Data Rate (Gbps) 4.5 5 5.5 6 D002 Figure 2. Current vs Data Rate in Redriver Mode 1600 VOD No Term VOD 150 to 300 : VOD 75 to 150 : 1400 VOD (mVpp) 1200 1000 800 600 400 200 0 4 4.5 5 5.5 6 6.5 Vsadj (k:) 7 7.5 8 D003 Figure 3. VOD vs Vsadj 8 Parameter Measurement Information VTERM 3.3V 50Q 50Q 75-200nF 50Q 50Q 0.5 pF D+ VD+ VID Receiver Driver D75-200nF Y VY Z VD- VID = VD+ - VD- VOD = VY - VZ VICM = (VD+ + VD-) 2 VOC = (VY + VZ) 2 VZ Figure 4. TMDS Main Link Test Circuit Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: SN65DP159 SN75DP159 Submit Documentation Feedback 17 SN65DP159, SN75DP159 SLLSEJ2G – JULY 2015 – REVISED MARCH 2020 www.ti.com Parameter Measurement Information (continued) 2.2 V VTERM VID 1.8 V VID+ VID(pp) 0V VID± tPHL tPLH 80% 80% VOD VOD(pp) 0V 20% tf 20% tr Figure 5. Input and Output Timing Measurements tSK1(T) tSK1(T) TMDS_OUTxp 50% TMDS_OUTxn tSK2(T) TMDS_OUTyp TMDS_OUTyn Figure 6. HDMI and DVI Sink TMDS Output Skew Measurements VOC ûVOC(SS) Figure 7. TMDS Main Link Common Mode Measurements 18 Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: SN65DP159 SN75DP159 SN65DP159, SN75DP159 www.ti.com SLLSEJ2G – JULY 2015 – REVISED MARCH 2020 Parameter Measurement Information (continued) VOD(PP) PRE_SEL=Z Vsadj = 7.06