SN65DSI83
SN65DSI83
SLLSEC1I – SEPTEMBER 2012 – REVISED OCTOBER
2020
SLLSEC1I – SEPTEMBER 2012 – REVISED OCTOBER 2020
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SN65DSI83 MIPI® DSI Bridge to FlatLink™ LVDS
Single-Channel DSI to Single-Link LVDS Bridge
1 Features
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3 Description
Implements MIPI® D-PHY version 1.00.00 physical
layer front-end and display serial interface (DSI)
version 1.02.00
Single channel DSI receiver configurable for 1, 2,
3, or 4 D-PHY data lanes per channel operating up
to 1 Gbps/lane
Supports 18 bpp and 24 bpp DSI video packets
with RGB666 and RGB888 formats
Max resolution up to 60 fps WUXGA
1920 × 1200 at 18 bpp and 24 bpp color with
reduced blanking. suitable for 60 fps 1366 × 768 /
1280 × 800 at 18 bpp and 24 bpp
FlatLink™ output for single-link LVDS
Supports single channel DSI to single-link LVDS
operating mode
LVDS Output Clock Range of 25 MHz to 154 MHz
LVDS pixel clock may be sourced from freerunning continuous D-PHY clock or external
reference clock (REFCLK)
1.8-V main VCC power supply
Low power features include shutdown mode,
reduced LVDS output voltage swing, common
mode, and MIPI ultra-low power state (ULPS)
support
LVDS channel swap, LVDS PIN order reverse
feature for ease of PCB routing
ESD rating ±2 kV (HBM)
Packaged in 64-pin 5-mm × 5-mm nFBGA (ZXH)
Temperature range: –40°C to 85°C
The SN65DSI83 DSI to FlatLink bridge device
features a single-channel MIPI D-PHY receiver frontend configuration with four lanes per channel
operating at 1 Gbps per lane; a maximum input
bandwidth of 4 Gbps. The bridge decodes MIPI DSI
18 bpp RGB666 and 24 bpp RGB888 packets and
converts the formatted video data stream to a
FlatLink-compatible LVDS output operating at pixel
clocks operating from 25 MHz to 154 MHz, offering a
Single-Link LVDS with four data lanes per link.
The SN65DSI83 device can support up to WUXGA
1920 × 1200 at 60 frames per second, at 24 bpp with
reduced blanking. The SN65DSI83 device is also
suitable for applications using 60 fps 1366 × 768 /
1280 × 800 at 18 bpp and 24 bpp. Partial line
buffering is implemented to accommodate the data
stream mismatch between the DSI and LVDS
interfaces.
Designed
with
industry-compliant
interface
technology, the SN65DSI83 device is compatible with
a wide range of microprocessors, and is designed
with a range of power management features including
low-swing LVDS outputs, and the MIPI defined ultralow power state (ULPS) support.
The SN65DSI83 device is implemented in a small
outline 5-mm × 5-mm nFBGA at 0.5-mm pitch
package, and operates across a temperature range
from –40°C to 85°C.
Device Information (1)
2 Applications
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PC & notebooks
Tablets
Connected peripherals & printers
PART
NUMBER
PACKAGE
BODY SIZE
SN65DSI83
nFBGA (64)
5.00 mm × 5.00 mm
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
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Incorporated
intellectual
property
matters
and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings (1) ................................... 6
6.2 ESD Ratings............................................................... 6
6.3 Recommended Operating Conditions.........................6
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics.............................................7
6.6 Timing Requirements.................................................. 8
6.7 Switching Characteristics..........................................10
7 Detailed Description......................................................13
7.1 Overview................................................................... 13
7.2 Functional Block Diagram......................................... 13
7.3 Feature Description...................................................14
7.4 Device Functional Modes..........................................15
7.5 Programming............................................................ 22
7.6 Register Maps...........................................................24
8 Application and Implementation.................................. 30
8.1 Application Information............................................. 30
8.2 Typical Application.................................................... 31
9 Power Supply Recommendations................................37
9.1 VCC Power Supply.................................................... 37
9.2 VCORE Power Supply.............................................. 37
10 Layout...........................................................................38
10.1 Layout Guidelines................................................... 38
10.2 Layout Example...................................................... 39
11 Device and Documentation Support..........................40
11.1 Receiving Notification of Documentation Updates.. 40
11.2 Community Resources............................................40
11.3 Trademarks............................................................. 40
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (June 2018) to Revision I (October 2020)
Page
• Changed from u*jrBGA ZQE to nFBGA ZXH......................................................................................................1
• Changed u*jr ZQE to nFBGA ZXH..................................................................................................................... 4
• Changed u*jr ZQE to nFBGA ZXH. Updated thermal information...................................................................... 6
• Changed u*jr ZQE to nFBGA ZXH................................................................................................................... 38
Changes from Revision G (June 2015) to Revision H (June 2018)
Page
• Deleted figure RESET and Initialization Timing Definition While VCC is High ..................................................10
• Changed the paragraph following Figure 7-3 .................................................................................................. 15
• Changed Recommended Initialization Sequence To: Initialization Sequence ................................................. 16
• Changed Table 7-2 .......................................................................................................................................... 16
• Changed item 3 in Video Stop and Restart Sequence From: Drive all DSI input lanes including DSI CLK lane
to LP11. To: Drive all DSI data lanes to LP11, but keep the DSI CLK lanes in HS. ......................................... 30
Changes from Revision F (May 2015) to Revision G (June 2015)
Page
• Moved Recommended Initialization Setup Sequence ..................................................................................... 16
• Changed SN65DSI83 DSI Lane Merging Illustration back to original image....................................................19
Changes from Revision E (October 2013) to Revision F (May 2015)
Page
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ............................................................................................................................................................... 1
• Updated data sheet to new TI standards, added sections, and rearranged content ......................................... 1
• Updated the SN65DSI83 FlatLink Timing Definitions diagram......................................................................... 10
• Changed Functional Block Diagram ................................................................................................................ 13
• Changed SN65DSI83 DSI Lane Merging Illustration .......................................................................................19
• Changed from: 1366 × 768 WXGA to:1280 × 800 WXGA ...............................................................................31
• Changed Design Parameters table values....................................................................................................... 31
2
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SN65DSI83
SLLSEC1I – SEPTEMBER 2012 – REVISED OCTOBER 2020
Changed Detailed Design Procedure values and text...................................................................................... 32
Changed Example Script subsection ...............................................................................................................35
Changes from Revision D (December 2012) to Revision E (October 2013)
Page
• Changed status from Product Preview to Production Data................................................................................ 1
Changes from Revision A (September 2012) to Revision B (December 2012)
Page
• Changed the value of VOH From: 1.3 MIN To: 1.25 MIN.....................................................................................7
• Changed the ICC TYP value From: TBD To: 77 and MAX value From: TBD To: 112 .........................................7
• Added a TYP value of 7.7 to IULPS .....................................................................................................................7
• Changed the IRST TYP value From: 0.05 To: 0.04 and MAX value From: 0.2 To: 0.06...................................... 7
• changed the values of |VOD|.............................................................................................................................. 7
• Changed the values of VOC(SS) for test conditions CSR 0x19.6 = 0................................................................... 7
• Added table note 2..............................................................................................................................................7
• Added table note 3..............................................................................................................................................7
• Changed the tsetup and thold NOM value of 1.5 to a MIN value of 1.5................................................................. 8
• Changed the SWITCHING CHARACTERISTICS table....................................................................................10
• Changed the description of CHA_LVDS_VOD_SWING................................................................................... 24
Changes from Revision * (August 2012) to Revision A (September 2012)
Page
• Changed Feature From: Max Resolution up to 60 fps WUXGA 1920 × 1200 at 18 and 24 bpp Color with
Reduced Blanking. Suitable for 60 fps 1366 × 768 at 18 and 24 bpp To: Max Resolution up to 60 fps WUXGA
1920 × 1200 at 18 and 24 bpp Color with Reduced Blanking. Suitable for 60 fps 1366 × 768 / 1280 × 800 at
18 and 24 bpp.....................................................................................................................................................1
• Changed text in paragraph two of the Description From: "applications using 60 fps 1366 × 768 at 18 bpp and
24 bpp." To: "applications using 60 fps 1366 × 768 / 1280 × 800 at 18 bpp and 24 bpp."..................................1
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5 Pin Configuration and Functions
A
B
C
D
E
F
G
H
J
9
VCC
GND
A_Y0N
A_Y1N
A_Y2N
A_CLKN
A_Y3N
GND
IRQ
8
GND
VCC
A_Y0P
A_Y1P
A_Y2P
A_CLKP
A_Y3P
RSVD1
VCORE
7
NC
NC
DA3P
DA3N
6
NC
NC
VCC
VCC
VCC
DA2P
DA2N
5
NC
NC
GND
VCC
GND
DACP
DACN
4
NC
NC
GND
GND
DA1P
DA1N
3
NC
NC
DA0P
DA0N
2
GND
RSVD2
NC
NC
NC
NC
NC
REFCLK
VCC
1
ADDR
EN
NC
NC
NC
NC
NC
SCL
SDA
Not to scale
ZXH Package 64-Pin nFBGA (Top View)
Table 5-1. Pin Functions
PIN
NAME
4
NO.
A_CLKN
F9
A_CLKP
F8
ADDR
A1
A_Y0N
C9
A_Y0P
C8
A_Y1N
D9
A_Y1P
D8
A_Y2N
E9
A_Y2P
E8
A_Y3N
G9
A_Y3P
G8
DA0N
J3
DA0P
H3
I/O
DESCRIPTION
LVDS output
CMOS I/O
FlatLink Channel A LVDS clock
Local I2C Interface Target Address Select. See Table 7-3. In normal operation, this pin is
an input. When the ADDR pin is programmed high, it must be tied to the same 1.8-V
power rails where the SN65DSI83 VCC 1.8-V power rail is connected.
FlatLink Channel A LVDS data output 0
FlatLink Channel A LVDS data output 1
LVDS output
FlatLink Channel A LVDS data output 2
FlatLink Channel A LVDS data output 3. A_Y3P and A_Y3N shall be left NC for 18 bpp
panels
LVDS Input (HS)
CMOS Input (LS)
MIPI D-PHY Channel A Data Lane 0; data rate up to 1 Gbps
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Table 5-1. Pin Functions (continued)
PIN
NAME
I/O
NO.
DA1N
J4
DA1P
H4
DA2N
J6
DA2P
H6
DA3N
J7
DA3P
H7
DESCRIPTION
MIPI D-PHY Channel A Data Lane 1; data rate up to 1 Gbps
MIPI D-PHY Channel A Data Lane 2; data rate up to 1 Gbps
(failsafe)
MIPI D-PHY Channel A Data Lane 3; data rate up to 1 Gbps
DACN
J5
DACP
H5
EN
B1
CMOS Input with
pullup (failsafe)
A2, A8, B9, D5, E4,
F4, F5, H9
Power Supply
Reference ground
IRQ
J9
CMOS Output
Interrupt signal
NC
B3, A3, B4, A4, B5,
A5, B6, A6, B7, A7,
C2, C1, D2, D1, F2,
F1, G2, G1, E2, E1
No connects
These pins must not be connected to any signal, power or ground.
REFCLK
H2
CMOS Input
(Failsafe)
Optional external reference clock for LVDS pixel clock. If an external reference clock is not
used, this pin must be pulled to GND with an external resistor. The source of the reference
clock must be placed as close as possible with a series resistor near the source to reduce
EMI.
RSVD1
H8
CMOS Input/Output
with pulldown
Reserved. This pin must be left unconnected for normal operation.
RSVD2
B2
CMOS Input with
pulldown
Reserved. This pin must be left unconnected for normal operation.
SCL
H1
CMOS Input
(Failsafe)
SDA
J1
Open Drain I/O
(failsafe)
VCC
A9, B8, D6, E5, E6,
F6, J2
GND
VCORE
MIPI D-PHY Channel A Clock Lane; operates up to 500 MHz
J8
Power Supply
Chip enable and reset. Device is reset (shutdown) when EN is low.
Local I2C interface clock
Local I2C interface bidirectional data signal
1.8-V power supply
1.1-V output from voltage regulator. This pin must have a 1-µF external capacitor to GND.
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6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature (unless otherwise noted)
MIN
MAX
UNIT
–0.3
2.175
V
CMOS input pins
–0.5
2.175
V
DSI input pins (DA × P/N, DB × P/N)
–0.4
1.4
V
–65
105
°C
Supply voltage, VCC
Input voltage
Storage temperature, Tstg
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101(2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VCC
VCC power supply
VPSN
Supply noise on any VCC pin
TA
Operating free-air temperature
TCASE
Case temperature
VDSI_PIN
DSI input pin voltage range
ZL
LVDS output differential impedance
MIN
NOM
MAX
UNIT
1.65
1.8
1.95
V
f(noise) > 1
MHz
0.05
V
–40
85
92.2
°C
–50
1350
mV
90
132
Ω
6.4 Thermal Information
SN65DSI83
THERMAL
METRIC(1)
ZXH (nFBGA)
UNIT
64 PINS
RθJA
Junction-to-ambient thermal resistance
55.1
RθJC(top)
Junction-to-case (top) thermal resistance
30.6
RθJB
Junction-to-board thermal resistance
31.0
ψJT
Junction-to-top characterization parameter
0.8
ψJB
Junction-to-board characterization parameter
30.8
(1)
6
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VIL
Low-level control signal input voltage
VIH
High-level control signal input voltage
VOH
High-level output voltage
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
0.3 × VCC
0.7 × VCC
IOH = –4 mA
V
1.25
VOL
Low-level output voltage
IOL = 4 mA
0.4
ILKG
Input failsafe leakage current
VCC = 0; VCC(PIN) = 1.8 V
±30
IIH
High-level input current
IIL
Low-level input current
Any input pin
±30
IOZ
High-impedance output current
Any output pin
±10
IOS
Short-circuit output current
Any output driving GND short
ICC
Device active current
See (2)
77
±20
112
IULPS
Device standby current
All data and clock lanes are in ultra-low
power state (ULPS)
7.7
10
IRST
Shutdown current
EN = 0
0.04
0.06
REN
EN control input resistor
200
μA
mA
mA
kΩ
MIPI DSI INTERFACE
VIH-LP
LP receiver input high threshold
VIL-LP
LP receiver input low threshold
|VID|
HS differential input voltage
|VIDT|
HS differential input voltage threshold
VIL-ULPS
LP receiver input low threshold; ultra-low
power state (ULPS)
VCM-HS
HS common mode voltage; steady-state
ΔVCM-HS
HS common mode peak-to-peak variation
including symbol delta and interference
VIH-HS
HS single-ended input high voltage
See Figure 6-2
880
550
70
270
50
300
70
330
mV
100
See Figure 6-2
VIL-HS
HS single-ended input low voltage
VTERM-EN
HS termination enable; single-ended input Termination is switched simultaneous for
voltage (both Dp and Dn apply to enable) Dn and Dp
RDIFF-HS
HS mode differential input impedance
460
–40
450
80
125
Ω
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over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
TYP(1)
MAX
CSR 0x19.3:2 = 00
100-Ω near-end termination
180
245
313
CSR 0x19.3:2 = 01
100-Ω near-end termination
215
293
372
CSR 0x19.3:2 = 10
100-Ω near-end termination
250
341
430
290
389
488
150
204
261
CSR 0x19.3:2 = 01
200-Ω near-end termination
200
271
346
CSR 0x19.3:2 = 10
200-Ω near-end termination
250
337
428
CSR 0x19.3:2 = 11
200-Ω near-end termination
300
402
511
CSR 0x19.3:2 = 00
100-Ω near-end termination
140
191
244
CSR 0x19.3:2 = 01
100-Ω near-end termination
168
229
290
CSR 0x19.3:2 = 01
100-Ω near-end termination
195
266
335
226
303
381
117
159
204
CSR 0x19.3:2 = 01
200-Ω near-end termination
156
211
270
CSR 0x19.3:2 = 10
200-Ω near-end termination
195
263
334
CSR 0x19.3:2 = 11
200-Ω near-end termination
234
314
399
TEST CONDITIONS
UNIT
FlatLink LVDS OUTPUT
CSR 0x19.3:2 = 11
Steady-state differential output voltage for 100-Ω near-end termination
A_Y x P/N and B_Y x P/N
CSR 0x19.3:2 = 00
200-Ω near-end termination
|VOD|
mV
CSR 0x19.3:2 = 11
Steady-state differential output voltage for 100-Ω near-end termination
A_CLKP/N and B_CLKP/N
CSR 0x19.3:2 = 00
200-Ω near-end termination
Δ|VOD|
Change in steady-state differential output
voltage between opposite binary states
VOC(SS)
Steady state common-mode output
voltage (3)
VOC(PP)
Peak-to-peak common-mode output
voltage
RLVDS_DIS
Pulldown resistance for disabled LVDS
outputs
(1)
(2)
(3)
mV
RL = 100 Ω
35
CSR 0x19.6 = 1 and CSR 0x1B.6 = 1
(see Figure 6-3)
CSR 0x19.6 = 0 (see Figure 6-3)
0.8
0.9
1
1.15
1.25
1.35
See Figure 6-3
35
1
mV
V
mV
kΩ
All typical values are at VCC = 1.8 V and TA = 25°C.
SN65DSI83: SINGLE Channel DSI to SINGLE Channel DSI, 1280 × 800
• Number of LVDS lanes = 3 data lanes + 1 CLK lane
• Number of DSI lanes = 4 data lanes + 1 CLK lane
• LVDS CLK OUT = 83 M
• DSI CLK = 500 M
• RGB888, LVDS 18 bpp
Maximum values are at VCC = 1.95 V and TA = 85°C
Tested at VCC = 1.8 V , TA = –40°C for MIN, TA = 25°C for TYP, TA = 85°C for max.
6.6 Timing Requirements
MIN
8
I2C
f(I2C)
Local
fHS_CLK
DSI HS clock input frequency
input frequency
tsetup
DSI HS data to clock setup time
40
0.15
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TYP
MAX
UNIT
400
kHz
500
MHz
UI(1)
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MIN
thold
(1)
DSI HS data to clock hold time; see Figure 6-1
TYP
MAX
UNIT
0.15
The unit interval (UI) is one half of the period of the HS clock; at 500 MHz the minimum setup and hold time is 150 ps.
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6.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
300
ps
DSI
tGS
DSI LP glitch suppression pulse width
LVDS
tc
Output clock period
tw
High-level output clock (CLK) pulse duration
6.49
t0
Delay time, CLK↑ to 1st serial bit position
–0.15
0.15
ns
t1
Delay time, CLK↑ to 2nd serial bit position
1 / 7 tc – 0.15
1 / 7 tc + 0.15
ns
t2
Delay time, CLK↑ to 3rd serial bit position
2 / 7 tc – 0.15
2 / 7 tc + 0.15
ns
3 / 7 tc – 0.15
3 / 7 tc + 0.15
ns
4 / 7 tc – 0.15
4 / 7 tc + 0.15
ns
4th
tc = 6.49 ns;
Input clock jitter < 25 ps
(REFCLK)
serial bit position
40
4 / 7 tc
ns
ns
t3
Delay time, CLK↑ to
t4
Delay time, CLK↑ to 5th serial bit position
t5
Delay time, CLK↑ to 6th serial bit position
5 / 7 tc – 0.15
5 / 7 tc + 0.15
ns
t6
Delay time, CLK↑ to 7th serial bit position
6 / 7 tc – 0.15
6 / 7 tc + 0.15
ns
tr
Differential output rise time
tf
Differential output fall time
180
500
ps
See Figure 6-4
EN, ULPS, RESET
ten
Enable time from EN or ULPS
tdis
Disable time to standby
1
treset
Reset Time
10
FREFCLK
REFCLK freqeuncy. Supported frequencies:
25 MHz to 154 MHz
25
154
100 ps
1 ns
s
50
ps
tc(o) = 12.9 ns
0.1
ms
ms
REFCLK
tr, tf
REFCLK rise and fall time
tpj
REFCLK peak-to-peak phase jitter
Duty
REFCLK duty cycle
40%
50%
60%
0.5%
1%
2%
MHz
REFCLK or DSI CLK (DACP/N, DBCP/N)
SSC_CLKIN
(1)
(2)
SSC enabled input CLK center spread depth (2)
Modulation frequency range
30
60
kHz
All typical values are at VCC = 1.8 V and TA = 25°C
For EMI reduction purpose, the SN65DSI83 device supports the center spreading of the LVDS CLK output through the REFCLK or DSI
CLK input. The center spread CLK input to the REFCLK or DSI CLK is passed through to the LVDS CLK output A_CLKP and A_CLKN,
or B_CLKP and B_CLKN, or both.
Figure 6-1. DSI HS Mode Receiver Timing Definitions
10
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1.3V
LP-RX
Input HIGH
VIH-LP
VIL-LP
VIH-HS
VID
LP-RX
Input LOW
VCM-HS(MAX)
HS-RX
Common Mode
Range
VCM-HS(MIN)
GND
VIL-HS
High Speed (HS) Mode
Receiver
Low Power (LP)
Mode Receiver
Figure 6-2. DSI Receiver Voltage Definitions
49.9 ? ± 1% (2 PLCS)
A_YnP
VOD
VOC
A_YnN
100 %
80%
VOD(H)
0V
VOD(L)
20%
0%
tf
tr
VOC(PP)
VOC(SS)
VOC(SS)
0V
Figure 6-3. Test Load and Voltage Definitions for FlatLink Outputs
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CLK
t6
t5
t4
t3
t2
t1
t0
Yn
VOD(H)
0.00V
VOD(L)
t0-6
Figure 6-4. SN65DSI83 FlatLink Timing Definitions
ULPS (LP00 State)
DSI lane
ten
tdis
A_CLKP/N
(LVDS_CHA_CLK)
A. See Section 7.3.2 for the ULPS entry and exit sequence.
B. ULPS entry and exit protocol and timing requirements must be met per MIPI DPHY specification.
Figure 6-5. ULPS Timing Definition
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7 Detailed Description
7.1 Overview
The SN65DSI83 DSI to FlatLink bridge device features a single-channel MIPI® D-PHY receiver front-end
configuration with four lanes per channel operating at 1 Gbps per lane; a maximum input bandwidth of 4 Gbps.
The bridge decodes MIPI DSI 18 bpp RGB666 and 24 bpp RGB888 packets and converts the formatted video
data stream to a FlatLink compatible LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz,
offering a Single-Link LVDS with four data lanes per link.
7.2 Functional Block Diagram
AVCC
ERR
AGND
VCC
GND
ULPS
LPRX
DA0P
DA0N
LANE ERR
MERGE
8
18
HSRX
18
DATA LANE 0
LVDS
SERIALIZER
EOT
DA1P
DA1N
DA2P
DA2N
DA3P
DA3N
DATA LANE 1
(Circuit same as DATA LANE 0)
8
DATA LANE 2
(Circuit same as DATA LANE 0)
8
DATA LANE 3
(Circuit same as DATA LANE 0)
8
DACN
32
DSI PACKET
PROCESSORS
DE
VS
HS
CHANNEL
FORMATTER
ULPS
ULPS
DACP
SOT
A_Y0P
A_Y0N
A_Y1P
A_Y1N
A_Y2P
A_Y2N
A_CLKP
A_CLKN
A_Y3P
A_Y3N
PARTIAL
LPRX
LPRX
HSRX
HSRX
LVDSPLL
PLL
Lock
CLOCK CIRCUITS
PIXEL CLOCK
CLK LANE
PLL Lock
Logic Clocks
SCL
CSR
HS Clock
Sourced
M /N Pixel
Clock PLL
2
LOCAL I2C
CSR READ
CSR WRITE
SDA
IRQ
ADDR
Clock Dividers
Reset
SN65DSI83
REFCLK
EN
RSVD1
RSVD2
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7.3 Feature Description
7.3.1 Clock Configurations and Multipliers
The FlatLink LVDS clock may be derived from the DSI channel A clock, or from an external reference clock
source. When the MIPI D-PHY channel A HS clock is used as the LVDS clock source, the D-PHY clock lane
must operate in HS free-running (continuous) mode. This feature eliminates the need for an external reference
clock reducing system costs
The reference clock source is selected by HS_CLK_SRC (CSR 0x0A.0) programmed through the local I2C
interface. If an external reference clock is selected, it is multiplied by the factor in REFCLK_MULTIPLIER (CSR
0x0B.1:0) to generate the FlatLink LVDS output clock. When an external reference clock is selected, it must be
between 25 MHz and 154 MHz. If the DSI channel A clock is selected, it is divided by the factor in
DSI_CLK_DIVIDER (CSR 0x0B.7:3) to generate the FlatLink LVDS output clock. Additionally,
LVDS_CLK_RANGE (CSR 0x0A.3:1) and CH_DSI_CLK_RANGE(CSR 0x12) must be set to the frequency
range of the FlatLink LVDS output clock and DSI Channel A input clock respectively for the internal PLL to
operate correctly. After these settings are programmed, PLL_EN (CSR 0x0D.0) must be set to enable the
internal PLL.
7.3.2 ULPS
The SN65DSI83 device supports the MIPI defined ULPS. While the device is in the ULPS, the CSR registers are
accessible via I2C interface. ULPS sequence must be issued to all active DSI CLK and, or DSI data lanes of the
enabled DSI channels for the SN65DSI83 device to enter the ULPS. The following sequence must be followed to
enter and exit the ULPS.
1. The host issues a ULPS entry sequence to all DSI CLK and data lanes enabled.
2. When the host is ready to exit the ULPS mode, the host issues a ULPS exit sequence to all DSI CLK and
data lanes that need to be active in normal operation.
3. Wait for the PLL_LOCK bit (CSR 0x0A.7) to be set.
4. Set the SOFT_RESET bit (CSR 0x09.0).
5. Device resumes normal operation (that is, video streaming resumes on the panel).
7.3.3 LVDS Pattern Generation
The SN65DSI83 device supports a pattern generation feature on LVDS channels. This feature can be used to
test the LVDS output path and LVDS panels in a system platform. The pattern generation feature can be enabled
by setting the CHA_TEST_PATTERN bit at address 0x3C. No DSI data is received while the pattern generation
feature is enabled.
There are three modes available for LVDS test pattern generation. The mode of test pattern generation is
determined by register configuration, as shown in Table 7-1.
Table 7-1. Video Registers
ADDRESS BIT
14
REGISTER NAME
0x20.7:0
CHA_ACTIVE_LINE_LENGTH_LOW
0x21.3:0
CHA_ACTIVE_LINE_LENGTH_HIGH
0x24.7:0
CHA_VERTICAL_DISPLAY_SIZE_LOW
0x25.3:0
CHA_VERTICAL_DISPLAY_SIZE_HIGH
0x2C.7:0
CHA_HSYNC_PULSE_WIDTH_LOW
0x2D.1:0
CHA_HSYNC_PULSE_WIDTH_HIGH
0x30.7:0
CHA_VSYNC_PULSE_WIDTH_LOW
0x31.1:0
CHA_VSYNC_PULSE_WIDTH_HIGH
0x34.7:0
CHA_HORIZONTAL_BACK_PORCH
0x36.7:0
CHA_VERTICAL_BACK_PORCH
0x38.7:0
CHA_HORIZONTAL_FRONT_PORCH
0x3A.7:0
CHA_VERTICAL_FRONT_PORCH
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7.4 Device Functional Modes
7.4.1 Reset Implementation
When EN is deasserted (low), the SN65DSI83 device is in shutdown or reset state. In this state, CMOS inputs
are ignored, the MIPI D-PHY inputs are disabled and outputs are high impedance. It is critical to transition the
EN input from a low level to a high level after the VCC supply has reached the minimum operating voltage, as
shown in Figure 7-1. This is achieved by a control signal to the EN input, or by an external capacitor connected
between EN and GND.
VCC
1.65V
EN
tVCC
ten
Figure 7-1. Cold Start VCC Ramp up to EN
When implementing the external capacitor, the size of the external capacitor depends on the power-up ramp of
the VCC supply, where a slower ramp-up results in a larger value external capacitor. See the latest reference
schematic for the SN65DSI83 device and, or consider approximately 200-nF capacitor as a reasonable first
estimate for the size of the external capacitor.
Both EN implementations are shown in Figure 7-2 and Figure 7-3.
VCC
GPO
EN
C
EN
REN =200 kΩ
C
controller
SN65DSI83
SN65DSI83
Figure 7-3. EN Input from Active Controller
Figure 7-2. External Capacitor Controlled EN
When the SN65DSI83 is reset while VCC is high, the EN pin must be held low for at least 10 ms before being
asserted high as described in Table 7-2 to be sure that the device is properly reset. The DSI CLK lane MUST be
in HS and the DSI data lanes MUST be driven to LP11 while the device is in reset before the EN pin is asserted
per the timing described in Table 7-2.
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7.4.2 Initialization Sequence
Use the following initialization sequence to setup the SN65DSI83. This sequence is required for proper operation
of the device. Steps 9 through 11 in the sequence are optional.
Table 7-2. Initialization Sequence
INITIALIZATION
SEQUENCE
NUMBER
INITIALIZATION SEQUENCE DESCRIPTION
Init seq 1
Power on
Init seq 2
After power is applied and stable, the DSI CLK lanes MUST be in HS state and the DSI data lanes MUST be driven
to LP11 state
Init seq 3
Set EN pin to Low
Wait 10 ms (1)
Init seq 4
Tie EN pin to High
Wait 10 ms (1)
Init seq 5
Initialize all CSR registers to their appropriate values based on the implementation (The SN65DSI8x is not
functional until the CSR registers are initialized)
Init seq 6
Set the PLL_EN bit (CSR 0x0D.0)
Wait 10 ms (1)
Init seq 7
Set the SOFT_RESET bit (CSR 0x09.0)
Wait 10 ms (1)
Init seq 8
Change DSI data lanes to HS state and start DSI video stream
Wait 5 ms (1)
Init seq 9
Read back all resisters and confirm they were correctly written
Init seq 10
Wait 1 ms
Init seq 11
(1)
Write 0xFF to CSR 0xE5 to clear the error registers
(1)
Read CSR 0xE5. If CSR 0xE5!= 0x00, then go back to step #2 and re-initialize
Minimum recommended delay. It is fine to exceed these.
7.4.3 LVDS Output Formats
The SN65DSI83 device processes DSI packets and produces video data driven to the FlatLink LVDS interface in
an industry standard format. Single-Link LVDS is supported by the SN65DSI83 device. During conditions such
as the default condition, and some video synchronization periods, where no video stream data is passing from
the DSI input to the LVDS output, the SN65DSI83 device transmits zero value pixel data on the LVDS outputs
while maintaining transmission of the vertical sync and horizontal sync status.
Figure 7-4 illustrates a Single-Link LVDS 18 bpp application.
Figure 7-5 illustrates a Single-Link 24 bpp application using Format 2, controlled by CHA_24BPP_FORMAT1
(CSR 0x18.1). In data Format 2, the two MSB per color are transferred on the Y3P/N LVDS lane.
Figure 7-6 illustrates a 24 bpp Single-Link application using Format 1. In data Format 1, the two LSB per color
are transferred on the Y3P/N LVDS lane.
Figure 7-7 illustrates a Single-Link LVDS application where 24 bpp data is received from DSI and converted to
18 bpp data for transmission to an 18 bpp panel. This application is configured by setting
CHA_24BPP_FORMAT1 (CSR 0x18.1) to 1 and CHA_24BPP_MODE (CSR 0x18.3) to 0. In this configuration,
the SN65DSI83 device does not transmit the 2 LSB per color since the Y3P and Y3N LVDS lane is disabled.
Note
Figure 7-4, Figure 7-5, Figure 7-6, and Figure 7-7 only illustrate a few example applications for the
SN65DSI83 device. Other applications are also supported.
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A_CLKP/N
cycle ‘n-1’
cycle ‘n’
A_Y0P/N
G0
R5
R4
R3
R2
R1
R0
A_Y1P/N
B1
B0
G5
G4
G3
G2
G1
A_Y2P/N
DE
VS
HS
B5
B4
B3
B2
A_Y3P/N
DE = Data Enable; A_Y3P/N are Output Low
Figure 7-4. FlatLink Output Data; Single-Link 18 bpp
A_CLKP/N
cycle ‘n-1’
cycle ‘n’
A_Y0P/N
G0
R5
R4
R3
R2
R1
R0
A_Y1P/N
B1
B0
G5
G4
G3
G2
G1
A_Y2P/N
DE
VS
HS
B5
B4
B3
B2
A_Y3P/N
0
B7
B6
G7
G6
R7
R6
DE = Data Enable
Figure 7-5. FlatLink Output Data (Format 2); Single-Link 24 bpp
A_CLKP/N
cycle ‘n-1’
cycle ‘n’
A_Y0P/N
G2
R7
R6
R5
R4
R3
R2
A_Y1P/N
B3
B2
G7
G6
G5
G4
G3
A_Y2P/N
DE
VS
HS
B7
B6
B5
B4
A_Y3P/N
0
B1
B0
G1
G0
R1
R0
DE = Data Enable
Figure 7-6. FlatLink Output Data (Format 1); Single-Link 24 bpp
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A_CLKP/N
cycle ‘n-1’
cycle ‘n’
A_Y0P/N
G2
R7
R6
R5
R4
R3
R2
A_Y1P/N
B3
B2
G7
G6
G5
G4
G3
A_Y2P/N
DE
VS
HS
B7
B6
B5
B4
A_Y3P/N
DE = Data Enable; A_Y3P and A_Y3N are output low; A_Y3P and A_Y3N are output low
Figure 7-7. FlatLink Output Data (Format 1); 24 bpp to Single-Link 18 bpp Conversion
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7.4.4 DSI Lane Merging
The SN65DSI83 device supports four DSI data lanes, and may be configured to support 1, 2, or 3 DSI data
lanes per channel. Unused DSI input pins on the SN65DSI83 device must be left unconnected or driven to LP11
state. The bytes received from the data lanes are merged in HS mode to form packets that carry the video
stream. DSI data lanes are bit and byte aligned.
Figure 7-8 shows the lane merging function for each channel; 4-, 3-, and 2-lane modes.
HS BYTES TRANSMITTED (n) IS INTEGER MULTIPLE OF 3
HS BYTES TRANSMITTED (n) IS INTEGER MULTIPLE OF 4
LANE 0
SOT
BYTE 0
BYTE 4
BYTE 8
BYTE n-4
EOT
LANE 0
SOT
BYTE 0
BYTE 3
BYTE 6
BYTE n-3
EOT
LANE 1
SOT
BYTE 1
BYTE 5
BYTE 9
BYTE n-3
EOT
LANE 1
SOT
BYTE 1
BYTE 4
BYTE 7
BYTE n-2
EOT
LANE 2
SOT
BYTE 2
BYTE 6
BYTE 10
BYTE n-2
EOT
LANE 2
SOT
BYTE 2
BYTE 5
BYTE 8
BYTE n-1
EOT
LANE 3
SOT
BYTE 3
BYTE 7
BYTE 11
BYTE n-1
EOT
HS BYTES TRANSMITTED (n) IS 1 LESS THAN INTEGER MULTIPLE OF 3
HS BYTES TRANSMITTED (n) IS 1 LESS THAN INTEGER MULTIPLE OF 4
LANE 0
SOT
BYTE 0
BYTE 4
BYTE 8
BYTE n-3
EOT
LANE 1
SOT
BYTE 1
BYTE 5
BYTE 9
BYTE n-2
EOT
LANE 2
SOT
BYTE 2
BYTE 6
BYTE 10
BYTE n-1
EOT
LANE 3
SOT
BYTE 3
BYTE 7
BYTE 11
EOT
LANE 0
SOT
BYTE 0
BYTE 3
BYTE 6
BYTE n-2
EOT
LANE 1
SOT
BYTE 1
BYTE 4
BYTE 7
BYTE n-1
EOT
LANE 2
SOT
BYTE 2
BYTE 5
BYTE 8
EOT
HS BYTES TRANSMITTED (n) IS 2 LESS THAN INTEGER MULTIPLE OF 3
HS BYTES TRANSMITTED (n) IS 2 LESS THAN INTEGER MULTIPLE OF 4
LANE 0
SOT
BYTE 0
BYTE 4
BYTE 8
BYTE n-2
EOT
LANE 1
SOT
BYTE 1
BYTE 5
BYTE 9
BYTE n-1
EOT
LANE 2
SOT
BYTE 2
BYTE 6
BYTE 10
EOT
LANE 3
SOT
BYTE 3
BYTE 7
BYTE 11
EOT
LANE 0
SOT
BYTE 0
BYTE 3
BYTE 6
BYTE n-1
LANE 1
SOT
BYTE 1
BYTE 4
BYTE 7
EOT
LANE 2
SOT
BYTE 2
BYTE 5
BYTE 8
EOT
3 DSI Data Lane Configuration
HS BYTES TRANSMITTED (n) IS INTEGER MULTIPLE OF 2
HS BYTES TRANSMITTED (n) IS 3 LESS THAN INTEGER MULTIPLE OF 4
LANE 0
SOT
BYTE 0
BYTE 4
BYTE 8
BYTE n-1
LANE 1
SOT
BYTE 1
BYTE 5
BYTE 9
EOT
LANE 2
SOT
BYTE 2
BYTE 6
BYTE 10
EOT
LANE 3
SOT
BYTE 3
BYTE 7
BYTE 11
EOT
4 DSI Data Lane Configuration (default)
EOT
EOT
LANE 0
SOT
BYTE 0
BYTE 2
BYTE 4
BYTE n-2
EOT
LANE 1
SOT
BYTE 1
BYTE 3
BYTE 5
BYTE n-1
EOT
HS BYTES TRANSMITTED (n) IS 1 LESS THAN INTEGER MULTIPLE OF 2
LANE 0
SOT
BYTE 0
BYTE 2
BYTE 4
BYTE n-1
LANE 1
SOT
BYTE 1
BYTE 3
BYTE 5
EOT
2 DSI Data Lane Configuration
Figure 7-8. SN65DSI83 DSI Lane Merging Illustration
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7.4.5 DSI Pixel Stream Packets
The SN65DSI83 device processes 18 bpp (RGB666) and 24 bpp (RGB888) DSI packets on each channel, as
shown in Figure 7-9, Figure 7-10, andFigure 7-11.
2 Bytes
DATA TYPE (0x2E)
VIRTUAL CHANNEL
1 Byte
1 Byte
WORD COUNT
WORD COUNT Bytes
18 bpp Loosely Packed Pixel Stream
ECC
CRC CHECKSUM
(Variable Size Payload)
Packet Payload
Packet Header
1 Byte
01
2 Bytes
1 Byte
1 Byte
1 Byte
1 Byte
Packet Footer
1 Byte
1 Byte
1 Byte
1 Byte
2
7
2
7
2
7
2
7
2
7
2
7
2
7
2
7
2
7
R0
R5
G0
G5
B0
B5
R0
R5
G0
G5
B0
B5
R0
R5
G0
G5
B0
B5
6-bits
RED
6-bits
GREEN
6-bits
BLUE
6-bits
RED
First Pixel in Packet
6-bits
GREEN
6-bits
BLUE
6-bits
RED
6-bits
GREEN
Second Pixel in Packet
6-bits
BLUE
Third Pixel in Packet
Variable Size Payload (Three Pixels Per Nine Bytes of Payload)
Figure 7-9. 18 bpp (Loosely Packed) DSI Packet Structure
2 Bytes
DATA TYPE (0x1E)
VIRTUAL CHANNEL
1 Byte
1 Byte
WORD COUNT
WORD COUNT Bytes
18 bpp Packed Pixel Stream
ECC
0
R0
5
Packet Payload
1 Byte
6 7 0
R5 G0
6-bits
RED
CRC CHECKSUM
(Variable Size Payload)
Packet Header
1 Byte
2 Bytes
3
4
G5 B 0
6-bits
GREEN
1 Byte
7 01
2
7
B 5 R0
6-bits
BLUE
First Pixel in Packet
1 Byte
0
5
R5 G0
6-bits
RED
1 Byte
6 7 0
G5 B 0
6-bits
GREEN
Second Pixel in Packet
3
4
B 5 R0
6-bits
BLUE
Packet Footer
1 Byte
7 01
2
7
R5 G0
6-bits
RED
1 Byte
0
G5 B 0
6-bits
GREEN
5
1 Byte
6 7 0
B 5 R0
6-bits
BLUE
3
4
7 01
R5 G0
6-bits
RED
Third Pixel in Packet
1 Byte
2
G5 B 0
6-bits
GREEN
7
B5
6-bits
BLUE
Fourth Pixel in Packet
Variable Size Payload (Four Pixels Per Nine Bytes of Payload)
Figure 7-10. 18 bpp (Tightly Packed) DSI Packet Structure
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2 Bytes
DATA TYPE (0x3E)
VIRTUAL CHANNEL
1 Byte
1 Byte
WORD COUNT
WORD COUNT Bytes
24 bpp Packed Pixel Stream
ECC
CRC CHECKSUM
(Variable Size Payload)
Packet Payload
Packet Header
1 Byte
1 Byte
0
7
0
R0
R7
G0
8-bits
RED
2 Bytes
1 Byte
7
1 Byte
0
7
G 7 B0
8-bits
GREEN
B7
8-bits
BLUE
1 Byte
0
7
0
R0
R7
G0
8-bits
RED
First Pixel in Packet
Packet Footer
1 Byte
7
0
7
G 7 B0
8-bits
GREEN
1 Byte
B7
0
7
R0
8-bits
BLUE
Second Pixel in Packet
1 Byte
R7
8-bits
RED
1 Byte
0
7
G0
G7 B 0
0
8-bits
GREEN
7
B7
8-bits
BLUE
Third Pixel in Packet
Variable Size Payload (Three Pixels Per Nine Bytes of Payload)
Figure 7-11. 24 bpp DSI Packet Structure
7.4.6 DSI Video Transmission Specifications
The SN65DSI83 device supports burst video mode and non-burst video mode with sync events or with sync
pulses packet transmission as described in the DSI specification. The burst mode supports time-compressed
pixel stream packets that leave added time per scan line for power savings LP mode. The SN65DSI83 device
requires a transition to LP mode once per frame to enable PHY synchronization with the DSI host processor;
however, for a robust and low-power implementation, the transition to LP mode is recommended on every video
line.
Figure 7-12 shows the DSI video transmission applied to SN65DSI83 device applications. In all applications, the
LVDS output rate must be less than or equal to the DSI input rate. The first line of a video frame shall start with a
VSS packet, and all other lines start with VSE or HSS. The position of the synchronization packets in time is of
utmost importance since this has a direct impact on the visual performance of the display panel; that is, these
packets generate the HS and VS (horizontal and vertical sync) signals on the LVDS interface after the delay
programmed into CHA_SYNC_DELAY_LOW/HIGH (CSR 0x28.7:0 and 0x29.3:0).
As required in the DSI specification, the SN65DSI83 device requires that pixel stream packets contain an integer
number of pixels (that is, end on a pixel boundary); TI recommends to transmit an entire scan line on one pixel
stream packet. When a scan line is broken in to multiple packets, inter-packet latency shall be considered such
that the video pipeline (that is, pixel queue or partial line buffer) does not run empty (under-run); during scan line
processing, if the pixel queue runs empty, the SN65DSI83 device transmits zero data (18’b0 or 24’b0) on the
LVDS interface.
Note
When the HS clock is used as a source for the LVDS pixel clock, the LP mode transitions apply only to
the data lanes, and the DSI clock lane remains in the HS mode during the entire video transmission.
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Note
The SN65DSI83 device does not support the DSI virtual channel capability or reverse direction
(peripheral to processor) transmissions.
One Video Frame
Vertical sync / blanking
t W (HS )
HS
(1)
VS
(2)
HS
0x000
NOP/
LP
DSI
Channel
RGB
NOP/
LP
VS
(2)
t PD
VS
DATA
(2)
DE (3)
0x000
(2) VS is signaled for a programmable number of lines (tLINE ) and is asserted when HS is
asserted for the first line of the frame . VS is de -asserted when HS is asserted after the
number of lines programmed has been reached. The illustration shows VS active low
0x000
DATA
(1) The assertion of HS is delayed (t PD) by a programmable number of pixel clocks from the
last bit of VSS/HSS packet received on DSI. The HS pulse width (tW(HS) ) is also programmable.
The illustration shows HS active low.
PixelStream Data
0x000 (4)
LEGEND
VSS
DSI Sync Event Packet: V Sync Start
HSS
DSI Sync Event Packet: H Sync Start
RGB
A sequence of DSI Pixel Stream Packets
and Null Packets
NOP/LP
DSI Null Packet , Blanking Packet , or a
transition to LP Mode
(3) DE is asserted when active pixel data is transmitted on LVDS , and polarity is set
independent to HS/VS. The illustration shows DE active high
(4) After the last pixel in an active line is output to LVDS, the LVDS data is output zero
Figure 7-12. DSI Channel Transmission and Transfer Function
7.5 Programming
7.5.1 Local I2C Interface Overview
The SN65DSI83 device local I2C interface is enabled when EN is input high, access to the CSR registers is
supported during ULPS. The SCL and SDA pins are used for I2C clock and I2C data respectively. The
22
HSS
t LINE
HS (1)
DE (3)
DATA
NOP/
LP
t W(HS)
(1)
t PD
DE (3)
NOP/
LP
...
Active Video Line LVDS Transfer Function
HSS
DSI
Channel A
NOP/
LP
Vertical sync / blanking
t LINE
HSS
VSS
t LINE
NOP/
LP
NOP/
LP
Active Lines
Vertical Blanking Period LVDS Transfer Function
DSI
Channel A
RGB
t LINE
HSS
NOP/ ...
LP
RGB
t LINE
HSS
NOP/
LP
t LINE
HSS
NOP/
LP
...
HSS
NOP/
LP
t LINE
NOP/
LP
NOP/
LP
t LINE
HSS
DSI
Channel A
t LINE
HSS
VSS
t LINE
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SN65DSI83 device I2C interface conforms to the 2-wire serial interface defined by the I2C Bus Specification,
Version 2.1 (January 2000) and supports fast mode transfers up to 400 kbps.
The device address byte is the first byte received following the start condition from the master device. The 7-bit
device address for SN65DSI83 device is factory preset to 010110X with the least significant bit being determined
by the ADDR control input. Table 7-3 clarifies the SN65DSI83 device target address.
Table 7-3. SN65DSI83 I2C Target Address Description (1) (2)
BIT 7 (MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0 (W/R)
0
1
0
1
1
0
ADDR
0/1
(1)
(2)
When ADDR = 1, Address cycle is 0x5A (write) and 0x5B (read)
When ADDR = 0, Address cycle is 0x58 (write) and 0x59 (read)
The following procedure is followed to write to the SN65DSI83 device I2C registers:
1. The master initiates a write operation by generating a start condition (S), followed by the SN65DSI83 device
7-bit address and a zero-value W/R bit to indicate a write cycle.
2. The SN65DSI83 device acknowledges the address cycle.
3. The master presents the subaddress (I2C register within SN65DSI83 device) to be written, consisting of one
byte of data, MSB-first.
4. The SN65DSI83 device acknowledges the subaddress cycle.
5. The master presents the first byte of data to be written to the I2C register.
6. The SN65DSI83 device acknowledges the byte transfer.
7. The master may continue presenting additional bytes of data to be written, with each byte transfer completing
with an acknowledge from the SN65DSI83 device.
8. The master terminates the write operation by generating a stop condition (P).
The following procedure is followed to read the SN65DSI83 I2C registers:
1. The master initiates a read operation by generating a start condition (S), followed by the SN65DSI83 device
7-bit address and a one-value W/R bit to indicate a read cycle.
2. The SN65DSI83 device acknowledges the address cycle.
3. The SN65DSI83 device transmits the contents of the memory registers MSB-first starting at register 00h. If a
write to the SN65DSI83 I2C register occurred prior to the read, then the SN65DSI83 device starts at the
subaddress specified in the write.
4. The SN65DSI83 device waits for either an acknowledge (ACK) or a not-acknowledge (NACK) from the
master after each byte transfer; the I2C master acknowledges reception of each data byte transfer.
5. If an ACK is received, the SN65DSI83 device transmits the next byte of data.
6. The master terminates the read operation by generating a stop condition (P).
The following procedure is followed for setting a starting subaddress for I2C reads:
1. The master initiates a write operation by generating a start condition (S), followed by the SN65DSI83 device
7-bit address and a zero-value W/R bit to indicate a write cycle
2. The SN65DSI83 device acknowledges the address cycle.
3. The master presents the subaddress (I2C register within the SN65DSI83 device) to be written, consisting of
one byte of data, MSB first.
4. The SN65DSI83 device acknowledges the subaddress cycle.
5. The master terminates the write operation by generating a stop condition (P).
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7.6 Register Maps
7.6.1 Control and Status Registers Overview
Many of the SN65DSI83 device functions are controlled by the control and status registers (CSR). All CSR
registers are accessible through the local I2C interface.
See Table 7-4 through Table 7-9 for the SN65DSI83 CSR descriptions. Reserved or undefined bit fields must not
be modified. Otherwise, the device may operate incorrectly.
Table 7-4. CSR Bit Field Definitions – ID Registers
ADDRESS
BIT
0x00 – 0x08
7:0
(1)
DESCRIPTION
Reserved
Addresses 0x08 – 0x00 = {0x01, 0x20, 0x20, 0x20, 0x44, 0x53, 0x49, 0x38,
0x35}
DEFAULT
ACCESS(1)
Reserved
R/O
R/O = Read only; R/W = Read/write; R/W1C = Read/write 1 to clear; W/O = Write only (reads return undetermined values)
Table 7-5. CSR Bit Field Definitions – Reset and Clock Registers
ADDRESS
0x09
0x0A
BIT
DESCRIPTION
DEFAULT
ACCESS (1)
0
SOFT_RESET
This bit automatically clears when set to 1 and returns 0s when read. This bit
must be set after the CSR’s are updated. This bit must also be set after
making any changes to the DIS clock rate or after changing between DSI
burst and nonburst modes.
0 – No action (default)
1 – Reset device to default condition excluding the CSR bits
0
W/O
7
PLL_EN_STAT
After PLL_EN_STAT = 1, wait at least 3 ms for PLL to lock
0 – PLL not enabled (default)
1 – PLL enabled
0
R/O
101
R/W
0
HS_CLK_SRC
0 – LVDS pixel clock derived from input REFCLK (default)
1 – LVDS pixel clock derived from MIPI D-PHY channel A HS continuous
clock
0
R/W
7:3
DSI_CLK_DIVIDER
When CSR 0x0A.0 = 1, this field controls the divider used to generate the
LVDS output clock from the MIPI D-PHY Channel A HS continuous clock.
When CSR 0x0A.0 = 0, this field must be programmed to 00000.
00000 – LVDS clock = source clock (default)
00001 – Divide by 2
00010 – Divide by 3
00011 – Divide by 4
…
10111 – Divide by 24
11000 – Divide by 25
11001 through 11111 – Reserved
00000
R/W
1:0
REFCLK_MULTIPLIER
When CSR 0x0A.0 = 0, this field controls the multiplier used to generate the
LVDS output clock from the input REFCLK. When CSR 0x0A.0 = 1, this field
must be programmed to 00.
00 – LVDS clock = source clock (default)
01 – Multiply by 2
10 – Multiply by 3
11 – Multiply by 4
00
R/W
3:1
0x0B
24
LVDS_CLK_RANGE
This field selects the frequency range of the LVDS output clock.
000 – 25 MHz ≤ LVDS_CLK < 37.5 MHz
001 – 37.5 MHz ≤ LVDS_CLK < 62.5 MHz
010 – 62.5 MHz ≤ LVDS_CLK < 87.5 MHz
011 – 87.5 MHz ≤ LVDS_CLK < 112.5 MHz
100 – 112.5 MHz ≤ LVDS_CLK < 137.5 MHz
101 – 137.5 MHz ≤ LVDS_CLK ≤ 154 MHz (default)
110 – Reserved
111 – Reserved
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Table 7-5. CSR Bit Field Definitions – Reset and Clock Registers (continued)
ADDRESS
0x0D
(1)
BIT
DESCRIPTION
DEFAULT
ACCESS (1)
0
PLL_EN
When this bit is set, the PLL is enabled with the settings programmed into
CSR 0x0A and CSR 0x0B. The PLL must be disabled before changing any
of the settings in CSR 0x0A and CSR 0x0B. The input clock source must be
active and stable before the PLL is enabled.
0 – PLL disabled (default)
1 – PLL enabled
0
R/W
R/O = Read Only; R/W = Read/write; R/W1C = Read/write 1 to Clear; W/O = Write only (reads return undetermined values)
Table 7-6. CSR Bit Field Definitions – DSI Registers
ADDRESS
0x10
BIT
ACCESS (1)
7
Reserved. Do not write to this field. Must remain at default.
0
R/W
Reserved. Do not write to this field. Must remain at default.
01
R/W
4:3
CHA_DSI_LANES
This field controls the number of lanes that are enabled for DSI channel A.
00 – Four lanes are enabled
01 – Three lanes are enabled
10 – Two lanes are enabled
11 – One lane is enabled (default)
Note: Unused DSI input pins on the SN65DSI83 must be left unconnected.
11
R/W
SOT_ERR_TOL_DIS
0 – Single bit errors are tolerated for the start of transaction SoT leader
sequence (default)
1 – No SoT bit errors are tolerated
0
R/W
7:6
CHA_DSI_DATA_EQ
This field controls the equalization for the DSI channel A data lanes
00 – No equalization (default)
01 – 1 dB equalization
10 – Reserved
11 – 2 dB equalization
00
R/W
3:2
CHA_DSI_CLK_EQ
This field controls the equalization for the DSI channel A clock
00 – No equalization (default)
01 – 1-dB equalization
10 – Reserved
11 – 2-dB equalization
00
R/W
7:0
CHA_DSI_CLK_RANGE
This field specifies the DSI clock frequency range in 5-MHz increments for
the DSI channel A clock
0x00 through 0x07 – Reserved
0x08 – 40 ≤ frequency < 45 MHz
0x09 – 45 ≤ frequency < 50 MHz
…
0x63 – 495 ≤ frequency < 500 MHz
0x64 – 500 MHz
0x65 through 0xFF – Reserved
0
R/W
0x11
(1)
DEFAULT
6:5
0
0x12
DESCRIPTION
R/O = Read only; R/W = Read/write; R/W1C = Read/write 1 to clear; W/O = Write only (reads return undetermined values)
Table 7-7. CSR Bit Field Definitions – LVDS Registers
ADDRESS
BIT
DESCRIPTION
DEFAULT
ACCESS (1)
7
DE_NEG_POLARITY
0 – DE is positive polarity driven 1 during active pixel transmission on LVDS
(default)
1 – DE is negative polarity driven 0 during active pixel transmission on LVDS
0
R/W
6
HS_NEG_POLARITY
0 – HS is positive polarity driven 1 during corresponding sync conditions
1 – HS is negative polarity driven 0 during corresponding sync (default)
1
R/W
0x18
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Table 7-7. CSR Bit Field Definitions – LVDS Registers (continued)
ADDRESS
BIT
DESCRIPTION
DEFAULT
ACCESS (1)
5
VS_NEG_POLARITY
0 – VS is positive polarity driven 1 during corresponding sync conditions
1 – VS is negative polarity driven 0 during corresponding sync (default)
1
R/W
4
Reserved. Do not write to this field. Must remain at default.
1
R/W
3
CHA_24BPP_MODE
0 – Force 18 bpp; LVDS channel A lane 4 (A_Y3P or A_Y3N) is disabled
(default)
1 – Force 24 bpp; LVDS channel A lane 4 (A_Y3P or A_Y3N) is enabled
0
R/W
1
CHA_24BPP_FORMAT1
This field selects the 24 bpp data format
0 – LVDS channel A lane A_Y3P or A_Y3N transmits the 2 MSB per color;
format 2 (default)
1 – LVDS channel A lane A_Y3P or A_Y3N transmits the 2 LSB per color;
format 1
Note1: This field must be 0 when 18bpp data is received from DSI.
Note2: If this field is set to 1 and CHA_24BPP_MODE is 0, the SN65DSI83
device will convert 24-bpp data to 18-bpp data for transmission to an 18-bpp
panel. In this configuration, the SN65DSI83 device will not transmit the 2
LSB per color on LVDS channel A, since LVDS channel A lane 4 is disabled.
0
R/W
6
CHA_LVDS_VOCM
This field controls the common mode output voltage for LVDS channel A
0 – 1.2 V (default)
1 – 0.9 V (CSR 0x1B.5:4 CHA_LVDS_CM_ADJUST must be set to 01b)
0
R/W
CHA_LVDS_VOD_SWING
This field controls the differential output voltage for LVDS channel A. See the
Electrical Characteristics table for |VOD| for each setting:
00, 01 (default), 10, 11
01
R/W
0
R/W
CHA_LVDS_TERM
This bit controls the near end differential termination for LVDS channel A.
This bit also affects the output voltage for LVDS Channel A.
0 – 100-Ω differential termination
1 – 200-Ω differential termination (default)
1
R/W
CHA_LVDS_CM_ADJUST
This field can be used to adjust the common mode output voltage for LVDS
channel A.
00 – No change to common mode voltage (default)
01 – Adjust common mode voltage down 3%
10 – Adjust common mode voltage up 3%
11 – Adjust common mode voltage up 6%
00
R/W
0x19
3:2
CHA_REVERSE_LVDS
This bit controls the order of the LVDS pins for channel A.
0 – Normal LVDS channel A pin order. LVDS channel A pin order is the same
as listed in the Pin Assignments Section. (default)
5
0x1A
1
0x1B
(1)
26
5:4
1 – Reversed LVDS channel A pin order. LVDS channel A pin order is
remapped as follows:
• A_Y0P → A_Y3P
• A_Y0N → A_Y3N
• A_Y1P → A_CLKP
• A_Y1N → A_CLKN
• A_Y2P → A_Y2P
• A_Y2N → A_Y2N
• A_CLKP → A_Y1P
• A_CLKN → A_Y1N
• A_Y3P → A_Y0P
• A_Y3N → A_Y0N
R/O = Read only; R/W = Read/write; R/W1C = Read/write 1 to clear; W/O = Write only (reads return undetermined values)
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Note
For all video registers:
TEST PATTERN GENERATION PURPOSE ONLY registers are for test pattern generation use only.
Others are for normal operation unless the test pattern generation feature is enabled.
Table 7-8. CSR Bit Field Definitions – Video Registers
BIT
DESCRIPTION
DEFAULT
ACCESS (1)
0x20
7:0
CHA_ACTIVE_LINE_LENGTH_LOW
This field controls the length in pixels of the active horizontal line that are
received on DSI channel A and output to LVDS channel A.. The value in this
field is the lower 8 bits of the 12-bit value for the horizontal line length.
0
R/W
0x21
3:0
CHA_ACTIVE_LINE_LENGTH_HIGH
This field controls the length in pixels of the active horizontal line that are
received on DSI channel A and output to LVDS channel A.. The value in this
field is the upper 4 bits of the 12-bit value for the horizontal line length.
0
R/W
7:0
CHA_VERTICAL_DISPLAY_SIZE_LOW
TEST PATTERN GENERATION PURPOSE ONLY.
This field controls the vertical display size in lines for LVDS channel A. The
value in this field is the lower 8 bits of the 12-bit value for the vertical display
size. The value in this field is only used for channel A test pattern generation.
0
R/W
3:0
CHA_VERTICAL_DISPLAY_SIZE_HIGH
TEST PATTERN GENERATION PURPOSE ONLY.
This field controls the vertical display size in lines for LVDS channel A. The
value in this field is the upper 4 bits of the 12-bit value for the vertical display
size. The value in this field is only used for channel A test pattern generation.
0
R/W
7:0
CHA_SYNC_DELAY_LOW
This field controls the delay in pixel clocks from when an HSync or VSync is
received on the DSI to when it is transmitted on the LVDS interface for
channel A. The delay specified by this field is in addition to the pipeline and
synchronization delays in the SN65DSI83 device. The additional delay is
approximately 10 pixel clocks. The sync delay must be programmed to at
least 32 pixel clocks to ensure proper operation. The value in this field is the
lower 8 bits of the 12-bit value for the sync delay.
0
R/W
3:0
CHA_SYNC_DELAY_HIGH
This field controls the delay in pixel clocks from when an HSync or VSync is
received on the DSI to when it is transmitted on the LVDS interface for
channel A. The delay specified by this field is in addition to the pipeline and
synchronization delays in the SN65DSI83 device. The additional delay is
approximately 10 pixel clocks. The sync delay must be programmed to at
least 32 pixel clocks to ensure proper operation. The value in this field is the
lower 4 bits of the 12-bit value for the sync delay.
0
R/W
7:0
CHA_HSYNC_PULSE_WIDTH_LOW
This field controls the width in pixel clocks of the HSync pulse duration for
LVDS channel A. The value in this field is the lower 8 bits of the 10-bit value
for the HSync pulse duration.
The value in this field is used for channel A test pattern generation when test
pattern generation feature is enabled by programming bit 4 at 0x3C.
0
R/W
1:0
CHA_HSYNC_PULSE_WIDTH_HIGH
This field controls the width in pixel clocks of the HSync pulse duration for
LVDS channel A. The value in this field is the upper 2 bits of the 10-bit value
for the HSync pulse duration.
The value in this field is used for channel A test pattern generation when test
pattern generation feature is enabled by programming bit 4 at 0x3C.
0
R/W
7:0
CHA_VSYNC_PULSE_WIDTH_LOW
This field controls the length in lines of the VSync pulse duration for LVDS
channel A. The value in this field is the lower 8 bits of the 10-bit value for the
VSync pulse duration.
The value in this field is used for channel A test pattern generation when test
pattern generation feature is enabled by programming bit 4 at 0x3C.
0
R/W
ADDRESS
0x24
0x25
0x28
0x29
0x2C
0x2D
0x30
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Table 7-8. CSR Bit Field Definitions – Video Registers (continued)
ADDRESS
0x31
0x34
0x36
0x38
0x3A
0x3C
(1)
28
BIT
DESCRIPTION
DEFAULT
ACCESS (1)
1:0
CHA_VSYNC_PULSE_WIDTH_HIGH
This field controls the length in lines of the VSync pulse duration for LVDS
channel A. The value in this field is the upper 2 bits of the 10-bit value for the
VSync pulse duration.
The value in this field is used for channel A test pattern generation when test
pattern generation feature is enabled by programming bit 4 at 0x3C.
0
R/W
7:0
CHA_HORIZONTAL_BACK_PORCH
This field controls the time in pixel clocks between the end of the HSync
pulse and the start of the active video data for LVDS channel A.
The value in this field is used for channel A test pattern generation when test
pattern generation feature is enabled by programming bit 4 at 0x3C.
0
R/W
7:0
CHA_VERTICAL_BACK_PORCH
TEST PATTERN GENERATION PURPOSE ONLY.
This field controls the number of lines between the end of the VSync pulse
and the start of the active video data for LVDS channel A. The value in this
field is only used for channel A test pattern generation.
0
R/W
7:0
CHA_HORIZONTAL_FRONT_PORCH
TEST PATTERN GENERATION PURPOSE ONLY.
This field controls the time in pixel clocks between the end of the active video
data and the start of the HSync pulse for LVDS channel A. The value in this
field is only used for channel A test pattern generation.
0
R/W
7:0
CHA_VERTICAL_FRONT_PORCH
TEST PATTERN GENERATION PURPOSE ONLY.
This field controls the number of lines between the end of the active video
data and the start of the VSync pulse for LVDS channel A. The value in this
field is only used for channel A test pattern generation.
0
R/W
4
CHA_TEST_PATTERN
TEST PATTERN GENERATION PURPOSE ONLY.
When this bit is set, the SN65DSI83 device will generate a video test pattern
for LVDS channel A based on the values programmed into the video
registers for channel A.
0
R/W
R/O = Read only; R/W = Read/write; R/W1C = Read/write 1 to clear; W/O = Write only (reads return undetermined values)
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Table 7-9. CSR Bit Field Definitions – IRQ Registers
ADDRESS
0xE0
0xE1
BIT
DESCRIPTION
DEFAULT
ACCESS (1)
0
IRQ_EN
When enabled by this field, the IRQ output is driven high to communicate
IRQ events.
0 – IRQ output is high-impedance (default)
1 – IRQ output is driven high when a bit is set in registers 0xE5 that also has
the corresponding IRQ_EN bit set to enable the interrupt condition
0
R/W
7
CHA_SYNCH_ERR_EN
0 – CHA_SYNCH_ERR is masked
1 – CHA_SYNCH_ERR is enabled to generate IRQ events
0
R/W
6
CHA_CRC_ERR_EN
0 – CHA_CRC_ERR is masked
1 – CHA_CRC_ERR is enabled to generate IRQ events
0
R/W
5
CHA_UNC_ECC_ERR_EN
0 – CHA_UNC_ECC_ERR is masked
1 – CHA_UNC_ECC_ERR is enabled to generate IRQ events
0
R/W
4
CHA_COR_ECC_ERR_EN
0 – CHA_COR_ECC_ERR is masked
1 – CHA_COR_ECC_ERR is enabled to generate IRQ events
0
R/W
3
CHA_LLP_ERR_EN
0 – CHA_LLP_ERR is masked
1 – CHA_ LLP_ERR is enabled to generate IRQ events
0
R/W
2
CHA_SOT_BIT_ERR_EN
0 – CHA_SOT_BIT_ERR is masked
1 – CHA_SOT_BIT_ERR is enabled to generate IRQ events
0
R/W
0
PLL_UNLOCK_EN
0 – PLL_UNLOCK is masked
1 – PLL_UNLOCK is enabled to generate IRQ events
0
R/W
7
CHA_SYNCH_ERR
When the DSI channel A packet processor detects an HS or VS
synchronization error, that is, an unexpected sync packet; this bit is set; this
bit is cleared by writing a 1 value.
0
R/W1C
6
CHA_CRC_ERR
When the DSI channel A packet processor detects a data stream CRC error,
this bit is set; this bit is cleared by writing a 1 value.
0
R/W1C
5
CHA_UNC_ECC_ERR
When the DSI channel A packet processor detects an uncorrectable ECC
error, this bit is set; this bit is cleared by writing a 1 value.
0
R/W1C
4
CHA_COR_ECC_ERR
When the DSI channel A packet processor detects a correctable ECC error,
this bit is set; this bit is cleared by writing a 1 value.
0
R/W1C
3
CHA_LLP_ERR
When the DSI channel A packet processor detects a low level protocol error,
this bit is set; this bit is cleared by writing a 1 value.
Low-level protocol errors include SoT and EoT sync errors, Escape Mode
entry command errors, LP transmission sync errors, and false control errors.
Lane merge errors are reported by this status condition.
0
R/W1C
2
CHA_SOT_BIT_ERR
When the DSI channel A packet processor detects an SoT leader sequence
bit error, this bit is set; this bit is cleared by writing a 1 value.
0
R/W1C
0
PLL_UNLOCK
This bit is set whenever the PLL Lock status transitions from LOCK to
UNLOCK.
1
R/W1C
0xE5
(1)
R/O = Read only; R/W = Read/write; R/W1C = Read/write 1 to clear; W/O = Write only (reads return undetermined values)
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
The SN65DSI83 device is primarily targeted for portable applications such as tablets and smart phones that
utilize the MIPI DSI video format. The SN65DSI83 device can be used between a GPU with DSI output and a
video panel with LVDS inputs.
8.1.1 Video STOP and Restart Sequence
When the system requires to stop outputting video to the display, TI recommends to use the following sequence
for the SN65DSI83 device:
1. Clear the PLL_EN bit to 0 (CSR 0x0D.0).
2. Stop video streaming on DSI inputs.
3. Drive all DSI data lanes to LP11, but keep the DSI CLK lanes in HS.
When the system is ready to restart the video streaming.
1. Start video streaming on DSI inputs.
2. Set the PLL_EN bit to 1 (CSR 0x0D.0).
3. Wait for minimum of 3 ms.
4. Set the SOFT_RESET bit (0x09.0).
8.1.2 Reverse LVDS Pin Order Option
For ease of PCB routing, the SN65DSI83 device supports reversing the pin order via configuration register
programming. The order of the LVDS pin for LVDS channel A can be reversed by setting the address 0x1A bit 5
CHA_REVERSE_LVDS. See the corresponding register bit definition for details.
8.1.3 IRQ Usage
The SN65DSI83 device provides an IRQ pin that can be used to indicate when certain errors occur on DSI. The
IRQ output is enabled through the IRQ_EN bit (CSR 0xE0.0). The IRQ pin will be asserted when an error occurs
on DSI, the corresponding error enable bit is set, and the IRQ_EN bit is set. An error is cleared by writing a 1 to
the corresponding error status bit.
Note
If the SOFT_RESET bit is set while the DSI video stream is active, some of the error status bits may
be set.
Note
If the DSI video stream is stopped, some of the error status bits may be set. These error status bits
must be cleared before restarting the video stream.
Note
If the DSI video stream starts before the device is configured, some of the error status bits may be set.
TI recommends to start streaming after the device is correctly configured as recommended in the
initialization sequence in Section 7.4.2.
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8.2 Typical Application
Figure 8-1 shows a typical application using the SN65DSI83 device for a single channel DSI receiver to interface
a single-channel DSI application processor to an LVDS single-link 18 bit-per-pixel panel supporting 1280 × 800
WXGA resolutions at 60 frames per second.
A_Y0N
A_Y0P
100Ω
DA0P
DA0N
A_Y1N
A_Y1P
100Ω
A_Y2N
A_Y2P
100Ω
A_CLKN
A_CLKP
100Ω
DA1P
DA1N
DA2P
DA2N
DA3P
DA3N
To column driver
To row driver
18bpp TCON
Application
Processor
SN65DSI83
A_Y3N
A_Y3P
DACP
DACN
SCL
SDA
IRQ
EN
ADDR
REFCLK
GND
1.8V
VCC
C1
Figure 8-1. Typical WXGA 18-bpp Panel Application
8.2.1 Design Requirements
Table 8-1. Design Parameters
DESIGN PARAMETERS
EXAMPLE VALUE
VCC
1.8 V (±5%)
Clock Source (REFCLK or DSIA_CLK)
DSIA_CLK
REFCKL Frequency
N/A
DSIA Clock Frequency
500 MHz
PANEL INFORMATION
Pixel Clock (MHz)
83 MHz
Horizontal Active (pixels)
1280
Horizontal Blanking (pixels)
384
Vertical Active (lines)
800
Vertical Blanking (lines)
30
Horizontal Sync Offset (pixels)
64
Horizontal Sync Pulse Width (pixels)
128
Vertical Sync Offset (lines)
3
Vertical Sync Pulse Width (lines)
7
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Table 8-1. Design Parameters (continued)
DESIGN PARAMETERS
EXAMPLE VALUE
PANEL INFORMATION (continued)
Horizontal Sync Pulse Polarity
Negative
Vertical Sync Pulse Polarity
Negative
Color Bit Depth (6 bpc or 8 bpc)
6-bit
Number of LVDS Lanes
1 × [3 Data Lanes + 1 Clock Lane]
DSI INFORMATION
Number of DSI Lanes
1 × [4 Data Lanes + 1 Clock Lane]
DSI Clock Frequency(MHz)
500 MHz
Dual DSI Configuration(Odd/Even or Left/Right)
N/A
8.2.2 Detailed Design Procedure
The video resolution parameters required by the panel need to be programmed into the SN65DSI83 device. For
this example, the parameters programmed would be the following:
Horizontal Active = 1280 or 0x500
CHA_ACTIVE_LINE_LENGTH_LOW = 0x00
CHA_ACTIVE_LINE_LENGTH_HIGH = 0x05
Vertical Active = 800 or 0x320
CHA_VERTICAL_DISPLAY_SIZE_LOW = 0x20
CHA_VERTICAL_DISPLAY_SIZE_HIGH = 0x03
Horizontal Pulse Width = 128 or 0x80
CHA_HSYNC_PULSE_WIDTH_LOW = 0x80
CHA_HSYNC_PULSE_WIDTH_HIGH = 0x00
Vertical Pulse Width = 7
CHA_VSYNC_PULSE_WIDTH_LOW = 0x07
CHA_VSYNC_PULSE_WIDTH_HIGH = 0x00
Horizontal Backporch = HorizontalBlanking – (HorizontalSyncOffset + HorizontalSyncPulseWidth)
Horizontal Backporch = 384 – (64 + 128)
Horizontal Backporch = 192 or 0xC0
CHA_HORIZONTAL_BACK_PORCH = 0xC0
Vertical Backporch = VerticalBlanking – (VerticalSyncOffset +VerticalSyncPulseWidth)
Vertical Backporch = 30 – (3 + 7)
Vertical Backporch = 20 or 0x14
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CHA_VERTICAL_BACK_PORCH = 0x14
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Horizontal Frontporch = HorizontalSyncOffset
Horizontal Frontporch = 64 or 0x40
CHA_HORIZONTAL_FRONT_PORCH = 0x40
Vertical Frontporch = VerticalSyncOffset
Vertical Frontporch = 3
CHA_VERTICAL_FRONT_PORCH = 0x03
The pattern generation feature can be enabled by setting the CHA_TEST_PATTERN bit at address 0x3C and
configuring the TEST PATTERN GENERATION PURPOSE ONLY register as shown in Table 7-8.
LVDS clock is derived from the DSI channel A clock. When the MIPI D-PHY channel A HS clock is used as the
LVDS clock source, it is divided by the factor in DSI_CLK_DIVIDER (CSR 0x0B.7:3) to generate the FlatLink
LVDS output clock. Additionally, LVDS_CLK_RANGE (CSR 0x0A.3:1) and CH_DSI_CLK_RANGE(CSR 0x12)
must be set to the frequency range of the FlatLink LVDS output clock and DSI Channel A input clock respectively
for the internal PLL to operate correctly. After these settings are programmed, PLL_EN (CSR 0x0D.0) must be
set to enable the internal PLL.
LVDS_CLK_RANGE = 2 – 62.5 MHz ≤ LVDS_CLK < 87.5 MHz
HS_CLK_SRC = 1 – LVDS pixel clock derived from MIPI D-PHY channel A
DSI_CLK_DIVIDER = 00101 – Divide by 6
CHA_DSI_LANES = 00 – Four lanes are enabled
CHA_DSI_CLK_RANGE = 0x64 – 500 MHz
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8.2.2.1 Example Script
This example configures the SN65DSI83 device for the following configuration:
=====SOFTRESET=======
09 01
======PLL_EN(bit 0) - Enable LAST after addr 0A and 0B configured======
0D 00
======HS_CLK_SRC bit0===
======LVDS_CLK_Range bit 3:1======
0A 05
======DSI_CLK_DIVIDER bit7:3=====
======RefCLK multiplier(bit1:0)======
======00 - LVDSclk=source clk, 01 - x2, 10 -x3, 11 - x4======
0B 28
======DSI Ch Confg Left_Right Pixels(bit7 - 0 for A ODD, B EVEN, 1 for the other config)======
======DSI Ch Mode(bit6:5) 00 - Dual, 01 - single, 10 - two single =======
======SOT_ERR_TOL_DIS(bit0)=======
10 26
====500M====
12 64
======bit7: DE_Pol, bit6:HS_Pol, bit5:VS_Pol, bit4: LVDS Link Cfg, bit3:CHA 24bpp, bit2: CHB 24bpp,
bit1: CHA 24bpp fmt1, bit0: CHB 24bpp fmt1======
18 72
19 00
======CHA_LINE_LENGTH_LOW========
20 00
======CHA_LINE_LENGTH_HIGH========
21 05
======CHA_VERTICAL_DISPLAY_SIZE_LOW========
24 00
======CHA_VERTICAL_DISPLAY_SIZE_HIGH========
25 04
======CHA_SYNC_DELAY_LOW========
28 20
======CHA_SYNC_DELAY_HIGH========
29 01
======CHA_HSYNC_PULSE_WIDTH_LOW========
2C 80
======CHA_HSYNC_PULSE_WIDTH_HIGH========
2D 00
======CHA_VSYNC_PULSE_WIDTH_LOW========
30 07
======CHA_VSYNC_PULSE_WIDTH_HIGH========
31 00
======CHA_HOR_BACK_PORCH========
34 C0
======CHA_VER_BACK_PORCH========
36 00
======CHA_HOR_FRONT_PORCH========
38 00
======CHA_VER_FRONT_PORCH========
3A 00
======CHA/CHB TEST PATTERN(bit4 CHA, bit0 CHB)========
3C 00
======PLL_EN(bit 0) - Enable LAST after addr 0A and 0B configured======
0D 01
======Read======
00
======Read======
00
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8.2.3 Application Curve
120
ICC (mA)
115
110
105
100
95
1.6
1.65
1.7
1.75
1.8
1.85
VCC (V)
1.9
1.95
2
D001
A. All typical values are at TA = 25°C.
B. SN65DSI83: SINGLE Channel DSI to SINGLE Channel DSI, 1280 × 800
1. number of LVDS lanes = 3 data lanes + 1 CLK lane
2. number of DSI lanes = 4 data lanes + 1 CLK lane
3. LVDS CLK OUT = 83 M
4. DSI CLK = 500 M
5. RGB666, LVDS 18 bpp
Figure 8-2. Power Consumption
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9 Power Supply Recommendations
9.1 VCC Power Supply
Each VCC power supply pin must have a 100-nF capacitor to ground connected as close as possible to the
SN65DSI83 device. It is recommended to have one bulk capacitor (1 µF to 10 µF) on it. It is also recommended
to have the pins connected to a solid power plane.
9.2 VCORE Power Supply
This pin must have a 100-nF capacitor to ground connected as close as possible to the SN65DSI83 device. It is
recommended to have one bulk capacitor (1 µF to 10 µF) on it. It is also recommended to have the pins
connected to a solid power plane.
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10 Layout
10.1 Layout Guidelines
10.1.1 Package Specific
For the ZXH package, to minimize the power supply noise floor, provide good decoupling near the SN65DSI83
device power pins. The use of four ceramic capacitors (2 × 0.1 μF and 2 × 0.01 μF) provides good performance.
At the least, TI recommends to install one 0.1-μF and one 0.01-μF capacitor near the SN65DSI83 device. To
avoid large current loops and trace inductance, the trace length between decoupling capacitor and device power
inputs pins must be minimized. Placing the capacitor underneath the SN65DSI83 device on the bottom of the
PCB is often a good choice.
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10.1.2 Differential Pairs
•
•
•
•
•
•
•
•
•
•
•
Differential pairs must be routed with controlled 100-Ω differential impedance (± 20%) or 50-Ω single-ended
impedance (±15%).
Keep away from other high speed signals
Keep lengths to within 5 mils of each other.
Length matching must be near the location of mismatch.
Each pair must be separated at least by 3 times the signal trace width.
The use of bends in differential traces must be kept to a minimum. When bends are used, the number of left
and right bends must be as equal as possible and the angle of the bend must be ≥ 135 degrees. This
arrangement minimizes any length mismatch caused by the bends and therefore minimizes the impact that
bends have on EMI.
Route all differential pairs on the same of layer.
The number of vias must be kept to a minimum. It is recommended to keep the via count to 2 or less.
Keep traces on layers adjacent to ground plane.
Do NOT route differential pairs over any plane split.
Adding Test points will cause impedance discontinuity and will therefore negatively impact signal
performance. If test points are used, they must be placed in series and symmetrically. They must not be
placed in a manner that causes a stub on the differential pair.
10.1.3 Ground
TI recommends that only one board ground plane be used in the design. This provides the best image plane for
signal traces running above the plane. The thermal pad of the SN65DSI83 must be connected to this plane with
vias.
10.2 Layout Example
Purple traces on
this side are LVDS
ChB signals.
Purple traces on
this side are DSI
ChA signals.
Green traces on
this side are LVDS
ChA signals.
Green traces on
this side are LVDS
ChB signals.
Green - Top Layer, Purple - Layer 3, Blue - Bottom Layer
Figure 10-1. SN65DSI8x Layout Example
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.2 Community Resources
11.3 Trademarks
FlatLink™ is a trademark of TI.
MIPI® is a registered trademark of Arasan Chip Systems, Inc.
All other trademarks are the property of their respective owners.
Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN65DSI83ZXHR
ACTIVE
NFBGA
ZXH
64
2500
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 85
DSI83
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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