SN65HVD05, SN65HVD06
SN75HVD05, SN65HVD07
SN75HVD06, SN75HVD07
SLLS533E – MAY 2002 – REVISED AUGUST 2009
www.ti.com
HIGH OUTPUT RS-485 TRANSCEIVERS
Check for Samples: SN65HVD05, SN65HVD06, SN75HVD05, SN65HVD07, SN75HVD06, SN75HVD07
FEATURES
1
•
•
•
•
•
•
•
•
•
Minimum Differential Output Voltage of 2.5 V
Into a 54-Ω Load
Open-Circuit, Short-Circuit, and Idle-Bus
Failsafe Receiver
1/8th Unit-Load Option Available (Up to 256
Nodes on the Bus)
Bus-Pin ESD Protection Exceeds 16 kV HBM
Driver Output Slew Rate Control Options
Electrically Compatible With ANSI
TIA/EIA-485-A Standard
Low-Current Standby Mode: 1 µA Typical
Glitch-Free Power-Up and Power-Down
Protection for Hot-Plugging Applications
Pin Compatible With Industry Standard
SN75176
APPLICATIONS
•
•
•
•
•
•
•
Data Transmission Over Long or Lossy Lines
or Electrically Noisy Environments
Profibus Line Interface
Industrial Process Control Networks
Point-of-Sale (POS) Networks
Electric Utility Metering
Building Automation
Digital Motor Control
DESCRIPTION
The SN65HVD05, SN75HVD05, SN65HVD06,
SN75HVD06,
SN65HVD07,
and
SN75HVD07
combine a 3-state differential line driver and
differential line receiver. They are designed for
balanced data transmission and interoperate with
ANSI
TIA/EIA-485-A
and
ISO
8482E
standard-compliant devices. The driver is designed to
provide a differential output voltage greater than that
required by these standards for increased noise
margin. The drivers and receivers have active-high
and active-low enables respectively, which can be
externally connected together to function as direction
control.
The driver differential outputs and receiver differential
inputs connect internally to form a differential input/
output (I/O) bus port that is designed to offer
minimum loading to the bus whenever the driver is
disabled or not powered. These devices feature wide
positive and negative common-mode voltage ranges,
making them suitable for party-line applications.
D OR P PACKAGE
(TOP VIEW)
R
RE
DE
D
V O - Differential Output Voltage - V
5
4
60 Ω Load
Line
3.5
TA = 25°C
DE at VCC
D at VCC
VCC = 5 V
R
RE
30 Ω Load
Line
3
DE
2.5
8
2
7
3
6
4
5
VCC
B
A
GND
LOGIC DIAGRAM
(POSITIVE LOGIC)
DIFFERENTIAL OUTPUT VOLTAGE
vs
DIFFERENTIAL OUTPUT CURRENT
4.5
1
1
2
3
6
2
D
1.5
1
4
7
A
B
0.5
0
0
20
40
60
80
100
120
IOD - Differential Output Current - mA
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2009, Texas Instruments Incorporated
SN65HVD05, SN65HVD06
SN75HVD05, SN65HVD07
SN75HVD06, SN75HVD07
SLLS533E – MAY 2002 – REVISED AUGUST 2009
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION (1)
MARKED AS
DRIVER
OUTPUT SLOPE
CONTROL
SIGNALING
RATE
UNIT
LOAD
40 Mbps
1/2
No
10 Mbps
1/8
Yes
(1)
(2)
PART NUMBER (2)
TA
–40°C to 85°C
PLASTIC
DUAL-IN-LINE
PACKAGE
(PDIP)
SMALL
OUTLINE
IC (SOIC)
PACKAGE
SN65HVD05D
SN65HVD05P
65HVD05
VP05
SN65HVD06D
SN65HVD06P
65HVD06
VP06
1 Mbps
1/8
Yes
SN65HVD07D
SN65HVD07P
65HVD07
VP07
40 Mbps
1/2
No
SN75HVD05D
SN75HVD05P
75HVD05
VN05
10 Mbps
1/8
Yes
SN75HVD06D
SN75HVD06P
75HVD06
VN06
1 Mbps
1/8
Yes
SN75HVD07D
SN75HVD07P
75HVD07
VN07
0°C to 70°C
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
The D package is available taped and reeled. Add an R suffix to the device type (i.e., SN65HVD05DR).
PACKAGE DISSIPATION RATINGS
(See Figure 12 and Figure 13)
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR (1)
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
D (2)
710 mW
5.7 mW/°C
455 mW
369 mW
1282 mW
10.3 mW/°C
821 mW
667 mW
1000 mW
8.0 m W/°C
640 mW
520 mW
D
(3)
P
(1)
(2)
(3)
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
Tested in accordance with the Low-K thermal metric definitions of EIA/JESD51-3
Tested in accordance with the High-K thermal metric definitions of EIA/JESD51-7
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted (1)
(2)
SN65HVD05, SN65HVD06, SN65HVD07
SN75HVD05, SN75HVD06, SN75HVD07
–0.3 V to 6 V
Supply voltage range, VCC
–9 V to 14 V
Voltage range at A or B
–0.5 V to VCC + 0.5 V
Input voltage range at D, DE, R or RE
Voltage input range, transient pulse, A and B, through 100 Ω (see Figure 11)
Electrostatic discharge
Human body model (3)
Charged-device model (4)
Continuous total power dissipation
(1)
(2)
(3)
(4)
2
–50 V to 50 V
–11 mA to 11mA
Receiver output current, IO
A, B, and GND
16 kV
All pins
4 kV
All pins
1 kV
See Dissipation Rating Table
Stresses beyond those listed under "absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under" recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
Tested in accordance with JEDEC Standard 22, Test Method A114-A.
Tested in accordance with JEDEC Standard 22, Test Method C101.
Submit Documentation Feedback
Copyright © 2002–2009, Texas Instruments Incorporated
Product Folder Link(s): SN65HVD05 SN65HVD06 SN75HVD05 SN65HVD07 SN75HVD06 SN75HVD07
SN65HVD05, SN65HVD06
SN75HVD05, SN65HVD07
SN75HVD06, SN75HVD07
SLLS533E – MAY 2002 – REVISED AUGUST 2009
www.ti.com
RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX
Supply voltage, VCC
Voltage at any bus terminal (separately or common mode) VI or VIC
High-level input voltage, VIH
D, DE, RE
Low-level input voltage, VIL
D, DE, RE
5.5
V
–7 (1)
12
V
2
High-level output current, IOH
Low-level output current, IOL
V
–12
Differential input voltage, VID (see Figure 7)
0.8
V
12
V
–100
Driver
UNIT
4.5
mA
–8
Receiver
Driver
100
Receiver
8
mA
SN65HVD05
SN65HVD06
Operating free-air temperature, TA
–40
85
°C
0
70
°C
SN65HVD07
SN75HVD05
SN75HVD06
SN75HVD07
(1)
The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
DRIVER ELECTRICAL CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER
VIK
Input clamp voltage
|VOD|
Differential output voltage
MIN TYP (1)
TEST CONDITIONS
II = –18 mA
Change in magnitude of differential output
voltage
VOC(SS)
Steady-state common-mode output voltage
ΔVOC(SS)
Change in steady-state common-mode
output voltage
VOC(PP)
Peak-to-peak common-mode
output voltage
VCC
RL = 54 Ω, See Figure 4
2.5
Vtest = –7 V to 12 V, See Figure 2
2.2
See Figure 4 and Figure 2
See Figure 3
0.2
V
2.2
3.3
V
–0.1
0.1
V
600
See Figure 3
500
HVD07
IOZ
High-impedance output current
See receiver input currents
D
Input current
IOS
Short-circuit output current
–7 V ≤ VO ≤ 12 V
C(diff)
Differential output capacitance
VID = 0.4 sin (4E6πt) + 0.5 V, DE at 0 V
(1)
mV
900
II
ICC
V
–0.2
HVD05
HVD06
UNIT
V
No Load
Δ|VOD|
MAX
–1.5
DE
Supply current
–100
0
0
100
–250
250
16
μA
mA
pF
RE at VCC,
D and DE at VCC,
No load
Receiver disabled
and driver enabled
9
15
mA
RE at VCC,
D at VCC DE at 0 V,
No load
Receiver disabled
and driver disabled
(standby)
1
5
μA
RE at 0 V,
D and DE at VCC,
No load
Receiver enabled
and driver enabled
9
15
mA
All typical values are at 25°C and with a 5-V supply.
Copyright © 2002–2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SN65HVD05 SN65HVD06 SN75HVD05 SN65HVD07 SN75HVD06 SN75HVD07
3
SN65HVD05, SN65HVD06
SN75HVD05, SN65HVD07
SN75HVD06, SN75HVD07
SLLS533E – MAY 2002 – REVISED AUGUST 2009
www.ti.com
DRIVER SWITCHING CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
MIN TYP (1)
MAX
HVD05
6.5
11
HVD06
27
40
HVD07
250
400
HVD05
6.5
11
PARAMETER
tPLH
Propagation delay time, low-to-high-level output
tPHL
Propagation delay time, high-to-low-level output
TEST CONDITIONS
HVD06
27
40
HVD07
250
400
3.6
6
HVD05
tr
Differential output signal rise time
HVD06
HVD07
HVD05
tf
Differential output signal fall time
tsk(p)
tsk(pp)
tPZH1
Pulse skew (|tPHL - tPLH|)
(2)
Part-to-part skew
Propagation delay time,
high-impedance-to-high-level output
tPZL1
18
28
55
150
300
450
2.7
3.6
6
18
28
55
HVD07
150
300
450
HVD05
2
HVD06
2.5
HVD07
10
HVD05
3.5
HVD06
14
HVD07
100
HVD05
25
HVD06
45
HVD05
Propagation delay time,
high-level-to-high-impedance output
RL = 54 Ω, CL = 50 pF,
See Figure 4
HVD06
HVD07
tPHZ
2.7
RE at 0 V, RL = 110 Ω,
See Figure 5
60
250
HVD05
Propagation delay time, high-impedance-to-low-level
HVD06
output
HVD07
15
45
Propagation delay time, low-level-to-high-impedance
HVD06
output
HVD07
tPLZ
ns
ns
ns
ns
ns
ns
25
HVD07
RE at 0 V, RL = 110 Ω,
See Figure 6
ns
250
HVD06
HVD05
UNIT
ns
ns
200
14
90
ns
550
tPZH2
Propagation delay time, standby-to-high-level output
RL = 110Ω , RE at 3 V,
See Figure 5
6
μs
tPZL2
Propagation delay time, standby-to-low-level output
RL = 110 Ω, RE at 3 V,
See Figure 6
6
μs
(1)
(2)
4
All typical values are at 25°C and with a 5-V supply.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
Submit Documentation Feedback
Copyright © 2002–2009, Texas Instruments Incorporated
Product Folder Link(s): SN65HVD05 SN65HVD06 SN75HVD05 SN65HVD07 SN75HVD06 SN75HVD07
SN65HVD05, SN65HVD06
SN75HVD05, SN65HVD07
SN75HVD06, SN75HVD07
SLLS533E – MAY 2002 – REVISED AUGUST 2009
www.ti.com
RECEIVER ELECTRICAL CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
VIT+
Positive-going input
threshold voltage
IO = –8 mA
VIT-
Negative-going input
threshold voltage
IO = 8 mA
Vhys
Hysteresis voltage
(VIT+ - VIT-)
VIK
Enable-input clamp voltage II = –18 mA
VOH
High-level output voltage
VID = 200 mV,
IOH = –8 mA,
See Figure 7
VOL
Low-level output voltage
VID = -200 mV,
IOL = 8 mA,
See Figure 7
IOZ
High-impedance-state
output current
VO = 0 or VCC
RE at VCC
V
Other inputat 0 V
VA or VB = 12 V,
V
4
V
Other inputat 0 V
VA or VB = 12 V,
VA or VB = –7 V
VA or VB = –7 V,
IIH
IIL
Low-level input current, RE VIL = 0.8 V
C(diff)
Differential input
capacitance
(1)
VCC = 0 V
VIH = 2 V
VI = 0.4 sin (4E6πt) + 0.5 V, DE at 0 V
V
1
μA
0.5
0.3
0.5
0.13
–0.4
0.15
VCC = 0 V
0.4
0.23
–0.4
VA or VB = 12 V
High-level input current,
RE
Supply current
VCC = 0 V
VCC = 0 V
mV
–1.5
–1
VA or VB = –7 V
VA or VB = –7 V,
Bus input current
HVD06
HVD07
UNIT
–0.2
35
HVD05
ICC
MAX
–0.01
VA or VB = 12 V
II
TYP (1)
0.06
0.1
0.08
0.13
mA
mA
–0.1
0.05
–0.05
0.03
–60
26.4
μA
–60
27.4
μA
16
pF
RE at 0 V, D and DE at
Receiver enabled and driver disabled
0 V, No load
5
10
mA
RE at VCC, DE at 0 V,
D at VCC, No load
Receiver disabled and driver disabled
(standby)
1
5
μA
RE at 0 V,
D and DE at VCC,
No load
Receiver enabled and driver enabled
9
15
mA
All typical values are at 25°C and with a 5-V supply.
Copyright © 2002–2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SN65HVD05 SN65HVD06 SN75HVD05 SN65HVD07 SN75HVD06 SN75HVD07
5
SN65HVD05, SN65HVD06
SN75HVD05, SN65HVD07
SN75HVD06, SN75HVD07
SLLS533E – MAY 2002 – REVISED AUGUST 2009
www.ti.com
RECEIVER SWITCHING CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
tPLH
Propagation delay time, low-to-high-level output 1/2 UL
HVD05
14.6
25
ns
tPHL
Propagation delay time, high-to-low-level output 1/2 UL
HVD05
14.6
25
ns
HVD06
55
70
HVD07
55
70
55
70
55
70
tPLH
Propagation delay time, low-to-high-level output 1/8 UL
tPHL
Propagation delay time, high-to-low-level output 1/8 UL
HVD06
VID = –1.5 V to 1.5 V,
CL = 15 pF,
See Figure 8
HVD07
HVD05
Pulse skew (|tPHL – tPLH|)
tsk(p)
tsk(pp)
(2)
Part-to-part skew
tr
Output signal rise time
tf
Output signal fall time
tPZH1
Output enable time to high level
tPZL1
Output enable time to low level
tPHZ
Output disable time from high level
tPLZ
Output disable time from low level
tPZH2
Propagation delay time, standby-to-high-level output
tPZL2
Propagation delay time, standby-to-low-level output
(1)
(2)
ns
2
HVD06
4.5
HVD07
4.5
HVD05
6.5
HVD06
14
HVD07
14
CL = 15 pF,
See Figure 8
ns
2
3
2
3
ns
ns
ns
10
CL = 15 pF,
DE at 3 V,
See Figure 9
10
15
ns
15
CL = 15 pF, DE at 0,
See Figure 10
6
6
μs
All typical values are at 25°C and with a 5-V supply.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
PARAMETER MEASUREMENT INFORMATION
VCC
DE
II
A
IOA
VOD
0 or 3 V
B
54 Ω ±1%
IOB
VI
VOB
VOA
Figure 1. Driver VOD Test Circuit and Voltage and Current Definitions
375 Ω ±1%
VCC
DE
D
A
VOD
0 or 3 V
60 Ω ±1%
+ -7 V < V(test)
_ < 12 V
B
375 Ω ±1%
Figure 2. Driver VOD With Common-Mode Loading Test Circuit
6
Submit Documentation Feedback
Copyright © 2002–2009, Texas Instruments Incorporated
Product Folder Link(s): SN65HVD05 SN65HVD06 SN75HVD05 SN65HVD07 SN75HVD06 SN75HVD07
SN65HVD05, SN65HVD06
SN75HVD05, SN65HVD07
SN75HVD06, SN75HVD07
SLLS533E – MAY 2002 – REVISED AUGUST 2009
www.ti.com
VCC
DE
D
Input
27 Ω ± 1%
A
A
VA
B
VB
VOC(PP)
27 Ω ± 1%
B
CL = 50 pF ±20%
VOC
∆VOC(SS)
VOC
CL Includes Fixture and
Instrumentation Capacitance
Input: PRR = 500 kHz, 50% Duty Cycle,tr