SN65HVD09DGGR

SN65HVD09 www.ti.com............................................................................................................................................................................................ SLLS941 – DECEMBER 2008 9-CHANNEL RS-422 / RS-485 TRANSCEIVER FEATURES 1 • • • • • • • Designed to Operate at up to 20 Million Data Transfers per Second on Each RS-422/RS-485 Channel SN65HVD09 Packaged in Thin Shrink Small-Outline Package with 0.5-mm Pin Pitch ESD Protection on Bus Pins Exceeds 12kV Low Disabled Supply Current 8 mA Typ Thermal Shutdown Protection Positive- and Negative-Current Limiting Power-Up/Down Glitch Protection DESCRIPTION The SN65HVD09 is a 9-channel RS-422 / RS-485 transceiver suitable for industrial applications. It offers improved switching performance, a small package, and high ESD protection. The precise skew limits ensures that the propagation delay times, not only from channel-to-channel but from device-to-device, are closely matched for the tight skew budgets associated with high-speed parallel data buses. Patented thermal enhancements are used in the thin shrink, small-outline package (TSSOP), allowing operation over the industrial temperature range. The TSSOP package offers very small board area requirements while reducing the package height to 1 mm. This provides more board area and allows component mounting to both sides of the printed circuit boards for low-profile, space-restricted applications such as small form-factor hard disk drives. Each of the nine half-duplex channels of the HVD09 is designed to operate with either RS-422 or RS-485 communication networks. The SN65HVD09 is characterized for operation over an ambient air temperature range of –40°C to 85°C. SN65HVD09 DGG (TOP VIEW) GND 1 56 CDE2 BSR 2 55 CDE1 GRE 3 54 CDE0 1A 4 53 9B+ 1DE/RE 5 52 9B- 2A 6 51 8B+ 2DE/RE 7 50 8B- 3A 8 49 7B+ 3DE/RE 9 48 7B- 4A 10 47 6B+ 4DE/RE 11 46 6B- VCC 12 45 VCC GND 13 44 GND GND 14 43 GND GND 15 42 GND GND 16 41 GND GND 17 40 VCC 18 39 GND VCC 5A 19 38 5B+ 5DE/RE 20 37 5B- 6A 21 36 4B+ 6DE/RE 22 35 4B- 7A 23 34 3B+ 7DE/RE 24 33 3B- 8A 25 32 2B+ 8DE/RE 26 31 2B- 9A 27 30 1B+ 9DE/RE 28 29 1B- The HVD09 can withstand electrostatic discharges exceeding 12 kV using the human-body model, and 600 V using the machine model on the RS-485 I/O terminals. This provides protection from the noise that can be coupled into external cables. The other terminals of the device can withstand discharges exceeding 4 kV and 400 V respectively. Terminals 13 through 17, and 40 through 44 are connected together to the package lead frame and signal ground. 9 Differential RS-422/RS-485 I/O Channels Configuration and Control Logic HVD09 9 Single-ended TTL I/O Channels 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008, Texas Instruments Incorporated SN65HVD09 SLLS941 – DECEMBER 2008............................................................................................................................................................................................ www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. PIN FUNCTIONS PIN NAME NO. LOGIC LEVEL I/O TERMINATION DESCRIPTION 1A to 9A 4,6,8,10, 19,21,23, 25,27 TTL I/O Pullup 1B– to 9B– 29,31,33, 35,37,.46 , 48,50,52 RS-485 I/O Pulldown 1B+ to 9B+ 30,32,34, 36,38,47, 49,51,53 RS-485 I/O Pullup 1B+ to 9B+ are the noninverted data signals of the balanced pair to/from the bus. BSR 2 TTL Input Pullup BSR is the bit significant response. BSR disables receivers 1 through 8 and enables wired-OR drivers when BSR and DE/RE and CDE1 or CDE2 are high. Channel 9 is placed in a high-impedance state with BSR high. CDE0 54 TTL Input Pulldown CDE0 is the common driver enable 0. Its input signal enables all drivers when CDE0 and 1DE/RE – 9DE/RE are high. CDE1 55 TTL Input Pulldown CDE1 is the common driver enable 1. Its input signal enables drivers 1 to 4 when CDE1 is high and BSR is low. CDE2 56 TTL Input Pulldown CDE2 is the common driver enable 2. When CDE2 is high and BSR is low, drivers 5 to 8 are enabled. CRE 1A to 9A carry data to and from the communication controller. 1B– to 9B– are the inverted data signals of the balanced pair to/from the bus. 3 TTL Input Pullup CRE is the common receiver enable. When high, CRE disables receiver channels 5 to 9. 1DE/RE to 9DE/RE 5,7,9,11, 20,22,24, 26,28 TTL Input Pullup 1DE/RE–9DE/RE are direction controls that transmit data to the bus when it and CDE0 are high. Data is received from the bus when 1DE/RE–9DE/RE and CRE and BSR are low and CDE1 and CDE2 are low. GND 1,13,14, 15,16,17, 40,41,42, 43,44 NA Power NA GND is the circuit ground. All GND terminals except terminal 1 are physically tied to the die pad for improved thermal conductivity. (1) VCC 12,18,39, 45 NA Power NA Supply voltage (1) 2 Terminal 1 must be connected to signal ground for proper operation. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD09 SN65HVD09 www.ti.com............................................................................................................................................................................................ SLLS941 – DECEMBER 2008 LOGIC DIAGRAM (POSITIVE LOGIC) CDE0 CDE1 BSR 1A 1DE/RE 2A 2DE/RE 3A 3DE/RE 4A 4DE/RE CDE2 CRE 5A 5DE/RE 6A 6DE/RE 7A 7DE/RE 8A 8DE/RE 54 55 2 30 4 29 5 6 7 8 9 10 11 Channel 2 Channel 3 Channel 4 9DE/RE 32 31 34 33 36 35 2B+ 2B− 3B+ 3B− 4B+ 4B− 56 3 38 19 37 5B+ 5B− 20 21 22 23 24 25 26 Channel 6 Channel 7 Channel 8 2 9A 1B+ 1B− 27 BSR 3 BSR 47 46 49 48 51 50 6B+ 6B− 7B+ 7B− 8B+ 8B− 54 CRE CDE0 53 9B+ 52 9B− 28 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD09 3 SN65HVD09 SLLS941 – DECEMBER 2008............................................................................................................................................................................................ www.ti.com ABSOLUTE MAXIMUM RATINGS (1) VCC Supply voltage range (2) IO –0.3 to 6 V V –0.3 to VCC +0.5 V Receiver output current Electrostatic discharge ±40 mA B side and GND, Class 3, A (3) 12 kV B side and GND, Class 3, B (3) 400 V All terminals, Class 3, A 4 kV All terminals, Class 3, B 400 V Continuous total power dissipation (1) (2) (3) (4) UNIT –10 to 15 Bus voltage range Data I/O and control (A side) voltage range VALUE (4) Internally Limited Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.r All voltage values are with respect to the GND terminals. This absolute maximum rating is tested in accordance with MIL-PRF-38535, Method 3015.7. The maximum operating junction temperature is internally limited. Use the Dissipation Rating Table to operate below this temperature. DISSIPATION RATINGS (1) PACKAGE TA ≤ 25°C OPERATING FACTOR (1) ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING DGG 2500 mW 20 mW/°C 1600 mW 1300 mW This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. PACKAGE THERMAL CHARACTERISTICS MIN θJA Junction-to-ambient thermal resistance DGG, board-mounted, no air flow θJC Junction-to-case thermal resistance DGG TSD Thermal shutdown temperature NOM MAX 50 UNIT °C/W 27 °C/W 165 °C RECOMMENDED OPERATING CONDITIONS VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage VO, VI, or VIC Voltage at any bus terminal (separately or common-mode) IO Output current TA Ambient temperature (1) 4 Except nB+, nB– (1) nB+ or nB– Driver Receiver SN65HVD09 MIN NOM MAX UNIT 4.75 5 5.25 V 2 V 0.8 V –7 12 V –60 60 mA –8 8 mA –40 85 °C n=1-9 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD09 SN65HVD09 www.ti.com............................................................................................................................................................................................ SLLS941 – DECEMBER 2008 ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER |VOD| VOH SN65HVD09 TEST CONDITIONS Driver differential output voltage magnitude High-level output voltage RS-422 load, RL = 100 Ω RS-485 load, RL = 54 Ω See Figure 1 A side, IOH = –8 mA, VID = 200 mV, See Figure 4 4 4.5 B side, See Figure 2 3 A side, IOH = 8 mA, VID = –200 mV, See Figure 4 0.6 B side, See Figure 2 1 IOH = –8 mA, See Figure 4 VIT– Receiver negativegoing differential input threshold voltage IOL = 8 mA, SeeFigure 4 Vhys Receiver input hysteresis (VIT+ – VIT–) VCC = 5 V, TA = 25°C VIH = 12 V VCC = 5 V, VIH = 12 V VCC = 0, VIH = –7 V VCC = 5 V, VIH = –7 V VCC = 0, nA, BSR, DE/RE, and CRE, VIH = 2 V CDE0, CDE1, and CDE2, VIH = 2V nA, BSR, DE/RE, and CRE, VIL = 0.8 V CDE1, CDE1, and CDE2, VIL = 0.8 V IIL Low-level input current IOS Short circuit output current nB+ or nB– IOZ High-impedance-state output current nA ICC CO Cpd (1) (2) Output capacitance Power dissipation capacitance (2) V V 0.8 V V –0.2 V V 45 mV 1 mA 1 mA –0.8 –0.4 mA –0.8 –0.3 mA µA –100 100 µA µA –100 100 µA ±260 mA See IIH and IIL nB+ or nB– Supply current UNIT V 0.2 24 Other input at 0 V MAX 1.4 1.5 Receiver positive-going differential input threshold voltages High-level input current 1.6 1 VIT+ IIH 1 See Figure 2 Low-level output voltage Bus input current TYP (1) Pull-Up Pull-Down Load VOL II MIN See III Disabled 10 All drivers enabled, no load 60 All receivers enabled, no load 45 nB+ or nB– to GND 18 Receiver 40 Driver 25 100 mA pF pF All typical values are at VCC = 5 V, TA = 25°C. Cpd determines the no-load dynamic supply current consumption, IS = CPD × VCC × f + ICC Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD09 5 SN65HVD09 SLLS941 – DECEMBER 2008............................................................................................................................................................................................ www.ti.com DRIVER SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS SN65HVD09 UNIT MIN TYP (1) MAX 2.5 13.5 ns 4 ns tpd Propagation delay time, tPHL or tPLH (see Figure 2 and Figure 3) tsk(p) Pulse skew, |tPHL – tPLH| tf Fall time S1 to B, See Figure 3 4 ns tr Rise time See Figure 3 8 ns ten Enable time, control inputs to active output tdis Disable time, control inputs to high-impedance output tPHZ Propagation delay time, high-level to high-impedance output tPLZ Propagation delay time, low-level to high-impedance output tPZH Propagation delay time, high-impedance to high-level output tPZL Propagation delay time, high-impedance to low-level output (1) See Figure 6 and Figure 7 50 ns 100 ns 17 100 ns 25 100 ns 17 50 ns 17 50 ns All typical values are at VCC = 5 V, TA = 25°C. RECEIVER SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER tpd TEST CONDITIONS Propagation delay time, tPHL or tPLH (see Figure 2 and Figure 3) SN65HVD09 UNIT MIN TYP (1) MAX 8.5 14.5 ns 5 ns 4 ns (2) tsk(lim) Skew limit, maximum tpd – minimum tpd tsk(p) Pulse skew, |tPHL – tPLH| tt Transition time (tr or tf) ten Enable time, control inputs to active output 50 ns tdis Disable time, control inputs to high-impedance output 60 ns tPHZ Propagation delay time, high-level to high-impedance output 60 ns tPLZ Propagation delay time, low-level to high-impedance output 50 ns tPZH Propagation delay time, high-impedance to high-level output 50 ns tPZL Propagation delay time, high-impedance to low-level output 50 ns (1) (2) 6 0.6 See Figure 5 2 See Figure 8 and Figure 9 ns All typical values are at VCC = 5 V, TA = 25°C. This parameter is applicable at one VCC and operating temperature within the recommended operating conditions and to any two devices. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD09 SN65HVD09 www.ti.com............................................................................................................................................................................................ SLLS941 – DECEMBER 2008 PARAMETER MEASUREMENT INFORMATION RL/2 B+ A Input VOC B- CL = 50 pF ±20% RL/2 CL Includes Fixture and Instrumentation Capacitance Figure 1. Driver Test Circuit, RS-422 and RS-485 Loading 5V PU S1 B+ IO 15 pF II Input (see Note A) A 165 Ω PD VOD 165 Ω VO VI 375 Ω 75 Ω 375 Ω IO B− VO † † ‡ S2 15 pF CDEO and DE/RE are at 2 V, BSR is at 0.8V, and all others are open. All nine drivers are enabled, similarly loaded, and switching. Figure 2. Driver Test Circuit, Pull-Up and Pull-Down Loading‡ 3V Input 1.5 V 1.5 V 0V tPLH Output, VOD tPHL 0V 10% tr 90% 90% VOD(H) 0V 10% S1 to PU or PD VOD(L) tf Figure 3. Driver Delay and Transition Time Test Waveforms Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD09 7 SN65HVD09 SLLS941 – DECEMBER 2008............................................................................................................................................................................................ www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) Input B + Generator (see Note A) 50 Ω IO VID Output Input B − Generator (see Note A) VO 50 Ω CL = 15 pF † † CDEO, CDE1, CDE2, BSR, CRE, and DE/RE at 0.8 V ‡ All nine receivers are enabled and switching. Figure 4. Receiver Propagation Delay and Transition Time Test Circuit A. All input pulses are supplied by a generator having the following characteristics: tr ≤ 6 ns, tf ≤ 6 ns, PRR ≤ 1 MHz, duty cycle = 50%, ZO = 50 Ω. B. All resistances are in Ω and ±5%, unless otherwise indicated. C. All capacitances are in pF and ±10%, unless otherwise indicated. D. All indicated voltages are ±10 mV. 3V Input B − 1.5 V 1.5 V Input B + 0V tPLH Output tPHL 1.4 V 10% 90% VOH 90% tr 1.4 V 10% VOL tf Figure 5. Receiver Delay and Transition Time Waveforms 4.5 V PU S1 B+ 50 pF A 0 V or 3 V VOD 165 Ω PD 165 Ω 375 Ω 75 Ω 375 Ω B− DE/RE See Table 1 S2 50 pF† Input † Includes probe and jig capacitance in two places. Figure 6. Driver Enable and Disable Time Test Circuit 8 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD09 SN65HVD09 www.ti.com............................................................................................................................................................................................ SLLS941 – DECEMBER 2008 Table 1. Enabling for Driver Enable and Disable Time DRIVER BSR CDE0 CDE1 CDE2 1–8 H H L L CRE X 9 L H H H H 3V Input, DE/RE 1.5 V 1.5 V 0V tPZH tPHZ VOD(H) 0V 0V Output, VOD ∼ −1 V tPZL tPLZ ∼1V 0V Output, VOD A at 3V S1 to PD 0V VOD(L) A at 0V S1 to PU Figure 7. Driver Enable Time Waveforms NOTES: A. All input pulses are supplied by a generator having the following characteristics: tr ≤ 6 ns, tf ≤ 6 ns, PRR ≤ 1 MHz, duty cycle = 50%, ZO = 50 Ω. B. All resistances are in Ω and ±5%, unless otherwise indicated. C. All capacitances are in pF and ±10%, unless otherwise indicated. D. All indicated voltages are ±10 mV. VT 0 V or 3 V 3 V or 0 V † A Output DE/RE Input 620 Ω B+ † B− 40 pF‡ CDEO is high, CDE1, CDE2, BSR, and CRE are low, all others are open. ‡ Includes probe and jig capacitance. Figure 8. Receiver Enable and Disable Time Test Circuit Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD09 9 SN65HVD09 SLLS941 – DECEMBER 2008............................................................................................................................................................................................ www.ti.com 3V Input 1.4 V 1.4 V 0V tPLZ tPZL 1.4 V Output VOD 1.4 V B + at 0 V B − at 3 V VT = VCC Indeterminate tPZH tPHZ 1.4 V Output 1.4 V B + at 3 V B − at 0 V VT = 0 Indeterminate VOD Figure 9. Receiver Enable and Disable Time Waveforms NOTES: 10 A. All input pulses are supplied by a generator having the following characteristics: tr ≤ 6 ns, tf ≤ 6 ns, PRR ≤ 1 MHz, duty cycle = 50%, ZO = 50 Ω. B. All resistances are in Ω and ±5%, unless otherwise indicated. C. All capacitances are in pF and ±10%, unless otherwise indicated. D. All indicated voltages are ±10 mV. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD09 SN65HVD09 www.ti.com............................................................................................................................................................................................ SLLS941 – DECEMBER 2008 TYPICAL CHARACTERISTICS AVERAGE SUPPLY CURRENT vs FREQUENCY LOGIC INPUT CURRENT vs INPUT VOLTAGE − 30 250 200 I I − Logic Input Current − m A I CC − Average Supply Current − mA A, DE/RE,CRE,BSR − 25 150 100 9 Drivers 50 − 20 − 15 − 10 −5 9 Receivers 0 0.001 0 0.01 0.1 1 10 0 100 1 2 3 VI − Input Voltage − V f − Frequency − MHz Figure 10. Figure 11. BUS INPUT CURRENT vs INPUT VOLTAGE DRIVER LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 15 VOL − Low-Level Output Voltage − V 5 0 II − Input Current − mA 5 2.5 10 −5 −10 −20 4 2 1.5 1 0.5 0 − 15 − 10 −5 0 5 10 15 20 0 10 20 30 40 50 60 70 80 90 100 IOL − Low-Level Output Current − mA VI − Input Voltage − V Figure 12. Figure 13. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD09 11 SN65HVD09 SLLS941 – DECEMBER 2008............................................................................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (continued) DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs TEMPERATURE 4 1.9 3.5 1.8 Differential Output Voltage - V VOH − High-Level Output Voltage − V DRIVER HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 3 2.5 2 1.5 1 0.5 1.6 PU/PD Load 1.5 1.4 0 − 20 − 40 −60 −80 IOH − High-Level Output Current − mA 1.3 1.2 1 -40 − 100 0 20 40 Temperature - °C Figure 15. RECEIVER PROPAGATION DELAY TIME vs TEMPERATURE DRIVER PROPAGATION DELAY TIME vs TEMPERATURE 60 80 60 80 13 tPHL 12 Driver Propagation Delay - ns 12.5 12 11.5 11 10.5 10 -40 -20 Figure 14. 13 0 20 40 Temperature - °C 11 10 tPLH 9 8 tPLH -20 tPHL 60 80 7 -40 Figure 16. 12 RL = 54 W 1.1 0 Receiver Propagation Delay - ns RL = 100 W 1.7 -20 0 20 40 Temperature - °C Figure 17. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD09 SN65HVD09 www.ti.com............................................................................................................................................................................................ SLLS941 – DECEMBER 2008 TYPICAL CHARACTERISTICS (continued) DRIVER OUTPUT CURRENT vs SUPPLY VOLTAGE 100 TA = 25°C 80 I O − Output Current − mA IOH 60 40 20 0 −20 −40 −60 −80 IOL 0 1 2 3 4 VCC − Supply Voltage − V Figure 18. 5 6 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD09 13 SN65HVD09 SLLS941 – DECEMBER 2008............................................................................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (continued) SCHEMATICS OF INPUTS AND OUTPUTS DE/RE, CRE, BSR, AND A Inputs CDE0, CDE1, AND CDE2 Inputs VCC VCC 100 kΩ 1 kΩ 1 kΩ Input Input 100 kΩ 8V 8V B + Input B − Input VCC 100 kΩ 16 V VCC 2 kΩ 2 kΩ 16 V 18 kΩ Input 18 kΩ Input 100 kΩ 4 kΩ 4 kΩ 16 V 16 V B + AND B − Outputs VCC A Output VCC 2 kΩ 16 V 18 kΩ 40 Ω Output Output 8V 4 kΩ 16 V 14 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD09 SN65HVD09 www.ti.com............................................................................................................................................................................................ SLLS941 – DECEMBER 2008 APPLICATION INFORMATION FUNCTION TABLES RECEIVER DRIVER B+ B+ A A B− INPUTS B− B +1 B −1 OUTPUT A INPUT A L H H L L H L H TRANSCEIVER OUTPUTS B+ B− L H H L DRIVER WITH ENABLE B+ A B+ B− A B− DE/RE DE/RE DE/RE L L H H INPUTS A B +1 − − L H L H − − B −1 A H L − − L H − − INPUTS DE/RE A OUTPUTS B− B+ − − L H L L H H − − H L WIRED-OR DRIVER L H L H OUTPUTS B− B+ Z Z L H Z Z H L TWO-ENABLE INPUT DRIVER B+ A A B− B+ B− DE/RE INPUT A L H OUTPUTS B+ B− Z H Z L INPUTS DE/RE A L L H H L H L H OUTPUTS B− B+ Z H L H Z L H L NOTE: H = high level, L = low level, X = irrelevant, Z = high impedance (off) (1) An H in this column represents a voltage of 200 mV or higher than the other bus input. An L represents a voltage of 200 mV or lower than the other bus input. Any voltage less than 200 mV results in an indeterminate receiver output. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD09 15 SN65HVD09 SLLS941 – DECEMBER 2008............................................................................................................................................................................................ www.ti.com VCC VCC 620 Ω 1 nB + nA I/O EN 620 Ω 1 Connector + nB − (b) ACTIVE-LOW BIDIRECTIONAL I/O WITH SEPARATE ENABLE VCC VCC 620 Ω 1 nB + nA − + nB − − EN nDE/RE (d) SEPARATE ACTIVE-HIGH INPUT, OUTPUT, AND ENABLE (c) WIRED-OR DRIVER AND ACTIVE-HIGH INPUT VCC VCC 620 Ω 1 O2 nB + nA O2 nDE/RE I Connector I + nB − O 620 Ω 1 Connector 620 Ω 1 I + nDE/RE (a) ACTIVE-HIGH BIDIRECTIONAL I/O WITH SEPARATE ENABLE VCC − nB − EN nDE/RE nB + nA I/O − Connector nB + nA − nB − + EN Connector 620 Ω 1 Connector nA I nB + nB − O − + nDE/RE nDE/RE 620 Ω (e) SEPARATE ACTIVE-LOW INPUT AND OUTPUT AND ACTIVE-HIGH ENABLE 1: When 0 is open drain 2: Must be open-drain or 3-state output (1) When 0 is open drain (2) Must be open-drain or 3-state output (f) WIRED-OR DRIVER AND ACTIVE-LOW INPUT NOTE: The BSR, CRE, A, and DE/RE inputs have internal pullup resistors. CDE0, CDE1, and CDE2 have internal pulldown resistors. Figure 19. Typical Transceiver Connections 16 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD09 SN65HVD09 www.ti.com............................................................................................................................................................................................ SLLS941 – DECEMBER 2008 CHANNEL LOGIC CONFIGURATIONS WITH CONTROL INPUT LOGIC The following logic diagrams show the positive-logic representation for all combinations of control inputs. The control inputs are from MSB to LSB; the BSR, CDE0, CDE1, CDE2, and CRE bit values are shown below the diagrams. Channel 1 is at the top of the logic diagrams; channel 9 is at the bottom of the logic diagrams. Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Figure 19. 00000 Figure 20. 00001 Hi-Z Figure 21. 00010 Figure 22. 00011 Figure 23. 00100 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD09 17 SN65HVD09 SLLS941 – DECEMBER 2008............................................................................................................................................................................................ www.ti.com Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Figure 24. 00101 Hi-Z Figure 25. 00110 Figure 26. 00111 Figure 28. 01001 Figure 27. 01000 18 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD09 SN65HVD09 www.ti.com............................................................................................................................................................................................ SLLS941 – DECEMBER 2008 Figure 32. 01101 Figure 29. 01010 Figure 30. 01011 Figure 33. 01110 Figure 31. 01100 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD09 19 SN65HVD09 SLLS941 – DECEMBER 2008............................................................................................................................................................................................ www.ti.com Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z VCC VCC VCC VCC VCC VCC VCC VCC Hi-Z VCC Hi-Z Hi-Z Hi-Z VCC Hi-Z Hi-Z Figure 34. 01111 VCC Figure 35. 10000 and 10001 VCC Hi-Z VCC Hi-Z Hi-Z VCC Hi-Z Hi-Z Figure 36. 10010 and 10011 Hi-Z Figure 37. 10100 and 10101 VCC VCC Hi-Z Figure 38. 10110 and 10111 20 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD09 SN65HVD09 www.ti.com............................................................................................................................................................................................ SLLS941 – DECEMBER 2008 Hi-Z Figure 39. 11000 and 11001 Hi-Z Figure 40. 11010 and 11011 Hi-Z Figure 41. 11100 and 11101 Hi-Z Figure 42. 11110 and 11111 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD09 21 PACKAGE MATERIALS INFORMATION www.ti.com 5-Jan-2022 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN65HVD09DGGR Package Package Pins Type Drawing TSSOP DGG 56 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 8.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 15.6 1.8 12.0 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 5-Jan-2022 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65HVD09DGGR TSSOP DGG 56 2000 367.0 367.0 45.0 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 5-Jan-2022 TUBE *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) SN65HVD09DGG DGG TSSOP 56 35 530 11.89 3600 4.9 Pack Materials-Page 3 PACKAGE OUTLINE DGG0056A TSSOP - 1.2 mm max height SCALE 1.200 SMALL OUTLINE PACKAGE C 8.3 TYP 7.9 SEATING PLANE PIN 1 ID AREA A 0.1 C 54X 0.5 56 1 14.1 13.9 NOTE 3 2X 13.5 28 B 6.2 6.0 29 56X 0.27 0.17 0.08 1.2 MAX C A B (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0 -8 0.15 0.05 0.75 0.50 DETAIL A TYPICAL 4222167/A 07/2015 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. Reference JEDEC registration MO-153. www.ti.com EXAMPLE BOARD LAYOUT DGG0056A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 56X (1.5) SYMM 1 56 56X (0.3) 54X (0.5) (R0.05) TYP SYMM 28 29 (7.5) LAND PATTERN EXAMPLE SCALE:6X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK 0.05 MAX ALL AROUND 0.05 MIN ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4222167/A 07/2015 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DGG0056A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 56X (1.5) SYMM 1 56 56X (0.3) 54X (0.5) (R0.05) TYP SYMM 29 28 (7.5) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4222167/A 07/2015 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. 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