SN65HVD09-EP
SLLSEA3 – DECEMBER 2011
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9-CHANNEL RS-422 / RS-485 TRANSCEIVER
Check for Samples: SN65HVD09-EP
FEATURES
1
•
•
•
•
•
•
•
Designed to Operate at up to 20 Million Data
Transfers per Second on Each RS-422/RS-485
Channel
SN65HVD09 Packaged in Thin Shrink
Small-Outline Package with 0.5-mm Pin Pitch
ESD Protection on Bus Pins Exceeds 12kV
Low Disabled Supply Current 8 mA Typ
Thermal Shutdown Protection
Positive- and Negative-Current Limiting
Power-Up/Down Glitch Protection
SN65HVD09 DGG
(TOP VIEW)
GND
1
56
CDE2
BSR
2
55
CDE1
GRE
3
54
CDE0
1A
4
53
9B+
1DE/RE
5
52
9B-
2A
6
51
8B+
2DE/RE
7
50
8B-
3A
8
49
7B+
3DE/RE
9
48
7B-
4A
10
47
6B+
4DE/RE
11
46
6B-
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
•
•
•
•
•
•
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
VCC
12
45
VCC
GND
13
44
GND
GND
14
43
GND
GND
15
42
GND
GND
16
41
GND
GND
17
40
VCC
18
39
GND
VCC
5A
19
38
5B+
5DE/RE
20
37
5B-
6A
21
36
4B+
6DE/RE
22
35
4B-
7A
23
34
3B+
7DE/RE
24
33
3B-
8A
25
32
2B+
8DE/RE
26
31
2B-
9A
27
30
1B+
9DE/RE
28
29
1B-
Terminals 13 through 17, and 40 through 44 are
connected together to the package lead frame
and signal ground.
9 Differential
RS-422/RS-485
I/O Channels
Configuration and
Control Logic
HVD09
9 Single-ended TTL
I/O Channels
DESCRIPTION
The SN65HVD09 is a 9-channel RS-422 / RS-485 transceiver suitable for industrial applications. It offers
improved switching performance, a small package, and high ESD protection. The precise skew limits ensures
that the propagation delay times, not only from channel-to-channel but from device-to-device, are closely
matched for the tight skew budgets associated with high-speed parallel data buses.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
SN65HVD09-EP
SLLSEA3 – DECEMBER 2011
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Patented thermal enhancements are used in the thin shrink, small-outline package (TSSOP), allowing operation
over the industrial temperature range. The TSSOP package offers very small board area requirements while
reducing the package height to 1 mm. This provides more board area and allows component mounting to both
sides of the printed circuit boards for low-profile, space-restricted applications such as small form-factor hard disk
drives.
The HVD09 can withstand electrostatic discharges exceeding 12 kV using the human-body model, and 600 V
using the machine model on the RS-485 I/O terminals. This provides protection from the noise that can be
coupled into external cables. The other terminals of the device can withstand discharges exceeding 4 kV and 400
V respectively.
Each of the nine half-duplex channels of the HVD09 is designed to operate with either RS-422 or RS-485
communication networks.
The SN65HVD09 is characterized for operation from –40°C to 85°C.
2
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
TA
PACKAGE (2)
ORDERABLE PART
NUMBER
TOP-SIDE MARKING
VID NUMBER
–40°C to 85°C
TSSOP-DGG
SN65HVD09IDGGREP
SN65HVD09EP
V62/12607-01XE
(1)
(2)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
PIN FUNCTIONS
PIN
NAME
NO.
LOGIC
LEVEL
I/O
TERMINATION
DESCRIPTION
1A to 9A
4,6,8,10,
19,21,23,
25,27
TTL
I/O
Pullup
1B– to 9B–
29,31,33,
35,37,.46
,
48,50,52
RS-485
I/O
Pulldown
1B+ to 9B+
30,32,34,
36,38,47,
49,51,53
RS-485
I/O
Pullup
1B+ to 9B+ are the noninverted data signals of the balanced pair to/from the bus.
BSR
2
TTL
Input
Pullup
BSR is the bit significant response. BSR disables receivers 1 through 8 and enables
wired-OR drivers when BSR and DE/RE and CDE1 or CDE2 are high. Channel 9 is
placed in a high-impedance state with BSR high.
CDE0
54
TTL
Input
Pulldown
CDE0 is the common driver enable 0. Its input signal enables all drivers when CDE0 and
1DE/RE – 9DE/RE are high.
CDE1
55
TTL
Input
Pulldown
CDE1 is the common driver enable 1. Its input signal enables drivers 1 to 4 when CDE1 is
high and BSR is low.
CDE2
56
TTL
Input
Pulldown
CDE2 is the common driver enable 2. When CDE2 is high and BSR is low, drivers 5 to 8
are enabled.
CRE
1A to 9A carry data to and from the communication controller.
1B– to 9B– are the inverted data signals of the balanced pair to/from the bus.
3
TTL
Input
Pullup
CRE is the common receiver enable. When high, CRE disables receiver channels 5 to 9.
1DE/RE to
9DE/RE
5,7,9,11,
20,22,24,
26,28
TTL
Input
Pullup
1DE/RE–9DE/RE are direction controls that transmit data to the bus when it and CDE0
are high. Data is received from the bus when 1DE/RE–9DE/RE and CRE and BSR are
low and CDE1 and CDE2 are low.
GND
1,13,14,
15,16,17,
40,41,42,
43,44
NA
Power
NA
GND is the circuit ground. All GND terminals except terminal 1 are physically tied to the
die pad for improved thermal conductivity. (1)
VCC
12,18,39,
45
NA
Power
NA
Supply voltage
(1)
Terminal 1 must be connected to signal ground for proper operation.
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LOGIC DIAGRAM (POSITIVE LOGIC)
CDE0
CDE1
BSR
1A
1DE/RE
2A
2DE/RE
3A
3DE/RE
4A
4DE/RE
CDE2
CRE
5A
5DE/RE
6A
6DE/RE
7A
7DE/RE
8A
8DE/RE
54
55
2
30
4
29
5
6
7
8
9
10
11
Channel 2
Channel 3
Channel 4
9DE/RE
4
32
31
34
33
36
35
2B+
2B−
3B+
3B−
4B+
4B−
56
3
38
19
37
5B+
5B−
20
21
22
23
24
25
26
Channel 6
Channel 7
Channel 8
2
9A
1B+
1B−
27
BSR
3
BSR
47
46
49
48
51
50
6B+
6B−
7B+
7B−
8B+
8B−
54
CRE
CDE0
53
9B+
52
9B−
28
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ABSOLUTE MAXIMUM RATINGS (1)
VCC
VALUE
UNIT
Supply voltage range (2)
–0.3 to 6
V
Bus voltage range
–10 to 15
V
–0.3 to VCC +0.5
V
Data I/O and control (A side) voltage range
IO
±40
mA
B side and GND, ESD HBM
12
kV
B side and GND, ESD MM
400
V
All terminals, ESD HBM
4
kV
All terminals, ESD MM
400
V
Receiver output current
Electrostatic discharge
Continuous total power dissipation
(1)
(2)
(3)
(3)
Internally Limited
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.r
All voltage values are with respect to the GND terminals.
The maximum operating junction temperature is internally limited. Use the Dissipation Rating Table to operate below this temperature.
DISSIPATION RATINGS
(1)
PACKAGE
TA ≤ 25°C
OPERATING FACTOR (1)
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
DGG
2500 mW
20 mW/°C
1600 mW
1300 mW
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
PACKAGE THERMAL CHARACTERISTICS
MIN
NOM
MAX
UNIT
θJA
Junction-to-ambient thermal
resistance
DGG, board-mounted, no air flow
50
θJC
Junction-to-case thermal resistance
DGG
27
°C/W
TSD
Thermal shutdown temperature
165
°C
°C/W
RECOMMENDED OPERATING CONDITIONS
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
VO, VI, or VIC
Voltage at any bus terminal (separately or common-mode)
Except nB+, nB– (1)
Driver
IO
Output current
TA
Operating free-air temperature
(1)
nB+ or nB–
Receiver
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
2
V
0.8
V
–7
12
V
–60
60
mA
–8
8
mA
–40
85
°C
n=1-9
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ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
|VOD|
VOH
SN65HVD09
TEST CONDITIONS
Driver differential output voltage
magnitude
High-level output voltage
RS-422 load,
RL = 100 Ω
RS-485 load,
RL = 54 Ω
See Figure 1
MIN
TYP (1)
0.56
1.6
MAX
1.4
Pull-Up Pull-Down Load
See Figure 2
1
1.5
A side, IOH = –8 mA, VID = 200 mV,
See Figure 4
4
4.5
B side,
See Figure 2
3
A side, IOH = 8 mA, VID = –200 mV,
See Figure 4
0.6
B side,
See Figure 2
1
UNIT
V
V
V
0.8
V
VOL
Low-level output voltage
VIT+
Receiver positive-going differential
input threshold voltages
IOH = –8 mA,
See Figure 4
VIT–
Receiver negativegoing differential
input threshold voltage
IOL = 8 mA,
SeeFigure 4
Vhys
Receiver input hysteresis
(VIT+ – VIT–)
VCC = 5 V,
TA = 25°C
VIH = 12 V
VCC = 5 V,
1
mA
VIH = 12 V
VCC = 0,
1
mA
VIH = –7 V
VCC = 5 V,
VIH = –7 V
VCC = 0,
II
IIH
Bus input current
High-level input current
nA, BSR, DE/RE, and CRE,
VIH = 2 V
CDE0, CDE1, and CDE2,
VIH = 2V
nA, BSR, DE/RE, and CRE,
VIL = 0.8 V
CDE1, CDE1, and CDE2,
VIL = 0.8 V
IIL
Low-level input current
IOS
Short circuit output current
nB+ or nB–
IOZ
High-impedance-state output
current
nA
ICC
Supply current
CO
Output capacitance
0.2
–0.2
24
Other input at 0 V
V
45
(1)
(2)
6
Power dissipation capacitance
mV
–0.8
–0.4
mA
–0.8
–0.3
mA
–100
μA
100
–100
μA
μA
100
μA
±260
mA
See III
Disabled
10
All drivers enabled, no load
60
All receivers enabled, no load
Cpd
V
See IIH and IIL
nB+ or nB–
(2)
V
45
nB+ or nB– to GND
18
Receiver
40
Driver
mA
100
pF
pF
All typical values are at VCC = 5 V, TA = 25°C.
Cpd determines the no-load dynamic supply current consumption, IS = CPD × VCC × f + ICC
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DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SN65HVD09
TYP (1) MAX
2.5
13.5
ns
5
ns
tpd
Propagation delay time, tPHL or tPLH (see Figure 2 and Figure 3)
tsk(p)
Pulse skew, |tPHL – tPLH|
tf
Fall time
S1 to B, See Figure 3
4
tr
Rise time
See Figure 3
8
ten
Enable time, control inputs to active output
tdis
Disable time, control inputs to high-impedance output
tPHZ
Propagation delay time, high-level to high-impedance output
tPLZ
Propagation delay time, low-level to high-impedance output
tPZH
Propagation delay time, high-impedance to high-level output
tPZL
Propagation delay time, high-impedance to low-level output
(1)
UNIT
MIN
See Figure 6 and
Figure 7
ns
ns
50
ns
225
ns
17
225
ns
25
225
ns
17
50
ns
17
50
ns
All typical values are at VCC = 5 V, TA = 25°C.
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
tpd
TEST CONDITIONS
Propagation delay time, tPHL or tPLH (see Figure 2 and Figure 3)
tsk(lim)
Skew limit, maximum tpd – minimum tpd
tsk(p)
Pulse skew, |tPHL – tPLH|
tt
Transition time (tr or tf)
ten
tdis
SN65HVD09
TYP (1) MAX
8
14.5
ns
5
ns
5
ns
(2)
0.6
2
ns
Enable time, control inputs to active output
31
ns
Disable time, control inputs to high-impedance output
41
ns
tPHZ
Propagation delay time, high-level to high-impedance output
34
ns
tPLZ
Propagation delay time, low-level to high-impedance output
14
ns
tPZH
Propagation delay time, high-impedance to high-level output
30
ns
tPZL
Propagation delay time, high-impedance to low-level output
30
ns
(1)
(2)
See Figure 5
UNIT
MIN
See Figure 8 and
Figure 9
All typical values are at VCC = 5 V, TA = 25°C.
This parameter is applicable at one VCC and operating temperature within the recommended operating conditions and to any two
devices.
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PARAMETER MEASUREMENT INFORMATION
RL/2
B+
A
Input
VOC
B-
CL = 50 pF ±20%
RL/2
CL Includes Fixture and
Instrumentation Capacitance
Figure 1. Driver Test Circuit, RS-422 and RS-485 Loading
5V
PU
S1
B+
IO
15 pF
II
Input
(see Note A)
A
165 Ω
PD
VOD
165 Ω
VO
VI
375 Ω
75 Ω
375 Ω
IO
B−
VO
†
†
‡
S2
15 pF
CDEO and DE/RE are at 2 V, BSR is at 0.8V, and all others are open.
All nine drivers are enabled, similarly loaded, and switching.
Figure 2. Driver Test Circuit, Pull-Up and Pull-Down Loading‡
3V
Input
1.5 V
1.5 V
0V
tPLH
Output, VOD
tPHL
0V
10%
tr
90%
90%
VOD(H)
0V
10%
S1 to PU or PD
VOD(L)
tf
Figure 3. Driver Delay and Transition Time Test Waveforms
8
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PARAMETER MEASUREMENT INFORMATION (continued)
Input B +
Generator
(see Note A)
50 Ω
IO
VID
Output
Input B −
Generator
(see Note A)
VO
50 Ω
CL = 15 pF
†
†
CDEO, CDE1, CDE2, BSR, CRE, and DE/RE at 0.8 V
‡
All nine receivers are enabled and switching.
Figure 4. Receiver Propagation Delay and Transition Time Test Circuit
A.
All input pulses are supplied by a generator having the following characteristics: tr ≤ 6 ns, tf ≤ 6 ns, PRR ≤ 1 MHz,
duty cycle = 50%, ZO = 50 Ω.
B.
All resistances are in Ω and ±5%, unless otherwise indicated.
C.
All capacitances are in pF and ±10%, unless otherwise indicated.
D.
All indicated voltages are ±10 mV.
3V
Input B −
1.5 V
1.5 V
Input B +
0V
tPLH
Output
tPHL
1.4 V
10%
90%
VOH
90%
tr
1.4 V
10%
VOL
tf
Figure 5. Receiver Delay and Transition Time Waveforms
4.5 V
PU
S1
B+
50 pF
A
0 V or 3 V
VOD
165 Ω
PD
165 Ω
375 Ω
75 Ω
375 Ω
B−
DE/RE
See Table 1
S2
50 pF†
Input
†
Includes probe and jig capacitance in two places.
Figure 6. Driver Enable and Disable Time Test Circuit
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Table 1. Enabling for Driver Enable and Disable Time
DRIVER
BSR
CDE0
CDE1
CDE2
CRE
1–8
H
H
L
L
X
9
L
H
H
H
H
3V
Input, DE/RE
1.5 V
1.5 V
0V
tPZH
tPHZ
VOD(H)
0V
0V
Output, VOD
∼ −1 V
tPZL
tPLZ
∼1V
0V
Output, VOD
A at 3V
S1 to PD
0V
VOD(L)
A at 0V
S1 to PU
Figure 7. Driver Enable Time Waveforms
NOTES:
A. All input pulses are supplied by a generator having the following characteristics: tr ≤ 6 ns, tf ≤ 6 ns, PRR ≤ 1 MHz,
duty cycle = 50%, ZO = 50 Ω.
B. All resistances are in Ω and ±5%, unless otherwise indicated.
C. All capacitances are in pF and ±10%, unless otherwise indicated.
D. All indicated voltages are ±10 mV.
VT
0 V or 3 V
3 V or 0 V
†
A
Output
DE/RE
Input
620 Ω
B+
†
B−
40 pF‡
CDEO is high, CDE1, CDE2, BSR, and CRE are low,
all others are open.
‡ Includes
probe and jig capacitance.
Figure 8. Receiver Enable and Disable Time Test Circuit
10
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3V
Input
1.4 V
1.4 V
0V
tPLZ
tPZL
1.4 V
Output
VOD
1.4 V
B + at 0 V
B − at 3 V
VT = VCC
Indeterminate
tPHZ
tPZH
1.4 V
Output
1.4 V
B + at 3 V
B − at 0 V
VT = 0
Indeterminate
VOD
Figure 9. Receiver Enable and Disable Time Waveforms
NOTES:
A.
All input pulses are supplied by a generator having the following characteristics: tr ≤ 6 ns, tf ≤ 6 ns, PRR ≤ 1 MHz,
duty cycle = 50%, ZO = 50 Ω.
B.
All resistances are in Ω and ±5%, unless otherwise indicated.
C.
All capacitances are in pF and ±10%, unless otherwise indicated.
D.
All indicated voltages are ±10 mV.
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TYPICAL CHARACTERISTICS
AVERAGE SUPPLY CURRENT
vs
FREQUENCY
LOGIC INPUT CURRENT
vs
INPUT VOLTAGE
−30
250
200
I I − Logic Input Current − m A
I CC − Average Supply Current − mA
A, DE/RE,CRE,BSR
−25
150
100
9 Drivers
50
−20
−15
−10
−5
9 Receivers
0
0.001
0
0.01
0.1
1
10
0
100
1
2
3
VI − Input Voltage − V
f − Frequency − MHz
Figure 10.
Figure 11.
BUS
INPUT CURRENT
vs
INPUT VOLTAGE
DRIVER
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
15
VOL − Low-Level Output Voltage − V
0
II
− Input Current − mA
5
−5
2
1.5
1
0.5
0
−15
−10
−5
0
5
10
15
20
0
10
VI − Input Voltage − V
Figure 12.
12
5
2.5
10
−10
−20
4
20
30
40
50
60
70
80
90 100
IOL − Low-Level Output Current − mA
Figure 13.
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TYPICAL CHARACTERISTICS (continued)
DRIVER
DIFFERENTIAL OUTPUT VOLTAGE
vs
TEMPERATURE
4
1.9
3.5
1.8
Differential Output Voltage - V
VOH − High-Level Output Voltage − V
DRIVER
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
3
2.5
2
1.5
1
0.5
1.6
PU/PD Load
1.5
1.4
RL = 54 W
1.3
1.2
1.1
1
-40
0
0
−20
− 40
−60
−80
IOH − High-Level Output Current − mA
− 100
0
20
40
Temperature - °C
60
80
60
80
Figure 15.
RECEIVER
PROPAGATION DELAY TIME
vs
TEMPERATURE
DRIVER
PROPAGATION DELAY TIME
vs
TEMPERATURE
13
tPHL
12
Driver Propagation Delay - ns
12.5
12
11.5
11
10.5
10
-40
-20
Figure 14.
13
Receiver Propagation Delay - ns
RL = 100 W
1.7
0
20
40
Temperature - °C
11
10
tPLH
9
8
tPLH
-20
tPHL
60
80
7
-40
-20
Figure 16.
0
20
40
Temperature - °C
Figure 17.
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TYPICAL CHARACTERISTICS (continued)
DRIVER
OUTPUT CURRENT
vs
SUPPLY VOLTAGE
100
TA = 25°C
80
I O − Output Current − mA
IOH
60
40
20
0
−20
−40
−60
−80
14
IOL
0
1
2
3
4
VCC − Supply Voltage − V
Figure 18.
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5
6
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TYPICAL CHARACTERISTICS (continued)
SCHEMATICS OF INPUTS AND OUTPUTS
DE/RE, CRE, BSR, AND
A Inputs
CDE0, CDE1, AND CDE2 Inputs
VCC
VCC
100 kΩ
1 kΩ
1 kΩ
Input
Input
100 kΩ
8V
8V
B + Input
B − Input
VCC
100 kΩ
16 V
VCC
2 kΩ
2 kΩ
16 V
18 kΩ
Input
18 kΩ
Input
100 kΩ
4 kΩ
4 kΩ
16 V
16 V
B + AND B − Outputs
VCC
A Output
VCC
2 kΩ
16 V
18 kΩ
40 Ω
Output
Output
8V
4 kΩ
16 V
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APPLICATION INFORMATION
FUNCTION TABLES
RECEIVER
DRIVER
B+
B+
A
A
B−
INPUTS
B−
B +1
B −1
OUTPUT
A
INPUT
A
L
H
H
L
L
H
L
H
TRANSCEIVER
OUTPUTS
B+
B−
L
H
H
L
DRIVER WITH ENABLE
B+
A
B+
B−
A
B−
DE/RE
DE/RE
DE/RE
L
L
H
H
INPUTS
A B +1
−
−
L
H
L
H
−
−
B −1
A
H
L
−
−
L
H
−
−
INPUTS
DE/RE
A
OUTPUTS
B−
B+
−
−
L
H
L
L
H
H
−
−
H
L
WIRED-OR DRIVER
L
H
L
H
OUTPUTS
B−
B+
Z
Z
L
H
Z
Z
H
L
TWO-ENABLE INPUT DRIVER
B+
A
A
B−
B+
B−
DE/RE
INPUT
A
OUTPUTS
B+
B−
L
H
Z
H
Z
L
INPUTS
DE/RE A
L
L
H
H
L
H
L
H
OUTPUTS
B−
B+
Z
H
L
H
Z
L
H
L
NOTE: H = high level, L = low level, X = irrelevant, Z = high impedance (off)
(1)
16
An H in this column represents a voltage of 200 mV or higher than the other bus input. An L represents a voltage of
200 mV or lower than the other bus input. Any voltage less than 200 mV results in an indeterminate receiver output.
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VCC
VCC
620 Ω 1
nB +
nA
I/O
EN
620 Ω 1
Connector
+
nB −
(b) ACTIVE-LOW BIDIRECTIONAL I/O
WITH SEPARATE ENABLE
VCC
VCC
620 Ω 1
nB +
nA
−
+
nB −
−
EN
nDE/RE
(d) SEPARATE ACTIVE-HIGH INPUT, OUTPUT,
AND ENABLE
(c) WIRED-OR DRIVER AND ACTIVE-HIGH INPUT
VCC
VCC
620 Ω 1
O2
nB +
nA
O2
nDE/RE
I
Connector
I
+
nB −
O
620 Ω 1
Connector
620 Ω 1
I
+
nDE/RE
(a) ACTIVE-HIGH BIDIRECTIONAL I/O
WITH SEPARATE ENABLE
VCC
−
nB −
EN
nDE/RE
nB +
nA
I/O
−
Connector
nB +
nA
−
nB −
+
EN
Connector
620 Ω 1
Connector
nB +
nA
I
nB −
O
−
+
nDE/RE
nDE/RE
620 Ω
(e) SEPARATE ACTIVE-LOW INPUT AND
OUTPUT AND ACTIVE-HIGH ENABLE
1: When 0 is open drain
2: Must be open-drain or 3-state output
(1)
When 0 is open drain
(2)
Must be open-drain or 3-state output
(f) WIRED-OR DRIVER AND ACTIVE-LOW INPUT
NOTE: The BSR, CRE, A, and DE/RE inputs have internal pullup resistors. CDE0, CDE1, and CDE2 have internal pulldown
resistors.
Figure 19. Typical Transceiver Connections
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CHANNEL LOGIC CONFIGURATIONS WITH CONTROL INPUT LOGIC
The following logic diagrams show the positive-logic representation for all combinations of control inputs. The
control inputs are from MSB to LSB; the BSR, CDE0, CDE1, CDE2, and CRE bit values are shown below the
diagrams. Channel 1 is at the top of the logic diagrams; channel 9 is at the bottom of the logic diagrams.
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Figure 19. 00000
18
Hi-Z
Figure 20. 00001
Figure 21. 00010
Figure 22. 00011
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Figure 23. 00100
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Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Figure 24. 00101
Hi-Z
Figure 25. 00110
Figure 26. 00111
Figure 28. 01001
Figure 27. 01000
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Figure 32. 01101
Figure 29. 01010
20
Figure 30. 01011
Figure 33. 01110
Figure 31. 01100
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Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Hi-Z
VCC
Hi-Z
Hi-Z
Hi-Z
VCC
Hi-Z
Hi-Z
Figure 34. 01111
VCC
Figure 35.
10000
and 10001
VCC
Hi-Z
VCC
Hi-Z
Hi-Z
VCC
Hi-Z
Hi-Z
Figure 36. 10010
and 10011
Hi-Z
Figure 37. 10100
and 10101
VCC
VCC
Hi-Z
Figure 38. 10110
and 10111
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Hi-Z
Figure 39. 11000
and 11001
Hi-Z
Figure 40. 11010
and 11011
Hi-Z
Figure 41. 11100
and 11101
Hi-Z
Figure 42. 11110
and 11111
22
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
(4/5)
(6)
SN65HVD09IDGGREP
ACTIVE
TSSOP
DGG
56
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
SN65HVD09EP
V62/12607-01XE
ACTIVE
TSSOP
DGG
56
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
SN65HVD09EP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
