SN65HVD10, SN65HVD11, SN65HVD12
SN75HVD10, SN75HVD11, SN75HVD12
SLLS505P – FEBRUARY 2002 – REVISED FEBRUARY 2022
SNx5HVD1x 3.3-V RS-485 Transceivers
1 Features
3 Description
•
•
•
The SN65HVD10, SN75HVD10, SN65HVD11,
SN75HVD11, SN65HVD12, and SN75HVD12 bus
transceivers all combine a 3-state differential line
driver, as well as a differential input line receiver
that operates with a single 3.3-V power supply. They
are designed for balanced transmission lines and
meet or exceed ANSI standard TIA/EIA-485-A and
ISO 8482:1993. These differential bus transceivers
are monolithic integrated circuits, designed for
bidirectional data communication on multipoint bustransmission lines. The drivers and receivers have
active-high and active-low enables, that can be
externally connected together to function as direction
control. Very low device standby supply current, can
be achieved by disabling the driver and the receiver.
•
•
•
•
•
•
•
•
Operates with a 3.3-V supply
Bus-pin ESD protection exceeds 16-kV HBM
1/8 Unit-load option available (up to 256 nodes on
the bus)
Optional driver output transition times for signaling
rates 1of 1 Mbps, 10 Mbps, and
32 Mbps
Meets or exceeds the requirements of ANSI TIA/
EIA-485-A
Bus-pin short-circuit protection from –7 V to
12 V
Low-current standby mode: 1 µA, typical
Open-circuit, idle-bus, and shorted-bus fail-safe
receiver
Thermal shutdown protection
Glitch-free power-up and power-down protection
for hot-plugging applications
SN75176 footprint
2 Applications
•
•
•
•
•
•
•
Digital motor control
Utility meters
Chassis-to-chassis interconnects
Electronic security stations
Industrial process control
Building automation
Point-of-sale (POS) terminals and networks
The driver differential outputs and receiver differential
inputs connect internally to form a differential input/
output (I/O) bus port, that is designed to offer
minimum loading to the bus whenever the driver is
disabled or VCC = 0. These parts feature wide positive
and negative common-mode voltage ranges, making
them suitable for party-line applications.
Device Information
PACKAGE(1)
PART NUMBER
BODY SIZE (NOM)
SN65HVD10
SN65HVD11
SOIC (8)
4.90 mm × 3.91 mm
PDIP (8)
9.81 mm × 6.35 mm
SN65HVD12
SN75HVD10
SN75HVD11
SN75HVD12
(1)
R
R
R
A
RE
B
DE
D
For all available packages, see the orderable addendum at
the end of the data sheet.
R
A
RT
RT
D
A
R
B
A
D
R RE DE D
RE
B
DE
D
B
R
D
D
R RE DE D
Copyright © 2016, Texas Instruments Incorporated
Typical Application Diagram
1
The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN65HVD10, SN65HVD11, SN65HVD12
SN75HVD10, SN75HVD11, SN75HVD12
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SLLS505P – FEBRUARY 2002 – REVISED FEBRUARY 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information....................................................5
7.5 Driver Electrical Characteristics.................................. 5
7.6 Receiver Electrical Characteristics............................. 6
7.7 Power Dissipation Characteristics.............................. 6
7.8 Driver Switching Characteristics................................. 7
7.9 Receiver Switching Characteristics.............................8
7.10 Dissipation Ratings................................................... 8
7.11 Typical Characteristics.............................................. 9
8 Parameter Measurement Information.......................... 11
9 Detailed Description......................................................17
9.1 Overview................................................................... 17
9.2 Functional Block Diagram......................................... 17
9.3 Feature Description...................................................17
9.4 Device Functional Modes..........................................17
10 Application and Implementation................................ 19
10.1 Application Information........................................... 19
10.2 Typical Application.................................................. 20
11 Power Supply Recommendations..............................23
12 Layout...........................................................................23
12.1 Layout Guidelines................................................... 23
12.2 Layout Example...................................................... 24
12.3 Thermal Considerations..........................................24
13 Device and Documentation Support..........................26
13.1 Device Support....................................................... 26
13.2 Related Links.......................................................... 26
13.3 Receiving Notification of Documentation Updates..26
13.4 Support Resources................................................. 26
13.5 Trademarks............................................................. 26
13.6 Electrostatic Discharge Caution..............................26
13.7 Glossary..................................................................26
14 Mechanical, Packaging, and Orderable
Information.................................................................... 26
4 Revision History
Changes from Revision O (February 2017) to Revision P (February 2022)
Page
• Changed the Thermal Information table............................................................................................................. 5
Changes from Revision N (July 2015) to Revision O (February 2017)
Page
• Added MIN value of –55°C to the Storage temperature in Absolute Maximum Ratings ....................................4
Changes from Revision M (July 2013) to Revision N (July 2015)
Page
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ............................................................................................................................................................... 1
Changes from Revision L (July 2013) to Revision M (July 2013)
Page
• Changed the VIT+ TYP value From: –0.65 V To: –0.065 V ................................................................................ 6
Changes from Revision K (September 2011) to Revision L (July 2013)
Page
• Added TYP = –0.65 V to VIT+ .............................................................................................................................6
• Added TYP = –0.1 V to VIT– ...............................................................................................................................6
Changes from Revision J (February 2009) to Revision K (September 2011)
Page
• Added new section 'LOW-POWER STANDBY MODE', in the Application Information section........................18
2
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SLLS505P – FEBRUARY 2002 – REVISED FEBRUARY 2022
5 Device Comparison Table
PART NUMBER
SIGNALING RATE
UNIT LOADS
SN65HVD10P
32 Mbps
1/2
SN65HVD11P
10 Mbps
1/8
SN65HVD12P
1 Mbps
1/8
VP12
SN75HVD10P
32 Mbps
1/2
VN10
SOIC(1)
PDIP
SN65HVD10D
SN65HVD11D
SN65HVD12D
SN75HVD10D
SN75HVD11D
SN75HVD11P
10 Mbps
1/8
SN75HVD12D
SN75HVD12P
1 Mbps
1/8
SN65HVD10QD
SN65HVD10QP
32 Mbps
1/2
SN65HVD11QD
SN65HVD11QP
10 Mbps
1/8
(1)
TA
SOIC MARKING
VP10
–40°C to 85°C
–0°C to 70°C
VP11
VN11
VN12
–40°C to 125°C
VP10Q
VP11Q
The D package is available as a tape and reel. Add an R suffix to the part number (that is, SN75HVD11DR) for this option.
6 Pin Configuration and Functions
R
RE
DE
D
1
8
2
7
3
6
4
5
VCC
B
A
GND
Figure 6-1. D, JD, or HKJ Package
8-Pin SOIC or PDIP
(Top View)
Table 6-1. Pin Functions
PIN
NAME
NO.
TYPE
DESCRIPTION
A
6
Bus input/output
Driver output or receiver input (complementary to B)
B
7
Bus input/output
Driver output or receiver input (complementary to A)
D
4
Digital input
Driver data input
DE
3
Digital input
Active-high driver enable
GND
5
R
1
Digital output
RE
2
Digital input
VCC
8
Supply
Reference potential Local device ground
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Receive data output
Active-low receiver enable
3-V to 3.6-V supply
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SLLS505P – FEBRUARY 2002 – REVISED FEBRUARY 2022
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range unless otherwise noted (1) (2)
VCC
Supply voltage
Voltage at A or B
IO
UNIT
6
V
–9
14
V
–0.5
VCC + 0.5
V
Voltage input, transient pulse, A and B, through 100 Ω, see Figure 8-12
–50
50
V
Receiver output current
–11
11
mA
Continuous total power dissipation
Junction temperature
Tstg
Storage temperature
(2)
MAX
Input voltage at D, DE, R, or RE
TJ
(1)
MIN
–0.3
See Section 7.10
–55
170
°C
145
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 7.3 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
7.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
(1)
(2)
(3)
Electrostatic
discharge
Pins 5, 6, and 7
±16000
All pins
±4000
Charged device model (CDM), per JEDEC specification
JESD22-C101(2)
All pins
Electrical fast transient/burst(3)
Pins 5, 6, and 7
UNIT
V
±1000
±4000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Tested in accordance with IEC 61000-4-4.
7.3 Recommended Operating Conditions
over operating free-air temperature range unless otherwise noted
MIN
VCC
Supply voltage
VI or VIC
Voltage at any bus terminal (separately or common mode)
VIH
High-level input voltage
VIL
VID
12
2
VCC
Low-level input voltage
D, DE, RE
0
0.8
Differential input voltage
See Figure 8-8
–12
12
Driver
–60
IOL
Low-level output current
RL
Differential load resistance
CL
Differential load capacitance
Signaling rate
4
Receiver
UNIT
3.6
D, DE, RE
High-level output current
(1)
(2)
MAX
–7(1)
IOH
TJ (2)
NOM
3
V
mA
–8
Driver
60
Receiver
mA
8
54
60
Ω
50
pF
HVD10
32
HVD11
10
HVD12
1
Junction temperature
Mbps
145
°C
The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
See thermal characteristics table for information regarding this specification.
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SLLS505P – FEBRUARY 2002 – REVISED FEBRUARY 2022
7.4 Thermal Information
SNx5HVD1xx
THERMAL
METRIC(1)
D (SOIC) P (PDIP)
UNIT
8 Pins
8 Pins
Junction-to-ambient thermal resistance
116.7
84.3
°C/W
Junction-to-case (top) thermal resistance
56.3
65.4
°C/W
RθJB
Junction-to-board thermal resistance
63.4
62.1
°C/W
ψJT
Junction-to-top characterization parameter
8.8
31.3
°C/W
ψJB
Junction-to-board characterization parameter
62.6
60.4
°C/W
RθJA
Rθ
JC(top)
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Driver Electrical Characteristics
Over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
VIK
Input clamp voltage
II = –18 mA
|VOD|
Differential output voltage(2)
Δ|VOD|
Change in magnitude of differential output
voltage
VOC(PP)
Peak-to-peak common-mode output
voltage
VOC(SS)
Steady-state common-mode output voltage See Figure 8-3
ΔVOC(SS)
Change in steady-state common-mode
output voltage
IOZ
High-impedance output current
II
Input current
IOS
Short-circuit output current
–7 V ≤ VO ≤ 12 V
C(OD)
Differential output capacitance
VOD = 0.4 sin(4E6πt) + 0.5 V, DE at 0 V
(1)
(2)
Supply current
TYP(1)
MAX
–1.5
IO = 0
ICC
MIN
V
2
RL = 54 Ω, See Figure 8-1
1.5
Vtest = –7 V to 12 V, See Figure 8-2
1.5
See Figure 8-1 and Figure 8-2
UNIT
VCC
V
–0.2
0.2
400
V
mV
1.4
2.5
V
–0.05
0.05
V
See receiver input currents
D
DE
–100
0
0
100
–250
250
16
μA
mA
pF
RE at VCC,
D and DE at VCC,
No load
Receiver disabled and
driver enabled
9
15.5
mA
RE at VCC,
D at VCC,
DE at 0 V,
No load
Receiver disabled
and driver disabled
(standby)
1
5
μA
RE at 0 V,
D and DE at VCC,
No load
Receiver enabled and
driver enabled
9
15.5
mA
All typical values are at 25°C and with a 3.3-V supply.
For TA > 85°C, VCC is ±5%.
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SLLS505P – FEBRUARY 2002 – REVISED FEBRUARY 2022
7.6 Receiver Electrical Characteristics
Over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage IO = –8 mA
VIT–
Negative-going input threshold
voltage
MIN
IO = 8 mA
–0.2
–1.5
Vhys
Hysteresis voltage (VIT+ – VIT–)
VIK
Enable-input clamp voltage
II = –18 mA
VOH
High-level output voltage
VID = 200 mV, IOH = –8 mA, see Figure 8-8
VOL
Low-level output voltage
VID = –200 mV, IOL = 8 mA, see Figure 8-8
IOZ
High-impedance-state output current VO = 0 or VCC, RE at VCC
TYP(1)
MAX
–0.065
–0.01
VA or VB = –7 V
2.4
V
HVD11, HVD12,
Other inputs at 0 V
VA or VB = –7 V
HVD10,
Other inputs at 0 V
0.13
–0.04
0.2
0.5
0.25
0.5
–0.4
–0.2
–0.15
VA or VB = –7 V, VCC = 0 V
–0.4
VIH = 2 V
–30
IIL
Low-level input current, RE
VIL = 0.8 V
–30
CID
Differential input capacitance
VID = 0.4 sin(4E6πt) + 0.5 V, DE at 0 V
(1)
μA
0.06
–0.05
High-level input current, RE
Supply current
1
0.11
–0.05
IIH
ICC
V
0.05
–0.1
VA or VB = 12 V
VA or VB = 12 V, VCC = 0 V
0.4
–1
VA or VB = –7 V, VCC = 0 V
Bus input current
mV
V
VA or VB = 12 V
II
V
–0.1
35
VA or VB = 12 V, VCC = 0 V
UNIT
mA
mA
0
μA
0
μA
15
pF
RE at 0 V
D and DE at 0 V
No load
Receiver enabled and driver
disabled
4
8
mA
RE at VCC
D at VCC
DE at 0 V
No load
Receiver disabled and driver
disabled (standby)
1
5
μA
RE at 0 V
D and DE at VCC
No load
Receiver enabled and driver
enabled
9
15.5
mA
All typical values are at 25°C and with a 3.3-V supply.
7.7 Power Dissipation Characteristics
PARAMETER
PD
RL= 60 Ω, CL = 50 pF,
DE at VCC, RE at 0 V,
Input to D is a 50% duty-cycle
square wave at indicated signaling
rate
High-K board, no airflow
TA
Ambient air temperature(1)
TJSD
Thermal shutdown junction temperature(1)
(1)
(2)
6
Device power dissipation
TEST CONDITIONS
No
airflow(2)
MIN
TYP
MAX
HVD10
(32Mbps)
198
250
HVD11
(10Mbps)
141
176
HVD12
(500 kbps)
133
161
D pkg
–40
116
P pkg
–40
123
165
UNIT
mW
°C
°C
See Section 12.3.1 section for an explanation of these parameters.
JESD51−10, Test Boards for Through-Hole Perimeter Leaded Package Thermal Measurements.
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7.8 Driver Switching Characteristics
Over recommended operating conditions unless otherwise noted
MIN
TYP(1)
MAX
HVD10
5
8.5
16
HVD11
18
25
40
HVD12
135
200
300
HVD10
5
8.5
16
PARAMETER
Propagation delay time,
low-to-high-level output
tPLH
Propagation delay time,
high-to-low-level output
tPHL
TEST CONDITIONS
HVD11
18
25
40
HVD12
135
200
300
HVD10
Differential output signal
rise time
tr
Differential output signal
fall time
tf
tsk(p)
Pulse skew (|tPHL – tPLH|)
tsk(pp) (2)
tPZH
tPHZ
tPZL
Part-to-part skew
Propagation delay
time, high-impedance-tohigh-level output
Propagation delay
time, high-level-to-highimpedance output
Propagation delay
time, high-impedance-tolow-level output
3
4.5
10
10
20
30
HVD12
100
170
300
HVD10
3
4.5
10
HVD11
10
20
30
HVD12
100
170
300
HVD11
RL = 54 Ω, CL = 50 pF
See Figure 8-4
HVD10
1.5
HVD11
2.5
HVD12
7
HVD10
6
HVD11
11
HVD12
100
HVD10
31
HVD11
55
HVD12
300
HVD10
RL = 110 Ω, RE at 0 V
See Figure 8-5
ns
ns
ns
ns
ns
ns
ns
25
HVD11
55
HVD12
300
HVD10
26
HVD11
55
HVD12
300
HVD10
UNIT
RL = 110 Ω, RE at 0 V
See Figure 8-6
ns
ns
26
tPLZ
Propagation delay
time, low-level-to-highimpedance output
tPZH
Propagation delay time, standby-to-high- RL = 110 Ω, RE at 3 V
level output
See Figure 8-5
6
μs
tPZL
Propagation delay time, standby-to-lowlevel output
6
μs
(1)
(2)
HVD11
75
HVD12
400
RL = 110 Ω, RE at 3 V
See Figure 8-6
ns
All typical values are at 25°C and with a 3.3-V supply.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
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7.9 Receiver Switching Characteristics
Over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
tPLH
Propagation delay time,
low-to-high-level output
HVD10
12.5
20
25
tPHL
Propagation delay time,
high-to-low-level output
HVD10
12.5
20
25
tPLH
Propagation delay time,
low-to-high-level output
HVD11
HVD12
30
55
70
ns
tPHL
Propagation delay time,
high-to-low-level output
HVD11
HVD12
30
55
70
ns
tsk(p)
Pulse skew (|tPHL – tPLH|)
tsk(pp) (2)
Part-to-part skew
tr
Output signal rise time
tf
Output signal fall time
ns
VID = –1.5 V to 1.5 V
CL = 15 pF
See Figure 8-9
HVD10
1.5
HVD11
4
HVD12
4
HVD10
8
HVD11
15
HVD12
tPZH (1)
tPZL
(1)
CL = 15 pF
See Figure 8-9
1
2
5
1
2
5
Output enable time to high level
ns
15
Output enable time to low level
15
CL = 15 pF, DE at 3 V
See Figure 8-10
Output disable time from high level
tPLZ
Output disable time from low level
tPZH (2)
Propagation delay time, standby-to-highlevel output
CL = 15 pF, DE at 0
Propagation delay time, standby-to-low- See Figure 8-11
level output
(1)
(2)
ns
15
tPHZ
tPZL (2)
ns
20
ns
15
6
μs
6
All typical values are at 25°C and with a 3.3-V supply
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
7.10 Dissipation Ratings
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR(1)
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
TA = 125°C
POWER RATING
D(2)
597 mW
4.97 mW/°C
373 mW
298 mW
100 mW
(1)
(2)
(3)
8
D(3)
990 mW
8.26 mW/°C
620 mW
496 mW
165 mW
P
1290 mW
10.75 mW/°C
806 mW
645 mW
215 mW
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
Tested in accordance with the Low-K thermal metric definitions of EIA/JESD51-3.
Tested in accordance with the High-K thermal metric definitions of EIA/JESD51-7.
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7.11 Typical Characteristics
70
TA = 25°C
RE at VCC
DE at VCC
RL = 54 W
CL = 50 pF
VCC = 3.6 V
60
50
VCC = 3 V
VCC = 3.3 V
40
30
0
5
10
15
20
25
30
35
TA = 25°C
RE at VCC
DE at VCC
I CC − RMS Supply Current − mA
I CC − RMS Supply Current − mA
70
50
VCC = 3 V
VCC = 3.3 V
40
30
0
2.5
Signaling Rate − Mbps
TA = 25°C
RE at VCC
DE at VCC
5
7.5
Signaling Rate − Mbps
10
Figure 7-2. HVD11 RMS Supply Current vs Signaling Rate
300
RL = 54 W
CL = 50 pF
250
VCC = 3.6 V
I I − Bus Input Current − uA
I CC − RMS Supply Current − mA
70
VCC = 3.6 V
60
40
Figure 7-1. HVD10 RMS Supply Current vs Signaling Rate
RL = 54 W
CL = 50 pF
60
VCC = 3.3 V
50
VCC = 3 V
40
TA = 25°C
DE at 0 V
200
VCC = 0 V
150
100
50
VCC = 3.3 V
0
−50
−100
−150
30
100
400
700
Signaling Rate − kbps
−200
−7 −6−5 −4−3 −2−1 0 1 2 3 4 5 6 7 8 9 10 11 12
VI − Bus Input Voltage − V
1000
Figure 7-3. HVD12 RMS Supply Current vs Signaling Rate
Figure 7-4. HVD10 Bus Input Current vs Bus Input Voltage
90
I I − Bus Input Current − uA
70
150
TA = 25°C
DE at 0 V
60
50
40
VCC = 0 V
30
20
10
0
VCC = 3.3 V
−10
−20
−30
−40
IOH − High-Level Output Current − mA
80
TA = 25°C
DE at VCC
D at VCC
VCC = 3.3 V
100
50
0
−50
−100
−150
−50
−60
−7−6 −5 −4 −3 −2 −1 0 1 2 3 4 5 6 7 8 9 10 11 12
VI − Bus Input Voltage − V
Figure 7-5. HVD11 or HVD12 Bus Input Current vs Bus Input
Voltage
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−200
−4
−2
0
2
4
VOH − Driver High-Level Output Voltage − V
6
Figure 7-6. High-Level Output Current vs Driver High-Level
Output Voltage
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9
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SLLS505P – FEBRUARY 2002 – REVISED FEBRUARY 2022
7.11 Typical Characteristics (continued)
2.5
200
TA = 25°C
DE at VCC
D at 0 V
VCC = 3.3 V
160
140
2.4
VOD − Driver Differential Output − V
I OL − Low-Level Output Current − mA
180
120
100
80
60
40
20
−20
−4
−2
0
2
4
6
VOL − Driver Low-Level Output Voltage − V
2.1
2.0
1.9
1.8
1.7
1.5
−40
8
Figure 7-7. Low-Level Output Current vs Driver Low-Level
Output Voltage
−15
10
35
60
TA − Free-Air Temperature − °C
85
Figure 7-8. Driver Differential Output vs Free-Air Temperature
600
−40
TA = 25°C
DE at VCC
D at VCC
RL = 54 Ω
−35
−30
500
HVD12
Enable Time − ns
I O − Driver Output Current − mA
2.2
1.6
0
−25
−20
−15
400
HVD11
300
HVD10
200
−10
100
−5
0
0
0
0.50
1
1.50
2
2.50
3
3.50
VCC − Supply Voltage − V
Figure 7-9. Driver Output Current vs Supply Voltage
10
2.3
VCC = 3.3 V
DE at VCC
D at VCC
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-7
-2
3
8
13
V(TEST) − Common-Mode Voltage − V
Figure 7-10. Enable Time vs Common-Mode Voltage
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SLLS505P – FEBRUARY 2002 – REVISED FEBRUARY 2022
8 Parameter Measurement Information
VCC
DE
II
IOA
A
VOD
0 or 3 V
B
54 Ω±1%
IOB
VI
VOB
VOA
Copyright © 2017, Texas Instruments Incorporated
Figure 8-1. Driver VOD Test Circuit and Voltage and Current Definitions
375 Ω ±1%
VCC
DE
D
A
VOD
0 or 3 V
60 Ω ±1%
+
_ −7 V < V(test) < 12 V
B
375 Ω ±1%
Copyright © 2017, Texas Instruments Incorporated
Figure 8-2. Driver VOD With Common-Mode Loading Test Circuit
VCC
DE
Input
D
27 Ω ± 1%
A
A
VA
B
VB
VOC(PP)
27 Ω ± 1%
B
CL = 50 pF ±20%
VOC
DVOC(SS)
VOC
CL Includes Fixture and
Instrumentation Capacitance
Copyright © 2017, Texas Instruments Incorporated
Input: PRR = 500 kHz, 50% Duty Cycle, tr < 60 ns, tf < 6 ns ZO = 50 Ω
Figure 8-3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
3V
VCC
DE
D
Input
Generator
VI
50 Ω
CL = 50 pF ±20%
A
B
VOD
RL = 54 Ω
± 1%
CL Includes Fixture
and Instrumentation
Capacitance
1.5 V
VI
t PLH
1.5 V
t PHL
90%
VOD
90%
0V
10%
tr
tf
≈2 V
0V
10%
≈ –2 V
Copyright © 2017, Texas Instruments Incorporated
Generator: PRR = 500 kHz, 50% Duty Cycle, tr < 60 ns, tf < 6 ns ZO = 50 Ω
Figure 8-4. Driver Switching Test Circuit and Voltage Waveforms
Copyright © 2022 Texas Instruments Incorporated
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SLLS505P – FEBRUARY 2002 – REVISED FEBRUARY 2022
A
3V
D
3V
S1
VO
VI
1.5 V
1.5 V
B
DE
Input
Generator
VI
50 Ω
0V
0.5 V
RL = 110 Ω
± 1%
CL = 50 pF ±20%
t PZH
VOH
CL Includes Fixture
and Instrumentation
Capacitance
VO
2.3 V
≈0V
t PHZ
Copyright © 2017, Texas Instruments Incorporated
Generator: PRR = 500 kHz, 50% Duty Cycle, tr < 60 ns, tf < 6 ns ZO = 50 Ω
Figure 8-5. Driver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms
3V
A
3V
D
VI
≈3 V
1.5 V
VI
S1
1.5 V
VO
0V
B
DE
Input
Generator
RL = 110 Ω
± 1%
t PZL
t PLZ
≈3 V
CL = 50 pF ±20%
50 Ω
0.5 V
CL Includes Fixture
and Instrumentation
Capacitance
VO
2.3 V
VOL
Copyright © 2017, Texas Instruments Incorporated
Generator: PRR = 500 kHz, 50% Duty Cycle, tr < 60 ns, tf < 6 ns ZO = 50 Ω
Figure 8-6. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
375 Ω ± 1%
Y
-7 V < V(TEST) < 12 V
D
0 or 3 V
VOD
60 W
± 1%
Z
DE
375 Ω ± 1%
Input
Generator
V
50 Ω
50%
tpZH(diff)
VOD (high)
1.5 V
0V
tpZL(diff)
-1.5 V
VOD (low)
Copyright © 2017, Texas Instruments Incorporated
The time tPZL(x) is the measure from DE to VOD(x). VOD is valid when it is greater than 1.5 V.
Figure 8-7. Driver Enable Time from DE to VOD
12
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SLLS505P – FEBRUARY 2002 – REVISED FEBRUARY 2022
IA
VA + VB
VID
VB
VIC
A
R
VA
IO
B
VO
IB
2
Copyright © 2017, Texas Instruments Incorporated
Figure 8-8. Receiver Voltage and Current Definitions
A
Input
Generator
R
VI
50 Ω
B
1.5 V
CL = 15 pF ±20%
RE
0V
VO
CL Includes Fixture
and Instrumentation
Capacitance
Generator: PRR = 500 kHz, 50% Duty Cycle, tr
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