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SN65HVD11-HT
SLLS934F – NOVEMBER 2008 – REVISED NOVEMBER 2015
SN65HVD11-HT 3.3-V RS-485 Transceiver
1 Features
2 Applications
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Operates With a 3.3-V Supply
Bus-Pin ESD Protection Exceeds 16-kV HumanBody Model (HBM)
1/8 Unit-Load Option Available (up to 256 Nodes
on Bus)
Optional Driver Output Transition Times for
Signaling Rates (1) of 1 Mbps, 10 Mbps, and
32 Mbps
Based on ANSI TIA/EIA-485-A
Bus-Pin Short Circuit Protection From
–7 V to 12 V
Open-Circuit, Idle-Bus, and Shorted-Bus Fail-Safe
Receiver
Glitch-Free Power-Up and Power-Down Protection
for Hot-Plugging Applications
SN75176 Footprint
Supports Extreme Temperature Applications:
– Controlled Baselines
– One Assembly and Test Sites
– One Fabrication Sites
– Available in Extreme (–55°C/210°C)
Temperature Range (2)
– Extended Product Life Cycles
– Extended Product-Change Notifications
– Product Traceability
– Texas Instruments' High Temperature
Products Use Highly Optimized Silicon (Die)
Solutions With Design and Process
Enhancements to Maximize Performance Over
Extended Temperatures.
Down-Hole Drilling
High Temperature Environments
Digital Motor Controls
Utility Meters
Chassis-to-Chassis Interconnects
Electronic Security Stations
Industrial Process Controls
Building Automation
Point-of-Sale (POS) Terminals and Networks
3 Description
The SN65HVD11-HT device combines a 3-state
differential line driver and differential input line
receiver that operates with a single 3.3-V power
supply. It is designed for balanced transmission lines
and meets or exceeds ANSI TIA/EIA-485-A and ISO
8482:1993, with the exception that the thermal
shutdown is removed. This differential bus transceiver
is a monolithic integrated circuit designed for
bidirectional data communication on multipoint bustransmission lines. The driver and receiver have
active-high and active-low enables, respectively, that
can be externally connected together to function as
direction control.
The driver differential outputs and receiver differential
inputs connect internally to form a differential input/
output (I/O) bus port that is designed to offer
minimum loading to the bus when the driver is
disabled or VCC = 0.
Device Information(1)
PART NUMBER
SN65HVD11-HT
PACKAGE
4.90 mm × 3.91 mm
CFP (8) (2)
6.90 mm × 5.65 mm
(3)
6.90 mm × 5.65 mm
CFP (8)
CDIP SB (8)
(1)
(2)
BODY SIZE (NOM)
SOIC (8)
11.81 mm × 7.49 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) HKJ Package
(3) HKQ Package
The signaling rate of a line is the number of voltage
transitions that are made per second expressed in the units
bits per second (bps).
Custom temperature ranges available
Typical Application Diagram
R
R
B
DE
D
R
A
RE
R
A
RT
RT
D
A
R
B
A
D
R RE DE D
R
RE
B
DE
D
B
D
D
R RE DE D
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN65HVD11-HT
SLLS934F – NOVEMBER 2008 – REVISED NOVEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
7
8
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Driver Electrical Characteristics ................................ 6
Receiver Electrical Characteristics ........................... 7
Driver Switching Characteristics ............................... 8
Receiver Switching Characteristics........................... 9
Typical Characteristics ............................................ 12
Parameter Measurement Information ................ 14
Detailed Description ............................................ 19
8.1 Overview ................................................................. 19
8.2 Functional Block Diagram ....................................... 19
8.3 Feature Description................................................. 19
8.4 Device Functional Modes........................................ 19
9
Application and Implementation ........................ 21
9.1 Application Information............................................ 21
9.2 Typical Application .................................................. 22
10 Power Supply Recommendations ..................... 25
11 Layout................................................................... 25
11.1 Layout Guidelines ................................................. 25
11.2 Layout Example .................................................... 25
11.3 Thermal Considerations ........................................ 26
12 Device and Documentation Support ................. 27
12.1
12.2
12.3
12.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
27
27
27
27
13 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (June 2012) to Revision F
•
2
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
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SLLS934F – NOVEMBER 2008 – REVISED NOVEMBER 2015
5 Pin Configuration and Functions
D, JD, or HKJ Package
8-Pin SOIC, PDIP, or CFP
Top View
R
RE
DE
D
1
8
2
7
3
6
4
5
HKQ Package
8-Pin CFP
Top View
VCC
B
A
GND
1
8
VCC
R
B
RE
A
DE
D
GND
5
4
Pin Functions
PIN
TYPE
DESCRIPTION
SOIC,
PDIP
HKQ
A
6
6
Bus input/output
Driver output or receiver input (complementary to B)
B
7
7
Bus input/output
Driver output or receiver input (complementary to A)
D
4
4
Digital input
Driver data input
DE
3
3
Digital input
Active-high driver enable
GND
5
5
Reference
potential
Local device ground
R
1
1
Digital output
Receive data output
RE
2
2
Digital input
VCC
8
8
Supply
NAME
Active-low receiver enable
3-V to 3.6-V supply
Bare Die Information
DIE THICKNESS
BACKSIDE FINISH
BACKSIDE
POTENTIAL
BOND PAD
METALLIZATION COMPOSITION
15 mils.
Silicon with backgrind
GND
Cu-Ni-Pd
Bond Pad Coordinates in Microns - Rev A
DESCRIPTION
(1)
(1)
PAD NUMBER
a
b
c
d
R
1
69.3
372.15
185.3
489.15
~RE
2
388.75
71.5
503.75
186.5
DNC
3
722.4
55.4
839.4
172.4
DNC
4
891.4
55.4
1008.4
172.4
DE
5
1174.8
71.5
1289.8
186.5
DNC
6
1754.35
65.4
1869.35
180.4
DNC
7
1907.35
65.4
2022.35
180.4
D
8
2280.55
69.5
2395.55
184.5
DNC
9
2733.5
371.5
2848.5
486.5
GND
10
2691
1693.1
2808
1810.1
GND
11
2535
1693.1
2652
1810.1
DNC
12
2253.45
1685.65
2368.45
1800.65
A
13
1961.55
1693.1
2078.55
1810.1
B
14
799.55
1693.1
916.55
1810.1
DNC
15
498.35
1681.2
613.35
1796.2
VCC
16
244.8
1668.5
359.8
1783.5
DNC = Do Not Connect
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Bond Pad Coordinates in Microns - Rev A (continued)
DESCRIPTION
(1)
PAD NUMBER
a
b
c
d
17
91.8
1668.5
206.8
1783.5
VCC
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
UNIT
–0.3
6
V
–9
14
V
Input voltage at D, DE, R, or RE
–0.5
VCC + 0.5
V
Voltage input, transient pulse, A and B, through 100 Ω (see
Figure 20)
–50
50
V
Receiver output current
–11
11
mA
Continuous total power dissipation
See Thermal Information
Supply voltage
Voltage at A or B
IO
(1)
4
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
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SLLS934F – NOVEMBER 2008 – REVISED NOVEMBER 2015
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
A, B, and GND
±16000
All pins
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
VCC
Supply voltage
VI or VIC
Voltage at any bus terminal (separately or common-mode)
VIH
High-level input voltage
VIL
Low-level input voltage
VID
Differential input voltage
IOH
High-level output current
IOL
Low-level output current
RL
Differential load resistance
CL
Differential load capacitance
NOM
MAX
3.6
V
–7 (1)
12
V
D, DE, RE
2
VCC
V
D, DE, RE
0
0.8
V
Figure 16
–12
12
V
Driver
–60
Receiver
mA
–8
Driver
60
Receiver
54
60
Ω
50
pF
(1)
(2)
10
Operating junction temperature
mA
8
Signaling rate
TJ (2)
UNIT
3
TA = –55°C to 125°C
129
TA = 175°C
179
TA = 210°C
214
Mbps
°C
The algebraic convention, in which the least-positive (most-negative) limit is designated as minimum, is used in this data sheet.
See Thermal Information table for information regarding this specification.
6.4 Thermal Information
SN65HVD11-HT
THERMAL METRIC (1)
RθJA
JD (CDIP SB)
HKJ (CFP)
HKQ (CFP)
8 PINS
8 PINS
8 PINS
8 PINS
UNIT
101.5
73.9
N/A
170
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
53.6
N/A
N/A
6.2
°C/W
RθJB
Junction-to-board thermal resistance
45.1
39.8
N/A
195
°C/W
ψJT
Junction-to-top characterization parameter
4.8
6.9
N/A
3.8
°C/W
ψJB
Junction-to-board characterization parameter
41.8
49.2
N/A
146.8
°C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance
N/A
9.1
6.2
N/A
°C/W
(1)
Junction-to-ambient thermal resistance
D (SOIC)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Driver Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
VIK
TEST CONDITIONS
Input clamp voltage
|VOD|
Differential output
voltage
MIN
II = –18 mA
TYP
MAX
–1.5
IO = 0
2
RL = 54 Ω, See Figure 10
1
Vtest = –7 V to 12 V,
See Figure 11
1
UNIT
V
VCC
V
Δ|VOD|
Change in magnitude
of differential output
voltage
Vtest = –7 V to 12 V,
See Figure 10 and Figure 11
VOC(PP)
Peak-to-peak common
mode output voltage
See Figure 12
VOC(SS)
Steady-state common
mode output voltage
See Figure 12
1.4
2.5
V
ΔVOC(SS)
Change in steady-state
common mode output
voltage
See Figure 12
–0.06
0.06
V
IOZ
High-impedance output
current
See receiver input currents
–0.2
400
TA = –55°C to 125°C
D
–100
0
–100
3
TA = 210°C (2)
–100
3
0
100
–250
250
TA = 175°C
Input
current
IOS
Short circuit output
current
–7 V ≤ VO ≤ 12 V
C(OD)
Differential output
capacitance
VOD = 0.4 sin (4E6πt) + 0.5 V,
DE = 0 V
DE
ICC
Supply current
RE = VCC,
D = VCC,
DE = 0 V,
No load
RE = 0 V,
D and
DE = VCC,
No load
(1)
(2)
6
Receiver disabled
and driver enabled
Receiver disabled
and driver disabled
(standby)
18
11
15.5
TA = 175°C
(1)
11.5
17.5
TA = 210°C
(2)
14
18
TA = –55°C to
125°C
2.5
20
TA = 175°C
(1)
20
150
TA = 210°C
(2)
175
450
TA = –55°C to
125°C
11
15.5
11
17.5
11
18
TA = 210°C
(2)
μA
mA
pF
TA = –55°C to
125°C
Receiver enabled and
driver enabled
TA = 175°C (1)
V
mV
(1)
II
RE = VCC,
D and
DE = VCC,
No load
0.2
mA
μA
mA
Minimum and maximum parameters are characterized for operation at TA = 175°C but may not be production tested at that temperature.
Production test limits with statistical guardbands are used to ensure high temperature performance.
Minimum and maximum parameters are characterized for operation at TA = 210°C but may not be production tested at that temperature.
Production test limits with statistical guardbands are used to ensure high temperature performance.
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6.6 Receiver Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input
threshold voltage
IO = –8 mA
VIT–
Negative-going
input threshold
voltage
IO = 8 mA
Vhys
Hysteresis voltage
(VIT+ –VIT–)
MIN
35
TA = 175°C (1)
41
TA = 210°C (2)
41
II = –18 mA
VOH
High-level output
voltage
VID = 200 mV, IOH = –8 mA,
See Figure 16
VOL
Low-level output
voltage
VID = –200 mV, IOL = 8 mA,
See Figure 16
IOZ
High-impedance
state output current
VO = 0 or VCC,RE = VCC
V
Other input
at 0 V
VA or VB = –7 V
VA or VB = –7 V,
VCC = 0 V
VIH = 2 V
IIL
Low-level input
current, RE
VIL = 0.8 V
CID
Differential input
capacitance
VID = 0.4 sin (4E6πt) + 0.5 V,
DE at 0 V
(1)
(2)
Supply current
RE = 0 V,
D and DE = 0 V,
No load
Receiver
enabled and
driver disabled
RE = VCC,
D = VCC,
DE = 0 V,
No load
Receiver
disabled and
driver disabled
(standby)
RE = 0 V,
D and DE = VCC,
No load
Receiver
enabled and
driver enabled
0.4
V
1
μA
0.075
0.11
(1)
0.1
0.15
TA = 210°C (2)
0.1
0.15
0.085
0.13
TA = 175°C (1)
0.12
0.16
TA = 210°C (2)
0.12
0.16
TA = 175°C
VA or VB = 12 V,
VCC = 0 V
mV
2.4
TA = –55°C to 125°C
ICC
V
V
–1
VA or VB = 12 V
High-level input
current, RE
–0.01
–1.5
TA = –55°C to 125°C
IIH
UNIT
V
TA = –55°C to 125°C
Enable-input clamp
voltage
Bus input current
MAX
–0.2
VIK
II
TYP
TA = –55°C to 125°C
–0.1
–0.05
TA = 175°C (1)
–0.3
–0.15
TA = 210°C (2)
–0.3
–0.15
TA = –55°C to 125°C
–0.1
–0.05
TA = 175°C (1)
–0.3
–0.15
TA = 210°C (2)
–0.3
–0.15
TA = –55°C to 125°C
–30
0
TA = 175°C (1)
–30
3
TA = 210°C (2)
–30
3
–30
0
TA = –55°C to 125°C
15
TA = 175°C (1)
18
TA = 210°C (2)
18
TA = –55°C to 125°C
5
8
7.5
8.5
(2)
7.5
10
TA = –55°C to 125°C
2.5
20
TA = 175°C (1)
12.5
200
TA = 210°C (2)
175
450
TA = –55°C to 125°C
μA
μA
pF
TA = 175°C (1)
TA = 210°C
mA
11
15.5
TA = 175°C (1)
11.5
17.5
TA = 210°C (2)
14
18
mA
μA
mA
Minimum and maximum parameters are characterized for operation at TA = 175°C but may not be production tested at that temperature.
Production test limits with statistical guardbands are used to ensure high temperature performance.
Minimum and maximum parameters are characterized for operation at TA = 210°C but may not be production tested at that temperature.
Production test limits with statistical guardbands are used to ensure high temperature performance.
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6.7 Driver Switching Characteristics
over recommended operating conditions (unless otherwise noted)
MIN
TYP
MAX
tPLH
Propagation delay time, lowto-high-level output
PARAMETER
TEST CONDITIONS
18
25
40
ns
tPHL
Propagation delay time, highto-low-level output
18
25
40
ns
TA = –55°C to 125°C
10
21
30
tr
Differential output signal rise
time
TA = 175°C (1)
10
22
30
TA = 210°C (2)
10
22
30
TA = –55°C to 125°C
10
21
30
TA = 175°C (1)
10
22
30
TA = 210°C (2)
10
22
30
RL = 54 Ω,
CL = 50 pF,
See Figure 13
Differential output signal fall
time
tf
UNIT
ns
ns
tsk(p)
Pulse skew (|tPHL – tPLH|)
2.5
ns
tsk(pp) (3)
Part-to-part skew (tPHL or tPLH)
11
ns
tPZH
Propagation delay time, highimpedance to high-level
output
55
ns
tPHZ
Propagation delay time, highlevel to high-impedance
output
55
ns
tPZL
Propagation delay time, highimpedance to low-level output
55
ns
tPLZ
Propagation delay time, lowlevel to high-impedance
output
75
ns
tPZH
Propagation delay time,
standby to high-level output
RL = 110 Ω,
RE = 3 V,
See Figure 14
6
μs
tPZL
Propagation delay time,
standby to low-level output
RL = 110 Ω,
RE = 3 V,
See Figure 15
6
μs
(1)
(2)
(3)
8
RL = 110 Ω,
RE = 0 V,
See Figure 14
RL = 110 Ω,
RE = 0 V,
See Figure 15
Minimum and maximum parameters are characterized for operation at TA = 175°C but may not be production tested at that temperature.
Production test limits with statistical guardbands are used to ensure high temperature performance.
Minimum and maximum parameters are characterized for operation at TA = 210°C but may not be production tested at that temperature.
Production test limits with statistical guardbands are used to ensure high temperature performance.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
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6.8 Receiver Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
tPLH
Propagation delay time, low-to-highlevel output
tPHL
Propagation delay time, high-to-lowlevel output
tsk(p)
Pulse skew (|tPHL – tPLH|)
tsk(pp) (1)
Part-to-part skew
tr
TEST CONDITIONS
VID = –1.5 V to 1.5 V,
CL = 15 pF,
See Figure 17
Output signal rise time
CL = 15 pF,
See Figure 17
tf
tPZH
Output signal fall time
(3)
Output enable time to low level
tPHZ
Output disable time from high level
tPLZ
Output disable time from low level
tPZH
(1)
tPZL (1)
(1)
(2)
(3)
Propagation delay time, standby-tohigh-level output
Propagation delay time, standby-tolow-level output
TYP
MAX
30
55
70
ns
30
55
70
ns
4
ns
15
ns
TA = –55°C to
125°C
1
3
5
TA = 175°C (2)
1
4
5
TA = 210°C (3)
1
4
5
TA = –55°C to
125°C
1
3
5
TA = 175°C (2)
1
4
5
TA = 210°C (3)
1
4
5
Output enable time to high level
tPZL (3)
MIN
CL = 15 pF, DE = 3 V,
See Figure 18
CL = 15 pF, DE = 0,
See Figure 19
UNIT
ns
ns
15
ns
15
ns
20
ns
15
ns
6
μs
6
μs
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
Minimum and maximum parameters are characterized for operation at TA = 175°C but may not be production tested at that temperature.
Production test limits with statistical guardbands are used to ensure high temperature performance.
Minimum and maximum parameters are characterized for operation at TA = 210°C but may not be production tested at that temperature.
Production test limits with statistical guardbands are used to ensure high temperature performance.
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xxx
Estimated Life (Hours)
1000000
100000
Electromigration Fail Mode
10000
1000
110
Wirebond Fail Mode
120
130
140
150
160
170
180
190
200
210
Continuous TJ (°C)
(1)
See data sheet for absolute maximum and minimum recommended operating conditions.
(2)
Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect
life).
(3)
The predicted operating lifetime vs. junction temperature is based on reliability modeling using electromigration as the
dominant failure mechanism affecting device wearout for the specific device process and design characteristics.
(4)
Wirebond fail mode applicable for D package only.
(5)
Wirebond life approaches 0 hours < 200°C which is only true of the HD device.
Figure 1. SN65HVD11SJD/SKGDA/SHKJ/SHKQ/HD
Operating Life Derating Chart
10
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SLLS934F – NOVEMBER 2008 – REVISED NOVEMBER 2015
375 W ± 1%
Y
D
0 or 3 V
-7 V < V(TEST) < 12 V
VOD
60 W
± 1%
Z
DE
375 W ± 1%
Input
Generator
V
50 W
50%
tpZH(diff)
VOD (high)
1.5 V
0V
tpZL(diff)
-1.5 V
VOD (low)
Note:
The time tpZL(x) is the measure from DE to VOD(x). VOD is valid when it is greater than 1.5 V.
Figure 2. Driver Enable Time From De to VOD
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6.9 Typical Characteristics
70
90
RL = 54 W
CL = 50 pF
70
60
50
VCC = 3 V
VCC = 3.3 V
40
TA = 25°C
DE at 0 V
80
VCC = 3.6 V
I I − Bus Input Current − mA
I CC − RMS Supply Current − mA
TA = 25°C
RE at VCC
DE at VCC
60
50
VCC = 0 V
40
30
20
10
0
VCC = 3.3 V
−10
−20
−30
−40
−50
30
0
2.5
5
7.5
Signaling Rate − Mbps
−60
−7−6 −5 −4 −3 −2 −1 0 1 2 3 4 5 6 7 8 9 10 11 12
VI − Bus Input Voltage − V
10
Figure 3. RMS Supply Current vs Signaling Rate
Figure 4. Bus Input Current vs Bus Input Voltage
200
TA = 25°C
DE at VCC
D at VCC
VCC = 3.3 V
100
TA = 25°C
DE at VCC
D at 0 V
VCC = 3.3 V
180
I OL − Low-Level Output Current − mA
IOH − High-Level Output Current − mA
150
50
0
−50
−100
−150
160
140
120
100
80
60
40
20
0
−200
−4
−2
0
2
4
VOH − Driver High-Level Output Voltage − V
−20
−4
6
Figure 5. High-Level Output Current vs Driver High-Level
Output Voltage
−40
VCC = 3.3 V
VTest = 12 V
2.2
2.1
2.0
1.9
1.8
1.7
1.6
1.5
-100
TA = 25°C
DE at VCC
D at VCC
RL = 54 W
−35
I O − Driver Output Current − mA
VOD – Driver Differential Output – V
2.3
−30
−25
−20
−15
−10
−5
0
-50
0
50
100
150
200
250
0
0.50
1
1.50
2
2.50
3
3.50
VCC − Supply Voltage − V
TA – Free-Air Temperature – °C
Figure 7. Driver Differential Output vs Free-Air Temperature
12
8
Figure 6. Low-Level Output Current vs Driver Low-Level
Output Voltage
2.5
2.4
−2
0
2
4
6
VOL − Driver Low-Level Output Voltage − V
Figure 8. Driver Output Current vs Supply Voltage
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SLLS934F – NOVEMBER 2008 – REVISED NOVEMBER 2015
Typical Characteristics (continued)
600
Enable Time − ns
500
400
300
200
100
0
-7
-2
3
8
13
V(TEST) − Common-Mode Voltage − V
Figure 9. Enable Time vs Common Mode Voltage (See Figure 2)
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7 Parameter Measurement Information
VCC
II
DE
A
IOA
VOD
0 or 3 V
B
54 Ω ±1%
IOB
VI
VOB
VOA
Figure 10. Driver VOD Test Circuit and Voltage and Current Definitions
375 Ω ±1%
VCC
DE
0 or 3 V
D
A
VOD
60 Ω ±1%
B
+
_ −7 V < V(test) < 12 V
375 Ω ±1%
Figure 11. Driver VOD With Common Mode Loading Test Circuit
VCC
DE
Input
D
27 Ω ± 1%
A
A
VA
B
VB
VOC(PP)
27 Ω ± 1%
B
CL = 50 pF ±20%
VOC
∆VOC(SS)
VOC
A. Input: PRR = 500 kHz, 50% Duty Cycle, t r
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