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SN65HVD10, SN65HVD11, SN65HVD12
SN75HVD10, SN75HVD11, SN75HVD12
SLLS505O – FEBRUARY 2002 – REVISED FEBRUARY 2017
SNx5HVD1x 3.3-V RS-485 Transceivers
1 Features
3 Description
•
•
•
The SN65HVD10, SN75HVD10, SN65HVD11,
SN75HVD11, SN65HVD12, and SN75HVD12 bus
transceivers combine a 3-state differential line driver
and differential input line receiver that operate with a
single 3.3-V power supply. They are designed for
balanced transmission lines and meet or exceed
ANSI standard TIA/EIA-485-A and ISO 8482:1993.
These differential bus transceivers are monolithic
integrated circuits designed for bidirectional data
communication on multipoint bus-transmission lines.
The drivers and receivers have active-high and
active-low enables, respectively, that can be
externally connected together to function as direction
control. Very low device standby supply current can
be achieved by disabling the driver and the receiver.
1
•
•
•
•
•
•
•
•
Operates With a 3.3-V Supply
Bus-Pin ESD Protection Exceeds 16-kV HBM
1/8 Unit-Load Option Available (Up to 256 Nodes
on the Bus)
Optional Driver Output Transition Times for
Signaling Rates (1) of 1 Mbps, 10 Mbps, and
32 Mbps
Meets or Exceeds the Requirements of ANSI
TIA/EIA-485-A
Bus-Pin Short-Circuit Protection From –7 V to
12 V
Low-Current Standby Mode: 1 µA, Typical
Open-Circuit, Idle-Bus, and Shorted-Bus Failsafe
Receiver
Thermal Shutdown Protection
Glitch-Free Power-Up and Power-Down Protection
for Hot-Plugging Applications
SN75176 Footprint
The driver differential outputs and receiver differential
inputs connect internally to form a differential input/
output (I/O) bus port that is designed to offer
minimum loading to the bus whenever the driver is
disabled or VCC = 0. These parts feature wide positive
and negative common-mode voltage ranges making
them suitable for party-line applications.
2 Applications
•
•
•
•
•
•
•
(1)
Device Information(1)
Digital Motor Control
Utility Meters
Chassis-to-Chassis Interconnects
Electronic Security Stations
Industrial Process Control
Building Automation
Point-of-Sale (POS) Terminals and Networks
The signaling rate of a line is the number of voltage
transitions that are made per second expressed in the units
bps (bits per second).
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN65HVD10
SN65HVD11
SOIC (8)
4.90 mm × 3.91 mm
PDIP (8)
9.81 mm × 6.35 mm
SN65HVD12
SN75HVD10
SN75HVD11
SN75HVD12
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Diagram
R
R
B
DE
D
R
A
RE
R
A
RT
RT
D
A
R
B
A
D
R RE DE D
R
RE
B
DE
D
B
D
D
R RE DE D
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN65HVD10, SN65HVD11, SN65HVD12
SN75HVD10, SN75HVD11, SN75HVD12
SLLS505O – FEBRUARY 2002 – REVISED FEBRUARY 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
4
4
4
5
5
6
6
7
8
8
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Driver Electrical Characteristics ................................
Receiver Electrical Characteristics ...........................
Power Dissipation Characteristics ............................
Driver Switching Characteristics ...............................
Receiver Switching Characteristics...........................
Dissipation Ratings .................................................
Typical Characteristics ............................................
Parameter Measurement Information ................ 11
Detailed Description ............................................ 17
9.1 Overview ................................................................. 17
9.2 Functional Block Diagram ....................................... 17
9.3 Feature Description................................................. 17
9.4 Device Functional Modes........................................ 17
10 Application and Implementation........................ 19
10.1 Application Information.......................................... 19
10.2 Typical Application ................................................ 20
11 Power Supply Recommendations ..................... 23
12 Layout................................................................... 23
12.1 Layout Guidelines ................................................. 23
12.2 Layout Example .................................................... 24
12.3 Thermal Considerations ........................................ 24
13 Device and Documentation Support ................. 26
13.1
13.2
13.3
13.4
13.5
13.6
13.7
Device Support......................................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
26
26
26
26
26
14 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
Changes from Revision N (July 2015) to Revision O
•
Page
Added MIN value of –55°C to the Storage temperature in Absolute Maximum Ratings........................................................ 4
Changes from Revision M (July 2013) to Revision N
•
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Changes from Revision L (July 2013) to Revision M
•
Page
Changed the VIT+ TYP value From: –0.65 V To: –0.065 V ................................................................................................... 6
Changes from Revision K (September 2011) to Revision L
Page
•
Added TYP = –0.65 V to VIT+ ................................................................................................................................................ 6
•
Added TYP = –0.1 V to VIT– ................................................................................................................................................... 6
Changes from Revision J (February 2009) to Revision K
•
2
Page
Added new section 'LOW-POWER STANDBY MODE', in the Application Information section........................................... 18
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SN75HVD10, SN75HVD11, SN75HVD12
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SLLS505O – FEBRUARY 2002 – REVISED FEBRUARY 2017
5 Device Comparison Table
PART NUMBER
SIGNALING RATE
UNIT LOADS
SN65HVD10P
32 Mbps
1/2
SN65HVD11D
SN65HVD11P
10 Mbps
1/8
SN65HVD12D
SN65HVD12P
1 Mbps
1/8
VP12
SN75HVD10D
SN75HVD10P
32 Mbps
1/2
VN10
SN75HVD11D
SN75HVD11P
10 Mbps
1/8
SOIC (1)
PDIP
SN65HVD10D
TA
SOIC MARKING
VP10
–40°C to 85°C
–0°C to 70°C
VP11
VN11
SN75HVD12D
SN75HVD12P
1 Mbps
1/8
VN12
SN65HVD10QD
SN65HVD10QP
32 Mbps
1/2
VP10Q
SN65HVD11QD
SN65HVD11QP
10 Mbps
1/8
(1)
–40°C to 125°C
VP11Q
The D package is available as a tape and reel. Add an R suffix to the part number (that is, SN75HVD11DR) for this option.
6 Pin Configuration and Functions
D, JD, or HKJ Package
8-Pin SOIC or PDIP
Top View
R
RE
DE
D
1
8
2
7
3
6
4
5
VCC
B
A
GND
Pin Functions
PIN
NAME
NO.
TYPE
DESCRIPTION
A
6
Bus input/output
Driver output or receiver input (complementary to B)
B
7
Bus input/output
Driver output or receiver input (complementary to A)
D
4
Digital input
Driver data input
DE
3
Digital input
Active-high driver enable
GND
5
Reference potential
Local device ground
R
1
Digital output
Receive data output
RE
2
Digital input
VCC
8
Supply
Copyright © 2002–2017, Texas Instruments Incorporated
Active-low receiver enable
3-V to 3.6-V supply
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SN75HVD10, SN75HVD11, SN75HVD12
SLLS505O – FEBRUARY 2002 – REVISED FEBRUARY 2017
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range unless otherwise noted
VCC
(1) (2)
Supply voltage
Voltage at A or B
IO
MAX
UNIT
6
V
–9
14
V
Input voltage at D, DE, R, or RE
–0.5
VCC + 0.5
V
Voltage input, transient pulse, A and B, through 100 Ω, see Figure 22
–50
50
V
–11
11
mA
Receiver output current
Continuous total power dissipation
TJ
Junction temperature
Tstg
Storage temperature
(1)
MIN
–0.3
See Dissipation Ratings
–55
170
°C
145
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(2)
7.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
Electrostatic
discharge
V(ESD)
(1)
(2)
(3)
Pins 5, 6, and 7
±16000
All pins
±4000
Charged device model (CDM), per JEDEC specification
JESD22-C101 (2)
All pins
±1000
Electrical fast transient/burst (3)
Pins 5, 6, and 7
UNIT
V
±4000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Tested in accordance with IEC 61000-4-4.
7.3 Recommended Operating Conditions
over operating free-air temperature range unless otherwise noted
MIN
VCC
Supply voltage
VI or VIC
Voltage at any bus terminal (separately or common mode)
VIH
High-level input voltage
VIL
VID
12
VCC
Low-level input voltage
D, DE, RE
0
0.8
Differential input voltage
See Figure 18
–12
12
Driver
–60
Low-level output current
RL
Differential load resistance
CL
Differential load capacitance
Signaling rate
4
Junction temperature
Receiver
V
mA
–8
Driver
60
Receiver
8
54
UNIT
3.6
2
IOL
(1)
(2)
3
D, DE, RE
High-level output current
(2)
MAX
–7 (1)
IOH
TJ
NOM
mA
Ω
60
50
pF
HVD10
32
HVD11
10
HVD12
1
145
Mbps
°C
The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
See thermal characteristics table for information regarding this specification.
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SLLS505O – FEBRUARY 2002 – REVISED FEBRUARY 2017
7.4 Thermal Information
SNx5HVD1xx
THERMAL METRIC
D (SOIC) P (PDIP)
8 Pins
RθJA
Junction-to-ambient thermal resistance (1)
RθJB
Junction-to-board thermal resistance
RθJC
Junction-to-case thermal resistance
(1)
(2)
(3)
High−K board (2), No airflow
No airflow
121
(3)
°C/W
93
High−K board
See
UNIT
8 Pins
67
(3)
°C/W
57
41
55
°C/W
The intent of RθJA specification is solely for a thermal performance comparison of one package to another in a standardized
environment. This methodology is not meant to and will not predict the performance of a package in an application-specific environment.
JSD51−7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.
JESD51−10, Test Boards for Through-Hole Perimeter Leaded Package Thermal Measurements.
7.5 Driver Electrical Characteristics
over recommended operating conditions unless otherwise noted
PARAMETER
VIK
MIN TYP (1)
TEST CONDITIONS
Input clamp voltage
II = –18 mA
–1.5
IO = 0
|VOD|
Differential output voltage (2)
RL = 54 Ω, See Figure 11
1.5
Vtest = –7 V to 12 V, See Figure 12
1.5
Change in magnitude of differential output
voltage
VOC(PP)
Peak-to-peak common-mode output voltage
VOC(SS)
Steady-state common-mode output voltage
ΔVOC(SS)
Change in steady-state common-mode
output voltage
IOZ
High-impedance output current
II
Input current
IOS
Short-circuit output current
–7 V ≤ VO ≤ 12 V
C(OD)
Differential output capacitance
VOD = 0.4 sin(4E6πt) + 0.5 V, DE at 0 V
(1)
(2)
See Figure 11 and Figure 12
VCC
V
–0.2
0.2
400
See Figure 13
UNIT
V
2
Δ|VOD|
ICC
MAX
V
mV
1.4
2.5
V
–0.05
0.05
V
See receiver input currents
D
DE
Supply current
–100
0
0
100
–250
250
16
μA
mA
pF
RE at VCC,
D and DE at VCC,
No load
Receiver disabled and
driver enabled
9
15.5
mA
RE at VCC,
D at VCC,
DE at 0 V,
No load
Receiver disabled and
driver disabled
(standby)
1
5
μA
RE at 0 V,
D and DE at VCC,
No load
Receiver enabled and
driver enabled
9
15.5
mA
All typical values are at 25°C and with a 3.3-V supply.
For TA > 85°C, VCC is ±5%.
Copyright © 2002–2017, Texas Instruments Incorporated
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SLLS505O – FEBRUARY 2002 – REVISED FEBRUARY 2017
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7.6 Receiver Electrical Characteristics
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
VIT+
Positive-going input threshold voltage
IO = –8 mA
VIT–
Negative-going input threshold
voltage
IO = 8 mA
Vhys
Hysteresis voltage (VIT+ – VIT–)
VIK
Enable-input clamp voltage
II = –18 mA
VOH
High-level output voltage
VID = 200 mV, IOH = –8 mA, see Figure 18
VOL
Low-level output voltage
VID = –200 mV, IOL = 8 mA, see Figure 18
IOZ
High-impedance-state output current
VO = 0 or VCC, RE at VCC
TYP (1)
MAX
–0.065
–0.01
–0.2
VA or VB = –7 V
V
2.4
V
HVD11, HVD12,
Other inputs at 0 V
VA or VB = –7 V
HVD10,
Other inputs at 0 V
0.13
–0.04
0.2
0.5
0.25
0.5
–0.4
–0.2
–0.15
VA or VB = –7 V, VCC = 0 V
–0.4
VIH = 2 V
–30
IIL
Low-level input current, RE
VIL = 0.8 V
–30
CID
Differential input capacitance
VID = 0.4 sin(4E6πt) + 0.5 V, DE at 0 V
(1)
μA
0.06
–0.05
High-level input current, RE
Supply current
1
0.11
–0.05
IIH
ICC
V
0.05
–0.1
VA or VB = 12 V
VA or VB = 12 V, VCC = 0 V
0.4
–1
VA or VB = –7 V, VCC = 0 V
Bus input current
mV
–1.5
VA or VB = 12 V
II
V
–0.1
35
VA or VB = 12 V, VCC = 0 V
UNIT
mA
mA
0
μA
0
μA
15
pF
RE at 0 V
D and DE at 0 V
No load
Receiver enabled and driver
disabled
4
8
mA
RE at VCC
D at VCC
DE at 0 V
No load
Receiver disabled and driver
disabled (standby)
1
5
μA
RE at 0 V
D and DE at VCC
No load
Receiver enabled and driver
enabled
9
15.5
mA
All typical values are at 25°C and with a 3.3-V supply.
7.7 Power Dissipation Characteristics
PARAMETER
PD
Device power dissipation
TEST CONDITIONS
RL= 60 Ω, CL = 50 pF,
DE at VCC, RE at 0 V,
Input to D is a 50% duty-cycle
square wave at indicated signaling
rate
MAX
198
250
HVD11
(10Mbps)
141
176
HVD12
(500 kbps)
133
161
D pkg
–40
116
No airflow (2)
P pkg
–40
123
Ambient air temperature (1)
TJSD
Thermal shutdown junction temperature (1)
6
MIN
High-K board, no airflow
TA
(1)
(2)
TYP
HVD10
(32Mbps)
165
UNIT
mW
°C
°C
See Thermal Characteristics of IC Packages section for an explanation of these parameters.
JESD51−10, Test Boards for Through-Hole Perimeter Leaded Package Thermal Measurements.
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SLLS505O – FEBRUARY 2002 – REVISED FEBRUARY 2017
7.8 Driver Switching Characteristics
over recommended operating conditions unless otherwise noted
MIN
TYP (1)
MAX
HVD10
5
8.5
16
HVD11
18
25
40
HVD12
135
200
300
HVD10
5
8.5
16
PARAMETER
Propagation delay time,
low-to-high-level output
tPLH
Propagation delay time,
high-to-low-level output
tPHL
TEST CONDITIONS
HVD11
18
25
40
HVD12
135
200
300
3
4.5
10
HVD10
Differential output signal
rise time
tr
Differential output signal
fall time
tf
tsk(p)
tsk(pp)
tPZH
tPHZ
tPZL
tPLZ
Pulse skew (|tPHL – tPLH|)
(2)
Part-to-part skew
Propagation delay time,
high-impedance-to-highlevel output
Propagation delay time,
high-level-to-highimpedance output
Propagation delay time,
high-impedance-to-lowlevel output
Propagation delay time,
low-level-to-highimpedance output
HVD11
RL = 54 Ω, CL = 50 pF
See Figure 14
10
20
30
HVD12
100
170
300
HVD10
3
4.5
10
HVD11
10
20
30
HVD12
100
170
300
HVD10
1.5
HVD11
2.5
HVD12
7
HVD10
6
HVD11
11
HVD12
100
HVD10
31
HVD11
55
HVD12
HVD10
RL = 110 Ω, RE at 0 V
See Figure 15
ns
ns
ns
ns
ns
ns
25
55
HVD12
300
HVD10
26
HVD11
55
HVD12
300
RL = 110 Ω, RE at 0 V
See Figure 16
ns
300
HVD11
HVD10
UNIT
ns
ns
26
HVD11
75
HVD12
400
ns
tPZH
Propagation delay time, standby-to-high- RL = 110 Ω, RE at 3 V
level output
See Figure 15
6
μs
tPZL
Propagation delay time, standby-to-lowlevel output
RL = 110 Ω, RE at 3 V
See Figure 16
6
μs
(1)
(2)
All typical values are at 25°C and with a 3.3-V supply.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
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7.9 Receiver Switching Characteristics
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
tPLH
Propagation delay time,
low-to-high-level output
HVD10
12.5
20
25
tPHL
Propagation delay time,
high-to-low-level output
HVD10
12.5
20
25
tPLH
Propagation delay time,
low-to-high-level output
HVD11
HVD12
30
55
70
ns
tPHL
Propagation delay time,
high-to-low-level output
HVD11
HVD12
30
55
70
ns
tsk(p)
Pulse skew (|tPHL – tPLH|)
tsk(pp)
(2)
Part-to-part skew
tr
Output signal rise time
tf
Output signal fall time
ns
HVD10
1.5
HVD11
4
HVD12
4
HVD10
8
HVD11
15
HVD12
15
CL = 15 pF
See Figure 19
tPZH
(1)
Output enable time to high level
tPZL
(1)
Output enable time to low level
Output disable time from high level
tPLZ
Output disable time from low level
(2)
tPZL
(2)
(1)
(2)
1
2
5
1
2
5
ns
ns
ns
15
tPHZ
tPZH
VID = –1.5 V to 1.5 V
CL = 15 pF
See Figure 19
15
CL = 15 pF, DE at 3 V
See Figure 20
20
ns
15
Propagation delay time, standby-to-highlevel output
CL = 15 pF, DE at 0
Propagation delay time, standby-to-low- See Figure 21
level output
6
μs
6
All typical values are at 25°C and with a 3.3-V supply
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
7.10 Dissipation Ratings
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR (1)
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
TA = 125°C
POWER RATING
D (2)
597 mW
4.97 mW/°C
373 mW
298 mW
100 mW
D (3)
990 mW
8.26 mW/°C
620 mW
496 mW
165 mW
P
1290 mW
10.75 mW/°C
806 mW
645 mW
215 mW
(1)
(2)
(3)
8
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
Tested in accordance with the Low-K thermal metric definitions of EIA/JESD51-3.
Tested in accordance with the High-K thermal metric definitions of EIA/JESD51-7.
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7.11 Typical Characteristics
70
TA = 25°C
RE at VCC
DE at VCC
RL = 54 W
CL = 50 pF
VCC = 3.6 V
60
50
VCC = 3 V
VCC = 3.3 V
40
30
0
5
10
15
20
25
30
35
TA = 25°C
RE at VCC
DE at VCC
I CC − RMS Supply Current − mA
I CC − RMS Supply Current − mA
70
50
VCC = 3 V
VCC = 3.3 V
40
30
0
2.5
Signaling Rate − Mbps
TA = 25°C
RE at VCC
DE at VCC
5
7.5
Signaling Rate − Mbps
10
Figure 2. HVD11 RMS Supply Current vs Signaling Rate
300
RL = 54 W
CL = 50 pF
250
VCC = 3.6 V
I I − Bus Input Current − mA
I CC − RMS Supply Current − mA
70
VCC = 3.6 V
60
40
Figure 1. HVD10 RMS Supply Current vs Signaling Rate
RL = 54 W
CL = 50 pF
60
VCC = 3.3 V
50
VCC = 3 V
40
TA = 25°C
DE at 0 V
200
VCC = 0 V
150
100
50
VCC = 3.3 V
0
−50
−100
−150
30
100
400
700
Signaling Rate − kbps
−200
−7 −6−5 −4−3 −2−1 0 1 2 3 4 5 6 7 8 9 10 11 12
VI − Bus Input Voltage − V
1000
Figure 3. HVD12 RMS Supply Current vs Signaling Rate
Figure 4. HVD10 Bus Input Current vs Bus Input Voltage
90
I I − Bus Input Current − mA
70
150
TA = 25°C
DE at 0 V
60
50
40
VCC = 0 V
30
20
10
0
VCC = 3.3 V
−10
−20
−30
−40
IOH − High-Level Output Current − mA
80
TA = 25°C
DE at VCC
D at VCC
VCC = 3.3 V
100
50
0
−50
−100
−150
−50
−60
−7−6 −5 −4 −3 −2 −1 0 1 2 3 4 5 6 7 8 9 10 11 12
VI − Bus Input Voltage − V
Figure 5. HVD11 or HVD12 Bus Input Current vs Bus Input
Voltage
Copyright © 2002–2017, Texas Instruments Incorporated
−200
−4
−2
0
2
4
VOH − Driver High-Level Output Voltage − V
6
Figure 6. High-Level Output Current vs Driver High-Level
Output Voltage
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SLLS505O – FEBRUARY 2002 – REVISED FEBRUARY 2017
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Typical Characteristics (continued)
200
2.5
TA = 25°C
DE at VCC
D at 0 V
VCC = 3.3 V
160
140
2.4
VOD − Driver Differential Output − V
I OL − Low-Level Output Current − mA
180
120
100
80
60
40
20
−20
−4
−2
0
2
4
6
VOL − Driver Low-Level Output Voltage − V
2.1
2.0
1.9
1.8
1.7
1.5
−40
8
Figure 7. Low-Level Output Current vs Driver Low-Level
Output Voltage
−15
10
35
60
TA − Free-Air Temperature − °C
85
Figure 8. Driver Differential Output vs Free-Air Temperature
600
−40
TA = 25°C
DE at VCC
D at VCC
RL = 54 Ω
−35
−30
500
HVD12
Enable Time − ns
I O − Driver Output Current − mA
2.2
1.6
0
−25
−20
−15
400
HVD11
300
HVD10
200
−10
100
−5
0
0
0
0.50
1
1.50
2
2.50
3
3.50
VCC − Supply Voltage − V
Figure 9. Driver Output Current vs Supply Voltage
10
2.3
VCC = 3.3 V
DE at VCC
D at VCC
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-7
-2
3
8
13
V(TEST) − Common-Mode Voltage − V
Figure 10. Enable Time vs Common-Mode Voltage
Copyright © 2002–2017, Texas Instruments Incorporated
Product Folder Links: SN65HVD10 SN65HVD11 SN65HVD12 SN75HVD10 SN75HVD11 SN75HVD12
SN65HVD10, SN65HVD11, SN65HVD12
SN75HVD10, SN75HVD11, SN75HVD12
www.ti.com
SLLS505O – FEBRUARY 2002 – REVISED FEBRUARY 2017
8 Parameter Measurement Information
VCC
DE
II
IOA
A
VOD
0 or 3 V
B
54 Ω±1%
IOB
VI
VOB
VOA
Copyright © 2017, Texas Instruments Incorporated
Figure 11. Driver VOD Test Circuit and Voltage and Current Definitions
375 Ω ±1%
VCC
DE
D
A
VOD
0 or 3 V
60 Ω ±1%
+
_ −7 V < V(test) < 12 V
B
375 Ω ±1%
Copyright © 2017, Texas Instruments Incorporated
Figure 12. Driver VOD With Common-Mode Loading Test Circuit
VCC
DE
Input
D
27 Ω ± 1%
A
A
VA
B
VB
VOC(PP)
27 Ω ± 1%
B
CL = 50 pF ±20%
VOC
DVOC(SS)
VOC
CL Includes Fixture and
Instrumentation Capacitance
Copyright © 2017, Texas Instruments Incorporated
Input: PRR = 500 kHz, 50% Duty Cycle, tr < 60 ns, tf < 6 ns ZO = 50 Ω
Figure 13. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
Copyright © 2002–2017, Texas Instruments Incorporated
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SN75HVD10, SN75HVD11, SN75HVD12
SLLS505O – FEBRUARY 2002 – REVISED FEBRUARY 2017
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Parameter Measurement Information (continued)
3V
VCC
DE
D
Input
Generator
VI
VOD
t PLH
CL Includes Fixture
and Instrumentation
Capacitance
RL = 54 Ω
± 1%
B
50 Ω
1.5 V
VI
CL = 50 pF ±20%
A
1.5 V
t PHL
90%
VOD
tr
≈2 V
90%
0V
10%
tf
0V
10%
≈ –2 V
Copyright © 2017, Texas Instruments Incorporated
Generator: PRR = 500 kHz, 50% Duty Cycle, tr < 60 ns, tf < 6 ns ZO = 50 Ω
Figure 14. Driver Switching Test Circuit and Voltage Waveforms
A
3V
D
3V
S1
VO
VI
1.5 V
1.5 V
B
DE
Input
Generator
VI
50 Ω
0V
0.5 V
RL = 110 Ω
± 1%
CL = 50 pF ±20%
t PZH
VOH
CL Includes Fixture
and Instrumentation
Capacitance
VO
2.3 V
≈0V
t PHZ
Copyright © 2017, Texas Instruments Incorporated
Generator: PRR = 500 kHz, 50% Duty Cycle, tr < 60 ns, tf < 6 ns ZO = 50 Ω
Figure 15. Driver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms
3V
A
3V
D
VI
≈3 V
1.5 V
VI
S1
1.5 V
VO
DE
Input
Generator
RL = 110 Ω
± 1%
0V
B
t PZL
t PLZ
≈3 V
CL = 50 pF ±20%
50 Ω
CL Includes Fixture
and Instrumentation
Capacitance
0.5 V
VO
2.3 V
VOL
Copyright © 2017, Texas Instruments Incorporated
Generator: PRR = 500 kHz, 50% Duty Cycle, tr < 60 ns, tf < 6 ns ZO = 50 Ω
Figure 16. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
12
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SN75HVD10, SN75HVD11, SN75HVD12
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SLLS505O – FEBRUARY 2002 – REVISED FEBRUARY 2017
Parameter Measurement Information (continued)
375 Ω ± 1%
Y
-7 V < V(TEST) < 12 V
D
0 or 3 V
60 W
± 1%
VOD
Z
DE
375 Ω ± 1%
Input
Generator
V
50 Ω
50%
tpZH(diff)
VOD (high)
1.5 V
0V
tpZL(diff)
-1.5 V
VOD (low)
Copyright © 2017, Texas Instruments Incorporated
The time tPZL(x) is the measure from DE to VOD(x). VOD is valid when it is greater than 1.5 V.
Figure 17. Driver Enable Time from DE to VOD
IA
VA
VA + VB
2
VIC
VB
A
R
VID
IB
IO
B
VO
Copyright © 2017, Texas Instruments Incorporated
Figure 18. Receiver Voltage and Current Definitions
Copyright © 2002–2017, Texas Instruments Incorporated
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13
SN65HVD10, SN65HVD11, SN65HVD12
SN75HVD10, SN75HVD11, SN75HVD12
SLLS505O – FEBRUARY 2002 – REVISED FEBRUARY 2017
www.ti.com
Parameter Measurement Information (continued)
A
VO
R
Input
Generator
VI
50 Ω
B
1.5 V
CL = 15 pF ±20%
RE
0V
CL Includes Fixture
and Instrumentation
Capacitance
Generator: PRR = 500 kHz, 50% Duty Cycle, tr
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