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SN65HVD1470, SN65HVD1471, SN65HVD1473
SN65HVD1474, SN65HVD1476, SN65HVD1477
SLLSEJ8E – JUNE 2014 – REVISED APRIL 2019
SN65HVD147x 3.3-V Full-Duplex RS-485 Transceivers with ±16-kV IEC ESD
1 Features
•
1
•
•
•
•
•
•
•
1/8 Unit-Load Options Available
– Up to 256 Nodes on the Bus
Bus I/O Protection
– > ±30 kV HBM protection
– > ±16 kV IEC61000-4-2 Contact Discharge
– > ±4 kV IEC61000-4-4 Fast Transient Burst
Extended Industrial Temperature Range:
–40°C to 125°C
Large Receiver Hysteresis (70 mV) for Noise
Rejection
Low Power Consumption
– < 1.1 mA Quiescent Current During Operation
– Low Standby Supply Current: 10 nA Typical,
< 5 µA (maximum)
Glitch-Free Power-Up and Power-Down Protection
for Hot-Plugging Applications
5-V Tolerant Logic Inputs Compatible With 3.3-V
or 5-V Controllers
Signaling Rate Options Optimized for:
400 kbps (1470, 1471), 20 Mbps (1473, 1474), 50
Mbps (1476, 1477)
2 Applications
•
•
•
•
•
Industrial Automation
Encoders and Decoders
Building Automation
Security and Surveillance Networks
Telecommunications
These devices each combine a differential driver and
a differential receiver, which operate from a single
3.3-V power supply. Each driver and receiver has
separate input and output pins for full-duplex bus
communication designs. These devices all feature a
wide common-mode voltage range which makes the
devices suitable for multi-point applications over long
cable runs.
The
SN65HVD1471,
SN65HVD1474,
and
SN65HVD1477 devices are fully enabled with no
external enabling pins.
The
SN65HVD1470,
SN65HVD1473,
and
SN65HVD1476 devices have active-high driver
enables and active-low receiver enables. A low, less
than 5-µA standby current can be achieved by
disabling both the driver and receiver.
These devices are characterized from –40°C to
125°C.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN65HVD1471
SN65HVD1474
SN65HVD1477
MSOP (8)
3.00 mm × 3.00 mm
SOIC (8)
4.90 mm × 3.91 mm
SN65HVD1470
SN65HVD1473
SN65HVD1476
MSOP (10)
3.00 mm × 3.00 mm
SOIC (14)
8.65 mm × 3.91 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Block Diagram
VCC
VCC
A
R
3 Description
RE
The SN65HVD147x family of full-duplex transceivers
feature the highest ESD protection in the RS-485
portfolio, supporting ±16-kV IEC61000-4-2 contact
discharge and > ±30-kV HBM ESD protection. These
RS-485 transceivers have robust 3.3-V drivers and
receivers and are offered in a standard SOIC
package as well as in a small-footprint MSOP
package. The large receiver hysteresis of the
SN65HVD147x devices provides immunity to
conducted differential noise and the wide operating
temperature enables reliability in harsh operating
environments.
DE
D
R
B
A
R
R
B
VCC
Z
D
Y
D
Z
D
Y
GND
GND
SN65HVD1470,
SN65HVD1473, and
SN65HVD1476
SN65HVD1471,
SN65HVD1474, and
SN65HVD1477
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN65HVD1470, SN65HVD1471, SN65HVD1473
SN65HVD1474, SN65HVD1476, SN65HVD1477
SLLSEJ8E – JUNE 2014 – REVISED APRIL 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
8
9
1
1
1
2
3
3
6
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 7
Thermal Information — D Packages......................... 7
Thermal Information — DGS and DGK Packages.... 7
Power Dissipation ..................................................... 8
Electrical Characteristics........................................... 8
Switching Characteristics — 400 kbps...................... 9
Switching Characteristics — 20 Mbps .................... 10
Switching Characteristics — 50 Mbps .................. 10
Typical Characteristics .......................................... 11
Parameter Measurement Information ................ 13
Detailed Description ............................................ 17
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
17
17
17
17
10 Application and Implementation........................ 20
10.1 Application Information.......................................... 20
10.2 Typical Application ................................................ 20
11 Power Supply Recommendations ..................... 26
12 Layout................................................................... 26
12.1 Layout Guidelines ................................................. 26
12.2 Layout Example .................................................... 27
13 Device and Documentation Support ................. 28
13.1
13.2
13.3
13.4
13.5
13.6
13.7
Device Support......................................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
28
28
28
28
28
28
28
14 Mechanical, Packaging, and Orderable
Information ........................................................... 29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (October 2014) to Revision E
Page
•
Changed the Pin Configuration images.................................................................................................................................. 3
•
Changed the Supply Voltage MAX value From: 5.5 V To 5 V in the Absolute Maximum Ratings ........................................ 6
•
Moved Storage Temperature From the ESD table to the Absolute Maximum Ratings.......................................................... 6
•
Changed the Handling Ratings table to ESD Ratings............................................................................................................ 6
•
Added Note: to Supply voltage in the Recommended Operating Conditions......................................................................... 7
Changes from Revision C (August 2014) to Revision D
•
Page
Updated the MSOP–10 logic diagram ................................................................................................................................... 4
Changes from Revision B (July 2014) to Revision C
•
Page
Updated the Device Comparison Table.................................................................................................................................. 3
Changes from Revision A (June 2014) to Revision B
•
Page
Updated SN65HVD1470 and SN65HVD1471 specifications to production values ............................................................... 3
Changes from Original (May 2014) to Revision A
•
2
Page
Changed device status from Product Preview to Production Data (mixed status) ................................................................ 1
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SN65HVD1474, SN65HVD1476, SN65HVD1477
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SLLSEJ8E – JUNE 2014 – REVISED APRIL 2019
5 Device Comparison Table
PART NUMBER (1)
(1)
SIGNALING RATE
DUPLEX
ENABLES
PACKAGE
NODES
256
SN65HVD1470
up to 400 kbps
Full
DE, RE
SOIC-14
MSOP-10
SN65HVD1471
up to 400 kbps
Full
None
SOIC-8
MSOP-8
256
SN65HVD1473
up to 20 Mbps
Full
DE, RE
SOIC-14
MSOP-10
256
SN65HVD1474
up to 20 Mbps
Full
None
SOIC-8
MSOP-8
256
SN65HVD1476
up to 50 Mbps
Full
DE, RE
SOIC-14
MSOP-10
96
SN65HVD1477
up to 50 Mbps
Full
None
SOIC-8
MSOP-8
96
For device status, see the Mechanical, Packaging, and Orderable Information section.
6 Pin Configuration and Functions
SN65HVD1471, SN65HVD1474, SN65HVD1477
8-Pin SOIC, D Package, and 8-Pin MSOP, DGK Package
(Top View)
SN65HVD1471
8-Pin SOIC, D Package
8
2
R
VCC
1
8
A
R
2
7
B
D
3
6
Z
A
7
B
5
3
D
GND
4
5
Y
Y
6
Z
No t to scale
Pin Functions — SOIC-8 and MSOP-8
PIN
NAME
NO.
TYPE
DESCRIPTION
VCC
1
Supply
3-V to 3.6-V supply
R
2
Digital output
Receive data output
D
3
Digital input
GND
4
Reference potential
Y
5
Bus output
Digital bus output, Y (Complementary to Z)
Z
6
Bus output
Digital bus output, Z (Complementary to Y)
B
7
Bus input
Digital bus input, B (Complementary to A)
A
8
Bus input
Digital bus input, A (Complementary to B)
Driver data input
Local device ground
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SN65HVD1470, SN65HVD1471, SN65HVD1473
SN65HVD1474, SN65HVD1476, SN65HVD1477
SLLSEJ8E – JUNE 2014 – REVISED APRIL 2019
www.ti.com
SN65HVD1470, SN65HVD1473, SN65HVD1476
10-Pin MSOP, DGS Package
(Top View)
SN65HVD1470
10-Pin MSOP, DGS Package
3
R
1
RE
10
2
9
VCC
6
4
7
A
2
DE
3
8
B
D
4
7
Z
GND
5
6
Y
9
1
8
No t to scale
Pin Functions — MSOP–10
PIN
NAME
NO.
TYPE
DESCRIPTION
R
1
Digital output
Receive data output
RE
2
Digital input
Receive enable Low
DE
3
Digital input
Driver enable High
D
4
Digital input
Driver data input
GND
5
Reference potential
Y
6
Bus output
Digital bus output, Y (Complementary to Z)
Z
7
Bus output
Digital bus output, Z (Complementary to Y)
B
8
Bus input
Digital bus input, B (Complementary to A)
A
9
Bus input
Digital bus input, A (Complementary to B)
VCC
10
Supply
4
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Local device ground
3-V to 3.6-V supply
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: SN65HVD1470 SN65HVD1471 SN65HVD1473 SN65HVD1474 SN65HVD1476 SN65HVD1477
SN65HVD1470, SN65HVD1471, SN65HVD1473
SN65HVD1474, SN65HVD1476, SN65HVD1477
www.ti.com
SLLSEJ8E – JUNE 2014 – REVISED APRIL 2019
SN65HVD1470, SN65HVD1473, SN65HVD1476
14-Pin SOIC, D Package
(Top View)
NC
1
14
VCC
R
2
13
VCC
RE
3
12
A
DE
4
11
B
D
5
10
Z
GND
6
9
Y
GND
7
8
NC
NC = no internal connection
SN65HVD1470
10-Pin MSOP, DGS Package
No t to scale
Pin Functions — SOIC-14
PIN
NAME
NO.
1
NC
8
TYPE
DESCRIPTION
No connect
Not connected
R
2
Digital output
Receive data output
RE
3
Digital input
Receive enable Low
DE
4
Digital input
Driver enable High
D
5
Digital input
Driver data input
GND
6 (1)
7 (1)
Reference potential
Local device ground
Y
9
Bus output
Digital bus output, Y (Complementary to Z)
Z
10
Bus output
Digital bus output, Z (Complementary to Y)
B
11
Bus input
Digital bus input, B (Complementary to A)
A
12
Bus input
Digital bus input, A (Complementary to B)
VCC
(1)
(2)
13 (2)
14 (2)
Supply
3-V to 3.6-V supply
Pin 6 and pin 7 are connected internally.
Pin 13 and pin 14 are connected internally.
Copyright © 2014–2019, Texas Instruments Incorporated
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SN65HVD1470, SN65HVD1471, SN65HVD1473
SN65HVD1474, SN65HVD1476, SN65HVD1477
SLLSEJ8E – JUNE 2014 – REVISED APRIL 2019
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
–0.5
5
V
Range at any bus pin (A, B, Y, or Z)
–13
16.5
V
Range at any logic pin (D, DE, or RE)
–0.3
5.7
V
Voltage input range, transient pulse, any bus pin (A, B, Y, or Z) through 100 Ω
–100
100
V
Receiver output
–24
Supply voltage
VCC
Voltage
Input voltage
Output current
Junction temperature, TJ
Storage temperature range, Tstg
–65
mA
°C
150
°C
See the Thermal
Information table
Continuous total power dissipation
(1)
24
170
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
V(ESD)
(1)
(2)
(3)
6
Electrostatic discharge
VALUE
UNIT
IEC 61000-4-2 ESD (Contact Discharge), bus pins and GND
±16000
V
IEC 61000-4-2 ESD (Air-Gap Discharge), bus pins and GND (1) (2)
±16000
V
IEC 61000-4-4 EFT (Fast transient or burst), bus pins and GND
±4000
V
IEC 60749-26 ESD (Human Body Model), bus pins and GND
(2)
±30000
V
Human body model (HBM), bus pins and GND (3)
±40000
V
Human body model (HBM), per JEDEC specification JESD22-A114, all pins
±8000
V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins
±1500
V
Machine model (MM), all pins
±30000
V
By inference from contact-discharge results, see the Application and Implementation section
Limited by tester capability.
Modeled performance only; based on measured IEC ESD (Contact) capability.
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SN65HVD1474, SN65HVD1476, SN65HVD1477
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SLLSEJ8E – JUNE 2014 – REVISED APRIL 2019
7.3 Recommended Operating Conditions
IEC 61000-4-2 ESD (Contact Discharge), bus pins and GND
MIN
(1)
VCC
Supply voltage
VI
Input voltage at any bus pin (separately or common mode)
VIH
High-level input voltage (Driver, driver enable, and receiver enable inputs)
VIL
Low-level input voltage (Driver, driver enable, and receiver enable inputs)
VID
Differential input voltage
IO
Output current, Driver
–60
IO
Output current, Receiver
–8
RL
Differential load resistance
54
CL
Differential load capacitance
1/tUI
Signaling rate
NOM MAX
3
(2)
3.3
UNIT
3.6
V
–7
12
V
2
VCC
V
0
0.8
V
–12
12
V
60
mA
8
mA
60
Ω
50
pF
HVD1470, HVD1471
400
HVD1473, HVD1474
20
HVD1476, HVD1477
50
kbps
Mbps
TA (3)
Operating free-air temperature (See the Application and Implementation for thermal
information)
–40
125
°C
TJ
Junction Temperature
–40
150
°C
(1)
(2)
(3)
Exposure to conditions beyond the recommended operation maximum for extended periods may affect device reliability.
The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
Operation is specified for internal (junction) temperatures up to 150°C. Self-heating because of internal power dissipation should be
considered for each application. Maximum junction temperature is internally limited by the thermal shut-down (TSD) circuit which
disables the driver outputs when the junction temperature reaches 170°C.
7.4 Thermal Information — D Packages
THERMAL METRIC
D
(8 PINS)
D
(14 PINS)
UNIT
RθJA
Junction-to-ambient thermal resistance
110.7
83.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
54.7
42.9
°C/W
RθJB
Junction-to-board thermal resistance
51.3
37.8
°C/W
ψJT
Junction-to-top characterization parameter
9.2
9.3
°C/W
ψJB
Junction-to-board characterization parameter
50.7
37.5
°C/W
TJ(TSD)
Thermal shut-down junction temperature
170
°C
7.5 Thermal Information — DGS and DGK Packages
THERMAL METRIC
DGS
(10 PINS)
DGK
(8 PINS)
UNIT
RθJA
Junction-to-ambient thermal resistance
165.5
168.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
37.7
62.2
°C/W
RθJB
Junction-to-board thermal resistance
86.4
89.5
°C/W
ψJT
Junction-to-top characterization parameter
1.4
7.4
°C/W
ψJB
Junction-to-board characterization parameter
84.8
87.9
°C/W
TJ(TSD)
Thermal shut-down junction temperature
Copyright © 2014–2019, Texas Instruments Incorporated
170
°C
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7.6 Power Dissipation
PARAMETER
TEST CONDITIONS
Unterminated
Power Dissipation
driver and receiver enabled,
VCC = 3.6 V, TJ = 150°C
50% duty cycle square-wave signal at
signaling rate:
•
HVD1470 and HVD1471 at 400 kbps
•
HVD1473 and HVD1474 at 20 Mbps
•
HVD1476 and HVD1477 at 50 Mbps
PD
RS-422 load
RS-485 load
RL = 300 Ω,
CL = 50 pF (driver)
RL = 100 Ω,
CL = 50 pF (driver)
RL = 54 Ω,
CL = 50 pF (driver)
VALUE
HVD1470,
HVD1471
150
HVD1473,
HVD1474
180
HVD1476,
HVD1477
220
HVD1470,
HVD1471
190
HVD1473,
HVD1474
220
HVD1476,
HVD1477
250
HVD1470,
HVD1471
230
HVD1473,
HVD1474
255
HVD1476,
HVD1477
285
UNIT
mW
mW
mW
7.7 Electrical Characteristics
over recommended operating range (unless otherwise specified)
PARAMETER
|VOD|
TEST CONDITIONS
Driver differential output voltage magnitude
MIN
TYP
RL = 60 Ω, 375 Ω on each
output to –7 V to 12 V, See Figure 15
1.5
2
V
RL = 54 Ω (RS-485), See Figure 16
1.5
2
V
RL = 100 Ω (RS-422) TJ ≥ 0°C,
VCC ≥ 3.2 V, See Figure 16
Δ|VOD|
Change in magnitude of driver differential output voltage
VOC(SS)
Steady-state common-mode output voltage
ΔVOC
Change in differential driver output common-mode voltage
VOC(PP)
Peak-to-peak driver common-mode output voltage
COD
Differential output capacitance
VIT+
Positive-going receiver differential input voltage threshold
VIT–
Negative-going receiver differential input voltage threshold
Vhys
Receiver differential input voltage threshold hysteresis
(VIT+ – VIT–)
VOH
Receiver high-level output voltage
IOH = –8 mA
VOL
Receiver low-level output voltage
IOL = 8 mA
II
Driver input, driver enable, and receiver enable input current
IOZ
Receiver output high-impedance
current
IOS
Driver short-circuit output current
II
2
RL = 54 Ω, CL = 50 pF, See Figure 16
Center of two 27-Ω load resistors,
See Figure 16
(1)
8
–50
0
50
1
VCC / 2
3
V
–50
0
50
mV
Bus input current (disabled driver)
Supply current (quiescent)
(1)
-70
–200
-140
40
70
2.4
VCC–0.3
See
0.2
VO = 0 V or VCC, RE = VCC
VCC = 0 to ROC (max),
DE = GND
(1)
mV
See
mV
V
–3
3
µA
–1
1
µA
150
mA
75
–100
VI = 12 V
VI = –7 V
mV
V
VI = 12 V
VI = –7 V
pF
–20
0.4
–150
HVD1470,
HVD1473
mV
mV
15
HVD1470, HVD1473,
HVD1476
UNIT
V
500
HVD1476
ICC
MAX
–40
240
–267
125
333
µA
–180
Driver and Receiver
enabled
DE = VCC,
RE = GND, No load
750
1100
µA
Driver enabled,
receiver disabled
DE = VCC, RE = VCC,
No load
350
650
µA
Driver disabled,
receiver enabled
DE = GND,
RE = GND, No load
650
800
µA
Driver and receiver
disabled
DE = GND, D = open,
RE = VCC, No load
0.1
5
µA
Under any specific conditions, VIT+ is assured to be at least Vhys higher than VIT–.
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Electrical Characteristics (continued)
over recommended operating range (unless otherwise specified)
PARAMETER
TEST CONDITIONS
Supply current (dynamic)
Tsd
MIN
TYP
MAX
UNIT
170
°C
See the Typical Characteristics section
Thermal Shut-down junction temperature
7.8 Switching Characteristics — 400 kbps
400-kbps devices (SN65HVD1470, SN65HVD1471) bit time ≥ 2 µs (over recommended operating conditions)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
100
400
750
ns
350
550
ns
40
ns
50
200
ns
300
750
ns
3
8
µs
13
25
ns
70
110
ns
7
ns
45
60
ns
20
115
ns
3
8
µs
DRIVER
tr, tf
Driver differential output rise/fall time
tPHL, tPLH
Driver propagation delay
tSK(P)
Driver pulse skew, |tPHL – tPLH|
tPHZ, tPLZ
Driver disable time
tPZH, tPZL
Driver enable time
RL = 54 Ω, CL = 50 pF
HVD1470
Receiver enabled
See Figure 17
See Figure 18
and Figure 19
Receiver disabled
RECEIVER
tr, tf
Receiver output rise/fall time
tPHL, tPLH
Receiver propagation delay time
tSK(P)
Receiver pulse skew, |tPHL – tPLH|
tPLZ, tPHZ
Receiver disable time
tPZL(1),
tPZH(1)
tPZL(2),
tPZH(2)
Receiver enable time
Copyright © 2014–2019, Texas Instruments Incorporated
CL = 15 pF
HVD1470
Driver enabled
Driver disabled
See Figure 20
See Figure 21
See Figure 22
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7.9 Switching Characteristics — 20 Mbps
20-Mbps devices (SN65HVD1473, SN65HVD1474) bit time ≥ 50 ns (over recommended operating conditions)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
DRIVER
tr, tf
Driver differential output rise/fall time
tPHL, tPLH
Driver propagation delay
tSK(P)
Driver pulse skew, |tPHL – tPLH|
tPHZ, tPLZ
Driver disable time
tPZH, tPZL
Driver enable time
RL = 54 Ω, CL = 50 pF
HVD1473
Receiver enabled
See Figure 17
4
7
14
ns
4
10
20
ns
0
4
ns
12
25
ns
10
20
ns
3
8
µs
5
10
ns
60
90
ns
See Figure 18 and
Figure 19
Receiver disabled
RECEIVER
tr, tf
Receiver output rise/fall time
tPHL, tPLH
Receiver propagation delay time
tSK(P)
Receiver pulse skew, |tPHL – tPLH|
tPLZ, tPHZ
Receiver disable time
tpZL(1), tPZH(1)
tPZL(2), tPZH(2)
Receiver enable time
CL = 15 pF
HVD1473
See Figure 20
0
5
ns
17
25
ns
Driver enabled
See Figure 21
12
90
ns
Driver disabled
See Figure 22
3
8
µs
7.10 Switching Characteristics — 50 Mbps
50-Mbps devices (SN65HVD1476, SN65HVD1477) bit time ≥ 20 ns (over recommended operating conditions)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
DRIVER
tr, tf
Driver differential output rise/fall time
tPHL, tPLH
Driver propagation delay
tSK(P)
Driver pulse skew, |tPHL – tPLH|
tPHZ, tPLZ
Driver disable time
tPZH, tPZL
Driver enable time
RL = 54 Ω, CL = 50 pF
HVD1476
Receiver enabled
See Figure 17
2
3
6
ns
3
10
16
ns
0
3.5
ns
10
20
ns
10
20
ns
3
8
µs
See Figure 18 and
Figure 19
Receiver disabled
RECEIVER
tr, tf
Receiver output rise/fall time
tPHL, tPLH
Receiver propagation delay time
tSK(P)
Receiver pulse skew, |tPHL – tPLH|
tPLZ, tPHZ
Receiver disable time
tpZL(1), tPZH(1)
tPZL(2), tPZH(2)
10
Receiver enable time
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1
CL = 15 pF
HVD1476
See Figure 20
3
6
ns
25
40
ns
0
2
ns
ns
8
15
Driver enabled
See Figure 21
8
90
ns
Driver disabled
See Figure 22
3
8
µs
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7.11 Typical Characteristics
3.5
3.6
Driver Output Voltage (V)
3
Driver Differential-Output Voltage (V)
VOH
VOL
3.3
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
10
20
30
40
50
60
70
Driver Output Current (mA)
80
90
2
1.5
1
0.5
0
100
10
20
30
40
50
60
70
Driver Output Current (mA)
D001
Figure 1. Driver Output Voltage vs Driver Output Current
80
90
100
D002
Figure 2. Driver Differential-Output Voltage vs Driver Output
Current
50
2.2
45
2.15
Driver Output Current (mA)
Driver Differential-Output Voltage (V)
2.5
0
0
2.1
2.05
2
1.95
40
35
30
25
20
15
10
5
1.9
-7
0
-5
-3
-1
1
3
5
7
Driver Common-Mode Voltage (V)
9
0
11
0.5
1
D003
Figure 3. Driver Differential-Output Voltage vs Driver
Common-Mode Voltage
360
360
355
355
350
345
340
335
330
325
320
1.5
2
2.5
Supply Voltage (V)
3
3.5
D004
Figure 4. Driver Output Current vs Supply Voltage
Driver Propagation Delay (ns)
Driver Rise and Fall Time (ns)
Differential Driver Output Voltage (V)
100 : Load Line
60 : Load Line
3
350
345
340
335
330
325
320
315
-40
-20
0
20
40
60
Temperature (qC)
80
100
120
D009
Figure 5. SN65HVD1470, SN65HVD1471 Driver Rise and Fall
Time vs Temperature
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315
-40
-20
0
20
40
60
Temperature (qC)
80
100
120
D010
Figure 6. SN65HVD1470, SN65HVD1471 Driver Propagation
Delay vs Temperature
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Typical Characteristics (continued)
10
14
Driver Propagation Delay (ns)
Driver Rise and Fall Time (ns)
9
8
7
6
5
4
3
2
1
0
-40
-20
0
20
40
60
Temperature (qC)
80
100
12
10
8
6
4
2
0
-40
120
-20
0
20
40
60
Temperature (qC)
D005
Figure 7. SN65HVD1473, SN65HVD1474 Driver Rise and Fall
Time vs Temperature
80
100
120
D006
Figure 8. SN65HVD1473, SN65HVD1474 Driver Propagation
Delay vs Temperature
4
12
Series1
Driver Propagation Delay (ns)
Driver Rise and Fall Time (ns)
3.5
3
2.5
2
1.5
1
0.5
0
-40
-20
0
20
40
60
Temperature (qC)
80
100
10
8
6
4
2
0
-40
120
-20
0
20
40
60
Temperature (qC)
D011
Figure 9. SN65HVD1476, SN65HVD1477 Driver Rise and Fall
Time vs Temperature
80
100
120
D012
Figure 10. SN65HVD1476, SN65HVD1477 Driver Propagation
Delay vs Temperature
80
42
70
Supply Current (mA)
Supply Current (mA)
41.8
41.6
41.4
60
50
40
30
20
41.2
10
0
41
0
0.05
0.1
0.15
0.2
0.25
Signaling Rate (Mbps)
0.3
0.35
0.4
0
2
4
D013
VCC = 3.3 V
Figure 11. SN65HVD1470, SN65HVD1471 Supply Current vs
Signal Rate
12
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6
8
10
12
14
Signaling Rate (Mbps)
16
18
20
D007
TA = 25°C
Figure 12. SN65HVD1473, SN65HVD1474 Supply Current vs
Signal Rate
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80
4
70
3.5
60
3
Receiver output, R (V)
Supply Current (mA)
Typical Characteristics (continued)
50
40
30
20
10
2.5
2
1.5
1
VCM = 12 V
VCM = 0 V
VCM = -7 V
0.5
0
0
5
10
15
20
25
30
35
Signaling Rate (Mbps)
40
45
0
-150
50
-130
D014
VCC = 3.3 V
Figure 13. SN65HVD1476, SN65HVD1477 Supply Current vs
Signal Rate
-110
-90
-70
Differential Input Voltage (mV)
-50
D008
TA = 25°C
Figure 14. Receiver Output vs Input
8 Parameter Measurement Information
The input generator rate is 100 kbps with 50% duty cycle, than 6-ns rise and fall times, and 50-Ω output
impedance.
375 W ±1%
VCC
DE
0 V or 3 V
D
Y
VOD
60 W ±1%
Z
+
_
–7 V < V (test) < 12 V
375 W ±1%
S0301-01
Figure 15. Measurement of Driver Differential Output Voltage With Common-Mode Load
0 V or 3 V
VOD
Z
V(Y)
Z
V(Z)
RL / 2
Y
D
Y
VOC(PP)
RL / 2
CL
DVOC(SS)
VOC
VOC
S0302-01
Figure 16. Measurement of Driver Differential and Common-Mode Output With RS-485 Load
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Parameter Measurement Information (continued)
50%
50%
Y
W
»
W
Z
»
Figure 17. Measurement of Driver Differential Output Rise and Fall Times and Propagation Delays
Y
D
3V
50 W
VI
VO
VI
Z
CL = 50 pF ±20%
DE
Input
Generator
3V
S1
50%
50%
0V
RL = 110 W
± 1%
CL Includes Fixture
and Instrumentation
Capacitance
tPZH
VOH
90%
VO
50%
»0V
tPHZ
S0304-01
D at 3 V to test non-inverting output, D at 0 V to test inverting output.
Figure 18. Measurement of Driver Enable and Disable Times with Active-High Output and Pulldown Load
3V
Y
D
3V
S1
VO
»3V
VI
50%
50%
0V
Z
DE
Input
Generator
RL = 110 W
±1%
tPZL
tPLZ
CL = 50 pF ±20%
VI
50 W
»3V
CL Includes Fixture
and Instrumentation
Capacitance
VO
50%
10%
VOL
S0305-01
D at 0 V to test non-inverting output, D at 3 V to test inverting output.
Figure 19. Measurement of Driver Enable and Disable Times with Active-Low Output and Pullup Load
3V
A
Input
Generator
R
VI
50 W
1.5 V
0V
VI
VO
50%
50%
0V
B
RE
tPLH
CL = 15 pF ±20%
VO
CL Includes Fixture
and Instrumentation
Capacitance
tPHL
90% 90%
50%
10%
50%
10%
tr
VOH
VOL
tf
S0306-01
Figure 20. Measurement of Receiver Output Rise and Fall Times and Propagation Delays
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Parameter Measurement Information (continued)
3V
VCC
DE
0 V or 3 V D
Y
A
Z
B
RE
Input
Generator
VI
1 kW ± 1%
R VO
S1
CL = 15 pF ±20%
CL Includes Fixture
and Instrumentation
Capacitance
50 W
3V
VI
50%
50%
0V
tPZH(1)
tPHZ
VOH
90%
VO
50%
D at 3 V
S1 to GND
»0V
tPZL(1)
tPLZ
VCC
VO
50%
D at 0 V
S1 to VCC
10%
VOL
S0307-01
Figure 21. Measurement of Receiver Enable and Disable Times With Driver Enabled
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Parameter Measurement Information (continued)
VCC
A
0 V or 1.5 V
R VO
S1
B
1.5 V or 0 V
RE
Input
Generator
VI
1 kW ± 1%
CL = 15 pF ±20%
CL Includes Fixture
and Instrumentation
Capacitance
50 W
3V
VI
50%
0V
tPZH(2)
VOH
VO
A at 1.5 V
B at 0 V
S1 to GND
50%
GND
tPZL(2)
VCC
VO
50%
VOL
A at 0 V
B at 1.5 V
S1 to VCC
S0308-01
Figure 22. Measurement of Receiver Enable Times With Driver Disabled
16
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9 Detailed Description
9.1 Overview
The SN65HVD1470, SN65HVD1471, SN65HVD1473, SN65HVD1474, SN65HVD1476, and SN65HVD1477
devices are low-power, full-duplex RS-485 transceivers available in three speed grades suitable for data
transmission up to 400 kbps, 20 Mbps, and 50 Mbps.
The SN65HVD1471, SN65HVD1474, and SN65HVD1477 are fully enabled with no external enabling pins. The
SN65HVD1470, SN65HVD1473, and SN65HVD1476 have active-high driver enables and active-low receiver
enables. A standby current of less than 5 µA can be achieved by disabling both driver and receiver.
9.2 Functional Block Diagram
VCC
VCC
A
R
A
R
R
B
R
B
RE
VCC
DE
D
Z
D
D
Y
Z
D
Y
GND
GND
Figure 23. Block Diagram
SN65HVD1470, SN65HVD1473, and SN65HVD1476
Figure 24. Block Diagram
SN65HVD1471, SN65HVD1474, and SN65HVD1477
9.3 Feature Description
Internal ESD protection circuits protect the transceiver against Electrostatic Discharges (ESD) according to
IEC61000-4-2 of up to ±16 kV, and against electrical fast transients (EFT) according to IEC61000-4-4 of up to ±4
kV.
The SN65HVD147x full-duplex family provides internal biasing of the receiver input thresholds in combination
with large input-threshold hysteresis. At a positive input threshold of VIT+ = –20 mV and an input hysteresis of
Vhys = 40 mV, the receiver output remains logic high under a bus-idle or bus-short condition even in the presence
of 120 mVPP differential noise without the need for external failsafe biasing resistors.
Device operation is specified over a wide temperature range from –40°C to 125°C.
9.4 Device Functional Modes
For the SN65HVD1470, SN65HVD1473, and SN65HVD1476, when the driver enable pin, DE, is logic high, the
differential outputs Y and Z follow the logic states at data input D. A logic high at D causes Y to turn high and Z
to turn low. In this case the differential output voltage defined as VOD = V(Y) – V(Z) is positive. When D is low, the
output states reverse, Z turns high, Y becomes low, and VOD is negative.
When DE is low, both outputs turn high-impedance. In this condition the logic state at D is irrelevant. The DE pin
has an internal pulldown resistor to ground, thus when left open the driver is disabled (high-impedance) by
default. The D pin has an internal pullup resistor to VCC, thus, when left open while the driver is enabled, output Y
turns high and Z turns low.
Table 1. Driver Function Table SN65HVD1470, SN65HVD1473, SN65HVD1476
INPUT
ENABLE
D
DE
Y
H
H
H
L
Actively drives the bus high
L
H
L
H
Actively drives the bus low
X
L
Z
Z
Driver disabled
X
OPEN
Z
Z
Driver disabled by default
OPEN
H
H
L
Actively drives the bus high by default
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OUTPUTS
FUNCTION
Z
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When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage
defined as VID = V(A) – V(B) is positive and higher than the positive input threshold, VIT+, the receiver output, R,
turns high. When VID is negative and less than the negative and lower than the negative input threshold, VIT–, the
receiver output, R, turns low. If VID is between VIT+ and VIT– the output is indeterminate.
When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of VID
are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is
disconnected from the bus (open-circuit), the bus lines are shorted (short-circuit), or the bus is not actively driven
(idle bus).
Table 2. Receiver Function Table SN65HVD1470, SN65HVD1473, SN65HVD1476
DIFFERENTIAL INPUT
ENABLE
OUTPUT
FUNCTION
VID = V(A) – V(B)
RE
R
VIT+ < VID
L
H
Receives valid bus High
VIT– < VID < VIT+
L
?
Indeterminate bus state
VID < VIT–
L
L
Receives valid bus Low
X
H
Z
Receiver disabled
X
OPEN
Z
Receiver disabled by default
Open-circuit bus
L
H
Fail-safe high output
Short-circuit bus
L
H
Fail-safe high output
Idle (terminated) bus
L
H
Fail-safe high output
For the SN65HVD1471, HVD1474, and HVD1477, the driver and receiver are fully enabled, thus the differential
outputs Y and Z follow the logic states at data input D at all times. A logic high at D causes Y to turn high and Z
to turn low. In this case the differential output voltage defined as VOD = V(Y) – V(Z) is positive. When D is low, the
output states reverse, Z turns high, Y becomes low, and VOD is negative. The D pin has an internal pullup
resistor to VCC, thus, when left open while the driver is enabled, output Y turns high and Z turns low.
Table 3. Driver Function Table SN65HVD1471, SN65HVD1474, SN65HVD1477
INPUT
OUTPUTS
FUNCTION
D
Y
Z
H
H
L
Actively drives the bus High
L
L
H
Actively drives the bus Low
OPEN
H
L
Actively drives the bus High by default
When the differential input voltage defined as VID = V(A) – V(B) is positive and higher than the positive input
threshold, VIT+, the receiver output, R, turns high. When VID is negative and less than the negative input
threshold, VIT–, the receiver output, R, turns low. If VID is between VIT+ and VIT– the output is indeterminate.
Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is disconnected
from the bus (open-circuit), the bus lines are shorted (short-circuit), or the bus is not actively driven (idle bus).
Table 4. Receiver Function Table SN65HVD1471, SN65HVD1474, SN65HVD1477
18
DIFFERENTIAL INPUT
OUTPUT
VID = V(A) – V(B)
R
VIT+ < VID
H
Receives valid bus High
VIT– < VID < VIT+
?
Indeterminate bus state
VID < VIT–
L
Receives valid bus Low
Open-circuit bus
H
Fail-safe high output
Short-circuit bus
H
Fail-safe high output
Idle (terminated) bus
H
Fail-safe high output
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9.4.1 Equivalent Circuits
VCC
VCC
1M
1.5 k
1.5 k
D, RE
DE
9V
9V
Figure 25. D and RE Inputs
1M
Figure 26. DE Input
VCC
VCC
R2
R2
R1
R
A
R
R1
B
9V
16 V
Figure 27. R Output
R3
R3
Figure 28. Receiver Inputs
VCC
Y
Z
16 V
Figure 29. Driver Outputs
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The SN65HVD147x family consists of full-duplex RS-485 transceivers commonly used for asynchronous data
transmissions. Full-duplex implementation requires two signal pairs (four wires), and allows each node to
transmit data on one pair while simultaneously receiving data on the other pair.
To eliminate line reflections, each cable end is terminated with a termination resistor, R(T), whose value matches
the characteristic impedance, Z0, of the cable. This method, known as parallel termination, allows for higher data
rates over longer cable length.
Y
R
D
Z
A
R(T)
R(T)
B
R
R
DE
RE
Master
Slave
RE
B
D
R
A
DE
Z
R(T)
R(T)
A
B
Z
D
Y
D
Y
R Slave
D
R RE DE D
Figure 30. Typical RS-485 Network With SN65HVD147x Full-Duplex Transceivers
10.2 Typical Application
A full-duplex RS-485 network consists of multiple transceivers connecting in parallel to two bus cables. On one
signal pair, a master driver transmits data to multiple slave receivers. The master driver and slave receivers may
remain fully enabled at all times. On the other signal pair, multiple slave drivers transmit data to the master
receiver. To avoid bus contention, the slave drivers must be intermittently enabled and disabled such that only
one driver is enabled at any time, as in half-duplex communication. The master receiver may remain fully
enabled at all times.
Because the driver may not be disabled, only one driver should be connected to the bus when using the
SN65HVD1471, SN65HVD1474, or SN65HVD1477 device.
Master Enable Control
Slave Enable Control
VCC
R
VCC
A
R
A
R
RE
VCC
R
B
DE
B
RE
DE
D
Z
D
D
Z
D
Y
Y
GND
GND
Figure 31. Full-Duplex Transceiver Configurations
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Typical Application (continued)
10.2.1 Design Requirements
RS-485 is a robust electrical standard suitable for long-distance networking that may be used in a wide range of
applications with varying parameter requirements, such as distance, data rate, and number of nodes.
10.2.1.1 Data Rate and Bus Length
There is an inverse relationship between data rate and cable length, which means the higher the data rate, the
short the cable length; and conversely, the lower the data rate, the longer the cable length. While most RS-485
systems use data rates between 10 kbps and 100 kbps, some applications require data rates up to 250 kbps at
distances of 4000 ft and longer. Longer distances are possible by allowing for small signal jitter of up to 5 or
10%.
10000
Cable Length (ft)
5%, 10%, and 20% Jitter
1000
Conservative
Characteristics
100
10
100
1k
10k
100k
1M
10M
100M
Data Rate (bps)
Figure 32. Cable Length vs Data Rate Characteristic
10.2.1.2 Stub Length
When connecting a node to the bus, the distance between the transceiver inputs and the cable trunk, known as
the stub, should be as short as possible. Stubs present a non-terminated piece of bus line which can introduce
reflections as the length of the stub increases. As a general guideline, the electrical length, or round-trip delay, of
a stub should be less than one-tenth of the rise time of the driver, thus giving a maximum physical stub length as
shown in Equation 1.
L(STUB) ≤ 0.1 × tr × v × c
where
•
•
•
tr is the 10/90 rise time of the driver
v is the signal velocity of the cable or trace as a factor of c
c is the speed of light (3 × 108 m/s)
(1)
Per Equation 1, Table 5 lists the maximum cable-stub lengths for the minimum-driver output rise-times of the
SN65HVD147x full-duplex family of transceivers for a signal velocity of 78%.
Table 5. Maximum Stub Length
DEVICE
MINIMUM DRIVER OUTPUT
RISE TIME (ns)
MAXIMUM STUB LENGTH
(m)
(ft)
SN65HVD1470
100
2.34
7.7
SN65HVD1471
100
2.34
7.7
SN65HVD1473
4
0.1
0.3
SN65HVD1474
4
0.1
0.3
SN65HVD1476
2
0.05
0.15
SN65HVD1477
2
0.05
0.15
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10.2.1.3 Bus Loading
The RS-485 standard specifies that a compliant driver must be able to driver 32 unit loads (UL), where 1 unit
load represents a load impedance of approximately 12 kΩ. Because the SN65HVD147x family consists of 1/8 UL
transceivers, connecting up to 256 receivers to the bus is possible.
10.2.1.4 Receiver Failsafe
The differential receivers of the SN65HVD147x family are failsafe to invalid bus states caused by the following:
• Open bus conditions, such as a disconnected connector
• Shorted bus conditions, such as cable damage shorting the twisted-pair together
• Idle bus conditions that occur when no driver on the bus is actively driving
In any of these cases, the differential receiver will output a failsafe logic high state so that the output of the
receiver is not indeterminate.
Receiver failsafe is accomplished by offsetting the receiver thresholds such that the input indeterminate range
does not include zero volts differential. In order to comply with the RS-422 and RS-485 standards, the receiver
output must output a high when the differential input VID is more positive than 200 mV, and must output a Low
when VID is more negative than –200 mV. The receiver parameters which determine the failsafe performance are
VIT+, VIT–, and Vhys (the separation between VIT+ and VIT–). As shown in the Electrical Characteristics table,
differential signals more negative than –200 mV will always cause a low receiver output, and differential signals
more positive than 200 mV will always cause a high receiver output.
When the differential input signal is close to zero, it is still above the VIT+ threshold, and the receiver output will
be High. Only when the differential input is more than Vhys below VIT+ will the receiver output transition to a Low
state. Therefore, the noise immunity of the receiver inputs during a bus fault conditions includes the receiver
hysteresis value, Vhys, as well as the value of VIT+.
R
Vhysmin
40 mV
±60
±20
0
20
60
VID (mV)
Vnmax = 120 mVpp
Figure 33. SN65HVD147x Noise Immunity Under Bus Fault Conditions
10.2.1.5 Transient Protection
The bus pins of the SN65HVD147x full-duplex transceiver family include on-chip ESD protection against ±30-kV
HBM and ±16-kV IEC 61000-4-2 contact discharge. The International Electrotechnical Commission (IEC) ESD
test is far more severe than the HBM ESD test. The 50% higher charge capacitance, C(S), and 78% lower
discharge resistance, R(D), of the IEC model produce significantly higher discharge currents than the HBM model.
As stated in the IEC 61000-4-2 standard, contact discharge is the preferred transient protection test method.
Although IEC air-gap testing is less repeatable than contact testing, air discharge protection levels are inferred
from contact discharge test results.
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R(C)
R(D)
High-Voltage
Pulse
Generator
330 Ω
(1.5 kΩ)
Device
Under
Test
150 pF
(100 pF)
C(S)
Current (A)
50 M
(1 M)
40
35
30 10-kV IEC
25
20
15
10
5
0
0
50
100
10-kV HBM
150
200
250
300
Time (ns)
Figure 34. HBM and IEC ESD Models and Currents in Comparison (HBM Values in Parenthesis)
The on-chip implementation of IEC ESD protection significantly increases the robustness of equipment. Common
discharge events occur because of human contact with connectors and cables. Designers may choose to
implement protection against longer duration transients, typically referred to as surge transients.
EFTs are generally caused by relay-contact bounce or the interruption of inductive loads. Surge transients often
result from lightning strikes (direct strike or an indirect strike which induce voltages and currents), or the
switching of power systems, including load changes and short circuit switching. These transients are often
encountered in industrial environments, such as factory automation and power-grid systems.
Figure 35 compares the pulse-power of the EFT and surge transients with the power caused by an IEC ESD
transient. The left hand diagram shows the relative pulse-power for a 0.5kV surge transient and 4-kV EFT
transient, both of which dwarf the 10-kV ESD transient visible in the lower-left corner. 500-V surge transients are
representative of events that may occur in factory environments in industrial and process automations.
22
20
18
16
14
12
10
8
6
4
2
0
Pulse Power (MW)
Pulse Power (kW)
The right hand diagram shows the pulse-power of a 6-kV surge transient, relative to the same 0.5-kV surge
transient. 6-kV surge transients are most likely to occur in power generation and power-grid systems.
0.5-kV Surge
4-kV EFT
10-kV ESD
0
5
10
15
20
25
Time (µs)
30
35
40
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
6-kV Surge
0.5-kV Surge
0
5
10
15
20
25
30
35
40
Time (µs)
Figure 35. Power Comparison of ESD, EFT, and Surge Transients
In the case of surge transients, high-energy content is characterized by long pulse duration and slow decaying
pulse power. The electrical energy of a transient that is dumped into the internal protection cells of a transceiver
is converted into thermal energy, which heats and destroys the protection cells, thus destroying the transceiver.
Figure 36 shows the large differences in transient energies for single ESD, EFT, surge transients, and an EFT
pulse train that is commonly applied during compliance testing.
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1000
100
Surge
10
1
Pulse Energy (J)
EFT Pulse Train
0.1
0.01
EFT
10-3
10-4
ESD
10-5
10-6
0.5
1
2
4
6
8 10
15
Peak Pulse Voltage (kV)
Figure 36. Comparison of Transient Energies
10.2.2 Detailed Design Procedure
In order to protect bus nodes against high-energy transients, the implementation of external transient protection
devices is therefore necessary. Figure 37 shows a protection circuit against 16-kV ESD, 4-kV EFT, and 1-kV
surge transients.
3.3 V
100 nF
R1
VCC
10 k
10 k
A
TVS
R
RxD
B
RE
DIR
MCU/
UART
R2
R1
SN65HVD147x
DE
DIR
Z
TVS
D
TxD
Y
10 k
GND
R2
Figure 37. Transient Protection Against ESD, EFT, and Surge transients
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SN65HVD1474, SN65HVD1476, SN65HVD1477
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Table 6. Bill of Materials
DEVICE
FUNCTION
ORDER NUMBER
MANUFACTURER
XCVR
3.3-V, full-duplex RS-485
transceiver
SN65HVD147xD
TI
R1
10-Ω, pulse-proof thick-film
resistor
CRCW0603010RJNEAHP
Vishay
Bidirectional 400-W
transient suppressor
CDSOT23-SM712
Bourns
R2
TVS
10.2.3 Application Curves
D
D
VOD
VOD
R
R
RL = 60 Ω
RL = 60 Ω
Figure 38. SN65HVD1470 and SN65HVD1471, 500 kbps
Figure 39. SN65HVD1473 and SN65HVD1474, 20 Mbps
D
VOD
R
RL = 60 Ω
Figure 40. SN65HVD1476 and SN65HVD1477, 50 Mbps
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11 Power Supply Recommendations
To ensure reliable operation at all data rates and supply voltages, each supply should be buffered with a 100-nF
ceramic capacitor located as close to the supply pins as possible. The TPS76333 is a linear voltage regulator
suitable for the 3.3-V supply.
12 Layout
12.1 Layout Guidelines
On-chip IEC-ESD protection is good for laboratory and portable equipment but never sufficient for EFT and surge
transients occurring in industrial environments. Therefore robust and reliable bus node design requires the use of
external transient protection devices.
Because ESD and EFT transients have a wide frequency bandwidth from approximately 3-MHz to 3-GHz, highfrequency layout techniques must be applied during PCB design.
For successful PCB design, begin with the design of the protection circuit (see Figure 41).
1. Place the protection circuitry close to the bus connector to prevent noise transients from penetrating your
board.
2. Use VCC and ground planes to provide low-inductance. Note that high-frequency currents follow the path of
least inductance and not the path of least impedance.
3. Design the protection components into the direction of the signal path. Do not force the transient currents to
divert from the signal path to reach the protection device.
4. Apply 100-nF to 220-nF bypass capacitors as close as possible to the VCC-pins of transceiver, UART,
controller ICs on the board (see Figure 41).
5. Use at least two vias for VCC and ground connections of bypass capacitors and protection devices to
minimize effective via-inductance (see Figure 41).
6. Use 1-kΩ to 10-kΩ pullup and pulldown resistors for enable lines to limit noise currents in theses lines during
transient events (see Figure 41).
7. Insert pulse-proof resistors into the A and B bus lines if the TVS clamping voltage is higher than the specified
maximum voltage of the transceiver bus pins. These resistors limit the residual clamping current into the
transceiver and prevent it from latching up (see Figure 41).
8. While pure TVS protection is sufficient for surge transients up to 1 kV, higher transients require metal-oxide
varistors (MOVs) which reduce the transients to a few hundred volts of clamping voltage, and transient
blocking units (TBUs) that limit transient current to less than 1 mA.
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SN65HVD1474, SN65HVD1476, SN65HVD1477
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12.2 Layout Example
GND
5
C
4
VCC or GND
7
1
R
MCU
7
SN65HVD147x
R
TVS
5
R
7
R
R
VCC or GND
1
R
GND
7
TVS
JMP
6
R
JMP
R
GND
6
5
GND
GND
Figure 41. SN65HVD147x Layout Example
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13 Device and Documentation Support
13.1 Device Support
13.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 7. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN65HVD1470
Click here
Click here
Click here
Click here
Click here
SN65HVD1471
Click here
Click here
Click here
Click here
Click here
SN65HVD1473
Click here
Click here
Click here
Click here
Click here
SN65HVD1474
Click here
Click here
Click here
Click here
Click here
SN65HVD1476
Click here
Click here
Click here
Click here
Click here
SN65HVD1477
Click here
Click here
Click here
Click here
Click here
13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN65HVD1470D
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
HVD1470
Samples
SN65HVD1470DGS
ACTIVE
VSSOP
DGS
10
80
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1470
Samples
SN65HVD1470DGSR
ACTIVE
VSSOP
DGS
10
2500
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1470
Samples
SN65HVD1470DR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
HVD1470
Samples
SN65HVD1471D
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
VD1471
Samples
SN65HVD1471DGK
ACTIVE
VSSOP
DGK
8
80
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1471
Samples
SN65HVD1471DGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1471
Samples
SN65HVD1471DR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
VD1471
Samples
SN65HVD1473D
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
HVD1473
Samples
SN65HVD1473DGS
ACTIVE
VSSOP
DGS
10
80
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1473
Samples
SN65HVD1473DGSR
ACTIVE
VSSOP
DGS
10
2500
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1473
Samples
SN65HVD1473DR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
HVD1473
Samples
SN65HVD1474D
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
VD1474
Samples
SN65HVD1474DGK
ACTIVE
VSSOP
DGK
8
80
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1474
Samples
SN65HVD1474DGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG | SN
Level-1-260C-UNLIM
-40 to 125
1474
Samples
SN65HVD1474DR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
VD1474
Samples
SN65HVD1476D
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
HVD1476
Samples
SN65HVD1476DGS
ACTIVE
VSSOP
DGS
10
80
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1476
Samples
SN65HVD1476DGSR
ACTIVE
VSSOP
DGS
10
2500
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1476
Samples
SN65HVD1476DR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
HVD1476
Samples
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
14-Oct-2022
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN65HVD1477D
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
VD1477
Samples
SN65HVD1477DGK
ACTIVE
VSSOP
DGK
8
80
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1477
Samples
SN65HVD1477DGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1477
Samples
SN65HVD1477DR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
VD1477
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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