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SN65HVD1780-Q1, SN65HVD1781-Q1, SN65HVD1782-Q1
SLLSE49D – SEPTEMBER 2010 – REVISED JULY 2017
SN65HVD178x-Q1 Fault-Protected RS-485 Transceivers With 3.3-V to 5-V Operation
1 Features
3 Description
•
•
These devices are designed to survive overvoltage
faults such as direct shorts to power supplies, miswiring faults, connector failures, cable crushes, and
tool mis-applications. They are also robust to ESD
events, with high levels of protection to the humanbody-model specification.
1
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results
– Device Temperature Grade 1:
–40°C to 125°C Ambient Operating
Temperature Range
– Device HBM ESD Classification Level H2
– Device CDM ESG Classification Level C3B
Bus-Pin Fault Protection to:
– > ±70 V ('HVD1780-Q1, 'HVD1781-Q1)
– > ±30 V ('HVD1782-Q1)
Operation With 3.3-V to 5-V Supply Range
±16-kV HBM Protection on Bus Pins
Reduced Unit Load for up to 320 Nodes
Failsafe Receiver for Open-Circuit, Short-Circuit
and Idle-Bus Conditions
Low Power Consumption
– Low Standby Supply Current, 1 μA Maximum
– ICC 4-mA Quiescent During Operation
Pin-Compatible With Industry-Standard SN75176
Signaling Rates of 115 kbps, 1 Mbps, and up to
10 Mbps
These devices combine a differential driver and a
differential receiver, which operate from a single
power supply. In the 'HVD1782, the driver differential
outputs and the receiver differential inputs are
connected internally to form a bus port suitable for
half-duplex (two-wire bus) communication. This port
features a wide common-mode voltage range, making
the devices suitable for multipoint applications over
long cable runs. These devices are characterized
from –40°C to 125°C. These devices are pincompatible with the industry-standard SN75176
transceiver, making them drop-in upgrades in most
systems.
These devices are fully compliant with ANSI TIA/EIA
485-A with a 5-V supply and can operate with a 3.3-V
supply with reduced driver output voltage for lowpower applications. For applications where operation
is required over an extended common-mode voltage
range, see the SN65HVD1785 (SLLS872) data sheet.
Device Information(1)
2 Applications
Automotive Data Links
PART NUMBER
SIGNALING RATE
NUMBER OF
NODES
SN65HVD1780-Q1
Up to 115 kbps
Up to 320
SN65HVD1781-Q1
Up to 1 Mbps
Up to 320
SN65HVD1782-Q1
Up to 10 Mbps
Up to 64
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
VFAULT up to 70 V
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
SN65HVD1780-Q1, SN65HVD1781-Q1, SN65HVD1782-Q1
SLLSE49D – SEPTEMBER 2010 – REVISED JULY 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
3
4
4
4
4
5
6
7
7
8
Absolute Maximum Ratings .....................................
ESD Ratings—AEC...................................................
ESD Ratings—IEC ....................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Power Dissipation Ratings ........................................
Switching Characteristics ..........................................
Package Dissipation Ratings ....................................
Typical Characteristics ............................................
Parameter Measurement Information .................. 9
Detailed Description ............................................ 13
8.1 Overview ................................................................. 13
8.2 Functional Block Diagram ....................................... 13
8.3 Feature Description................................................. 13
8.4 Device Functional Modes........................................ 14
9
Application and Implementation ........................ 16
9.1 Application Information............................................ 16
9.2 Typical Application ................................................. 16
10 Power Supply Recommendations ..................... 20
11 Layout................................................................... 20
11.1 Layout Guidelines ................................................. 20
11.2 Layout Example .................................................... 20
12 Device and Documentation Support ................. 21
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
21
21
21
21
21
21
21
13 Mechanical, Packaging, and Orderable
Information ........................................................... 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (April 2016) to Revision D
Page
•
Changed the differential input to receive a valid bus high from VID < VIT+ to VID > VIT+ in the Receiver Function Table..... 15
•
Changed the Half-Duplex Layout Example .......................................................................................................................... 20
•
Added the Receiving Notification of Documentation Updates section ................................................................................. 21
•
Changed the Electrostatic Discharge Caution statement..................................................................................................... 21
Changes from Revision B (January 2016) to Revision C
•
Page
Changed the signaling rate for SN65HVD1780-Q1 from 115 to 0.115 Bin the Recommended Operating Conditions
table ....................................................................................................................................................................................... 4
Changes from Revision A (August 2015) to Revision B
Page
•
Changed HBM and CDM back to the AEC specification and split the IEC specification into a separate table .................... 4
•
Added the SN65HVD1780-Q1 and SN65HVD1782-Q1 devices to the Thermal Information table ....................................... 4
Changes from Original (September 2010) to Revision A
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
•
Added new ListItem in Features, second one with sub list items........................................................................................... 1
2
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Product Folder Links: SN65HVD1780-Q1 SN65HVD1781-Q1 SN65HVD1782-Q1
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SLLSE49D – SEPTEMBER 2010 – REVISED JULY 2017
5 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
R
1
8
V
RE
2
7
B
DE
3
6
A
D
4
5
GND
CC
Pin Functions
PIN
NAME
TYPE
NO.
DESCRIPTION
A
6
Bus I/O
Driver output or receiver input (complementary to B)
B
7
Bus I/O
Driver output or receiver input (complementary to A)
D
4
Digital input
Driver data input
DE
3
Digital input
Driver enable, active high
GND
5
Reference
potential
R
1
RE
2
Digital input
VCC
8
Supply
Local device ground
Digital output Receive data output
Receiver enable, active low
3.15-V-to-5.5-V supply
6 Specifications
6.1 Absolute Maximum Ratings
See Note
VCC
(1)
.
Supply voltage
MAX
UNIT
7
V
'HVD1780-Q1, 'HVD1781Q1
A, B pins
–70
70
'HVD1782-Q1
A, B pins
–70
30
Input voltage range at any logic pin
–0.3
VCC + 0.3
V
Transient overvoltage pulse through 100 Ω per TIA-485
–70
70
V
–24
24
mA
Voltage range at bus pins
Receiver output current
Continuous total power dissipation
TJ
Junction temperature
Tstg
Storage temperature
(1)
MIN
–0.5
V
See Power Dissipation Ratings
–40
170
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Copyright © 2010–2017, Texas Instruments Incorporated
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SLLSE49D – SEPTEMBER 2010 – REVISED JULY 2017
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6.2 ESD Ratings—AEC
VALUE
Human-body model (HBM), per AEC Q100-002 (1)
Electrostatic
discharge
V(ESD)
(1)
Bus terminals and GND
±16000
All pins
±4000
Charged-device model (CDM), per AEC Q100-011
±2000
Machine Model (MM), AEC-Q100-003
±400
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 ESD Ratings—IEC
Electrostatic
discharge
V(ESD)
Human body model (HBM), per IEC 60749-26
Bus terminals and GND
VALUE
UNIT
±16000
V
6.4 Recommended Operating Conditions
MIN
NOM
MAX
3.15
5
VCC
Supply voltage
VI
Input voltage at any bus terminal (separately or common mode) (1)
VIH
High-level input voltage (driver, driver enable, and receiver enable inputs)
VIL
Low-level input voltage (driver, driver enable, and receiver enable inputs)
VID
Differential input voltage
Output current, driver
–60
IO
5.5
V
–7
12
V
2
VCC
V
0
0.8
V
–12
12
V
60
mA
8
mA
Output current, receiver
–8
RL
Differential load resistance
54
CL
Differential load capacitance
60
Ω
50
pF
SN65HVD1780-Q1
1/tUI
Signaling rate
TA
Operating free-air temperature (See the
Thermal Information table)
TJ
Junction Temperature
(1)
UNIT
0.115
SN65HVD1781-Q1
1
SN65HVD1782-Q1
10
5-V supply
–40
105
3.3-V supply
–40
125
–40
150
Mbps
°C
°C
By convention, the least positive (most negative) limit is designated as minimum in this data sheet.
6.5 Thermal Information
SN65HVD1780-Q1
SN65HVD1781-Q1
SN65HVD1782-Q1
THERMAL METRIC (1)
UNIT
D (SOIC)
8 PINS
JEDEC high-K model
138
°C/W
JEDIC low-K model
RθJA
Junction-to-ambient thermal resistance
242
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
61
°C/W
RθJB
Junction-to-board thermal resistance
62
°C/W
ψJT
Junction-to-top characterization parameter
3.8
°C/W
ψJB
Junction-to-board characterization parameter
38.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SN65HVD1780-Q1, SN65HVD1781-Q1, SN65HVD1782-Q1
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SLLSE49D – SEPTEMBER 2010 – REVISED JULY 2017
6.6 Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
|VOD|
Driver differential output voltage magnitude
TEST CONDITIONS
MIN
RL = 60 Ω, 4.75 V ≤ VCC 375 Ω
on each output to –7 V to 12 V,
SeeFigure 6
TA < 85°C
1.5
TA < 125°C
1.4
RL = 54 Ω,
4.75 V ≤ VCC ≤ 5.25 V
TA < 85°C
1.7
TA < 125°C
1.5
RL = 54 Ω,
3.15 V ≤ VCC ≤ 3.45 V
TA < 85°C
RL = 100 Ω,
4.75 V ≤ VCC ≤ 5.25 V
Δ|VOD|
Change in magnitude of driver differential
output voltage
VOC(SS)
Steady-state common-mode output voltage
ΔVOC
Change in differential driver output commonmode voltage
VOC(PP)
Peak-to-peak driver common-mode output
voltage
COD
Differential output capacitance
VIT+
Positive-going receiver differential input
voltage threshold
VIT–
Negative-going receiver differential input
voltage threshold
VHYS
Receiver differential input voltage threshold
hysteresis
(VIT+ – VIT–) (1)
VOH
Receiver high-level output voltage
IOH = –8 mA
VOL
Receiver low-level output voltage
IOL = 8 mA
II(LOGIC)
Driver input, driver enable, and receiver
enable input current
IOZ
Receiver output high-impedance current
IOS
Driver short-circuit output current
II(BUS)
Bus input current (disabled driver)
Supply current (quiescent)
2.5
2
–50
0
50
mV
1
VCC/2
3
V
–50
0
50
mV
(1)
mV
23
pF
mV
mV
30
50
mV
2.4
VCC
– 0.3
0.2
TA < 125°C
VCC = 3.15 to 5.5 V or
VCC = 0 V, DE at 0 V
–35
–150
V
0.4
0.5
V
–50
50
μA
–1
1
μA
–200
200
mA
HVD1780-Q1,
HVD1781-Q1
75
100
HVD1782-Q1
400
500
HVD1780-Q1,
HVD1781-Q1
–60
–40
HVD1782-Q1
-400
-300
Driver and receiver enabled
DE = VCC, RE = GND,
no load
4
6
Driver enabled, receiver
disabled
DE = VCC, RE = VCC,
no load
3
5
Driver disabled, receiver
enabled
DE = GND, RE = GND,
no load
2
4
0.15
1
DE = GND, D = open,
RE = VCC, no load, TA <
Driver and receiver disabled, 85°C
standby mode
DE = GND, D = open,
RE = VCC, no load, TA <
125°C
Supply current (dynamic)
500
–180
TA < 85°C
VI = –7 V
ICC
2.2
–100
VO = 0 V or VCC, RE at VCC
UNIT
V
1
Center of two 27-Ω load resistors,
See Figure 7
VI = 12 V
MAX
2
0.8
TA < 125°C
RL = 54 Ω
TYP
μA
mA
μA
12
See the Typical Characteristics section
Ensured by design. Not production tested.
Copyright © 2010–2017, Texas Instruments Incorporated
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SLLSE49D – SEPTEMBER 2010 – REVISED JULY 2017
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6.7 Power Dissipation Ratings
PARAMETER
PD
TSD
(1)
6
Power dissipation
TEST CONDITIONS
VALUE
VCC = 3.6 V, TJ = 150°C, RL = 300 Ω,
CL = 50 pF (driver), CL = 15 pF (receiver)
3.3-V supply, unterminated (1)
75
VCC = 3.6 V, TJ = 150°C, RL = 100 Ω,
CL = 50 pF (driver), CL = 15 pF (receiver)
3.3-V supply, RS-422 load (1)
95
VCC = 3.6 V, TJ = 150°C, RL = 54 Ω,
CL = 50 pF (driver), CL = 15 pF (receiver)
3.3-V supply, RS-485 load (1)
115
VCC = 5.5 V, TJ = 150°C, RL = 300 Ω,
CL = 50 pF (driver), CL = 15 pF (receiver)
5-V supply, unterminated (1)
290
VCC = 5.5 V, TJ = 150°C, RL = 100 Ω,
CL = 50 pF (driver), CL = 15 pF (receiver)
5-V supply, RS-422 load (1)
320
VCC = 5.5 V, TJ = 150°C, RL = 54 Ω,
CL = 50 pF (driver), CL = 15 pF (receiver)
5-V supply, RS-485 load (1)
400
UNIT
mW
Thermal-shutdown junction temperature
170
°C
Driver and receiver enabled, 50% duty cycle square-wave signal at signaling rate: 1 Mbps.
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SLLSE49D – SEPTEMBER 2010 – REVISED JULY 2017
6.8 Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
3.15 V < VCC < 3.45 V
0.4
1.4
1.8
μs
3.15 V < VCC < 5.5 V
0.4
1.7
2.6
µs
DRIVER (SN65HVD1780)
tr, tf
Driver differential output rise/fall time
RL = 54 Ω,
CL = 50 pF,
See Figure 8
tPHL, tPLH
Driver propagation delay
RL = 54 Ω, CL = 50 pF, See Figure 8
0.8
2
μs
tSK(P)
Driver differential output pulse skew,
|tPHL – tPLH|
RL = 54 Ω, CL = 50 pF, See Figure 8
20
250
ns
tPHZ, tPLZ
Driver disable time
See Figure 9 and Figure 10
0.1
5
μs
Receiver enabled
0.2
3
3
12
tPZH, tPZL
Driver enable time
Receiver disabled
See Figure 9 and
Figure 10
μs
DRIVER (SN65HVD1781)
tr, tf
Driver differential output rise/fall time
RL = 54 Ω, CL = 50 pF, See Figure 8
300
ns
tPHL, tPLH
Driver propagation delay
RL = 54 Ω, CL = 50 pF, See Figure 8
200
ns
tSK(P)
Driver differential output pulse skew,
|tPHL – tPLH|
RL = 54 Ω, CL = 50 pF, See Figure 8
25
ns
tPHZ, tPLZ
Driver disable time
See Figure 9 and Figure 10
tPZH, tPZL
Receiver enabled
Driver enable time
Receiver disabled
50
See Figure 9 and
Figure 10
3
μs
300
ns
10
μs
DRIVER (SN65HVD1782)
All VCC and Temp
50
tr, tf
Driver differential output rise/fall time
RL = 54 Ω,
CL = 50 pF
tPHL, tPLH
Driver propagation delay
RL = 54 Ω, CL = 50 pF, See Figure 8
55
ns
tSK(P)
Driver differential output pulse skew,
|tPHL – tPLH|
RL = 54 Ω, CL = 50 pF, See Figure 8
10
ns
tPHZ, tPLZ
Driver disable time
See Figure 9 and Figure 10
tPZH, tPZL
Receiver enabled
Driver enable time
Receiver disabled
VCC > 4.5V and T < 105°C
16
See Figure 9 and
Figure 10
ns
3
μs
300
ns
9
μs
RECEIVER (ALL DEVICES UNLESS OTHERWISE NOTED)
(1)
tr, tf
Receiver output rise/fall time
tPHL, tPLH
Receiver propagation delay time
tSK(P)
tPLZ, tPHZ
tPZL(1), tPZH(1)
tPZL(2), tPZH(2)
(1)
Receiver output pulse skew,
|tPHL – tPLH|
Receiver disable time
CL = 15 pF,
See Figure 11
CL = 15 pF,
See Figure 11
CL = 15 pF,
See Figure 11
(1)
Receiver enable time
All devices
HVD1780-Q1,
HVD1781-Q1
4
15
100
200
HVD1782-Q1
ns
ns
80
HVD1780-Q1,
HVD1781-Q1
6
HVD1782-Q1
20
ns
5
Driver enabled, See Figure 12
15
100
ns
Driver enabled, See Figure 12
80
300
ns
Driver disabled, See Figure 13
3
9
μs
Ensured by design. Not production tested.
6.9 Package Dissipation Ratings
PACKAGE (1)
SOIC (D) 8-pin
(1)
JEDEC
THERMAL
MODEL
TA < 25°C
RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 85°C
RATING
TA = 105°C
RATING
TA = 125°C
RATING (3.3 V
ONLY)
High-K
905 mW
7.25 mW/°C
470 mW
325 mW
180 mW
Low-K
516 mW
4.1 mW/°C
268 mW
186 mW
103 mW
For the most current package and ordering information, see the Mechanical, Packaging, and Orderable Information section, or see the
TI website at www.ti.com.
Copyright © 2010–2017, Texas Instruments Incorporated
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10
80
0
70
ICC − RMS Supply Current − mA
IO − Driver Output Current − mA
6.10 Typical Characteristics
−10
−20
−30
TA = 25°C
DE at VCC
D at VCC
RL = 54 W
−40
TA = 25°C
RE at VCC
DE at VCC
RL = 54 W
CL = 50 pF
VCC = 5 V
60
50
40
VCC = 3.3 V
30
20
−50
0
1
2
3
4
5
0
6
100 200 300 400 500 600 700 800 900 1000
Signaling Rate − kbps
VCC − Supply Voltage − V
G002
G001
Figure 2. RMS Supply Current vs Signaling Rate
Figure 1. Driver Output Current vs Supply Voltage
4.4
35
30
VCC = 5.5 V
3.6
VCC = 3.3 V
3.2
25
Load = 300 W
2.8
2.4
Rise\Fall Time - (ns)
VOD − Differential Output Voltage − V
4.0
Load = 100 W
2.0
Load = 60 W
1.6
1.2
20
15
VCC = 5 V
10
VCC = 3.3 V
0.8
5
0.4
VCC = 3.15 V
0.0
0
5
10
15
20
25
30
35
40
45
I(diff) − Differential Load Current − mA
0
50
-50
0
50
100
150
Temperature - (°C)
G003
Figure 3. Differential Output Voltage vs Differential Load
Current
Figure 4. SN65HVD1782 Rise and Fall Time
2.5
RL = 50 W,
CL = 50 pF
2.3
VCC = 5.5 V
VOD − Differential Output − V
2.1
VCC = 5 V
1.9
1.7
VCC = 4.5 V
1.5
1.3
VCC = 4 V
VCC = 3.6 V
1.1
VCC = 3.3 V
0.9
VCC = 3 V
0.7
2700
2500
2300
2100
1700
1900
1500
1300
1100
900
700
500
0.5
Transition Time − ns
Figure 5. SN65HVD1780 Differential Output Amplitude and Transition Time vs Supply Voltage
8
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SLLSE49D – SEPTEMBER 2010 – REVISED JULY 2017
7 Parameter Measurement Information
Input generator rate is 100 kbps, 50% duty cycle, rise and fall times less than 6 ns, output impedance 50 Ω.
375 W ±1%
VCC
DE
0 V or 3 V
A
D
VOD
60 W ±1%
B
+
_
–7 V < V(test) < 12 V
375 W ±1%
Copyright © 2016, Texas Instruments Incorporated
Figure 6. Measurement of Driver Differential Output Voltage With Common-Mode Load
VCC
27 W ±1%
DE
Input
A
D
A
VA
B
VB
VOC(PP)
VOC
B
DVOC(SS)
CL = 50 pF ±20%
27 W ±1%
VOC
CL Includes Fixture and
Instrumentation Capacitance
Copyright © 2016, Texas Instruments Incorporated
Figure 7. Measurement of Driver Differential and Common-Mode Output With RS-485 Load
3V
VCC
DE
D
Input
Generator
VI
CL = 50 pF ±20%
A
VOD
50 W
B
RL = 54 W
±1%
CL Includes Fixture
and Instrumentation
Capacitance
VI
50%
50%
tPLH
VOD
tPHL
»2V
90% 90%
0V
10%
0V
10%
tr
» –2 V
tf
Copyright © 2016, Texas Instruments Incorporated
Figure 8. Measurement of Driver Differential Output Rise and Fall Times and Propagation Delays
3V
D
DE
Input
Generator
VI
50 W
A
3V
S1
B
CL = 50 pF ±20%
CL Includes Fixture
and Instrumentation
Capacitance
VO
VI
RL = 110 W
± 1%
50%
50%
tPZH
VO
0V
0.5 V
VOH
90%
50%
tPHZ
»0V
Copyright © 2016, Texas Instruments Incorporated
NOTE: D at 3 V to test non-inverting output, D at 0 V to test inverting output.
Figure 9. Measurement of Driver Enable and Disable Times With Active High Output and Pulldown Load
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Parameter Measurement Information (continued)
3V
A
3V
D
DE
Input
Generator
RL = 110 W
±1%
S1
»3V
VI
VO
50%
50%
0V
B
tPZL
tPLZ
CL = 50 pF ±20%
VI
50 W
»3V
CL Includes Fixture
and Instrumentation
Capacitance
VO
50%
10%
VOL
Copyright © 2016, Texas Instruments Incorporated
NOTE: D at 0 V to test non-inverting output, D at 3 V to test inverting output.
Figure 10. Measurement of Driver Enable and Disable Times With Active-Low Output and Pullup Load
A
Input
Generator
R
VI
50 W
1.5 V
0V
VO
B
CL = 15 pF ±20%
RE
CL Includes Fixture
and Instrumentation
Capacitance
3V
VI
50%
50%
0V
tPLH
VO
tPHL
90% 90%
50%
10%
tr
50%
10%
VOH
VOL
tf
Copyright © 2016, Texas Instruments Incorporated
Figure 11. Measurement of Receiver Output Rise and Fall Times and Propagation Delays
10
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SLLSE49D – SEPTEMBER 2010 – REVISED JULY 2017
Parameter Measurement Information (continued)
3V
VCC
DE
A
0 V or 3 V D
B
RE
Input
Generator
VI
1 kW ± 1%
R VO
S1
CL = 15 pF ±20%
CL Includes Fixture
and Instrumentation
Capacitance
50 W
3V
VI
50%
50%
0V
tPZH(1)
tPHZ
VOH
90%
VO
50%
D at 3 V
S1 to GND
»0V
tPZL(1)
tPLZ
VCC
VO
50%
D at 0 V
S1 to VCC
10%
VOL
Copyright © 2016, Texas Instruments Incorporated
Figure 12. Measurement of Receiver Enable and Disable Times With Driver Enabled
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Parameter Measurement Information (continued)
VCC
A
0 V or 1.5 V
R VO
S1
B
1.5 V or 0 V
RE
Input
Generator
VI
1 kW ± 1%
CL = 15 pF ±20%
CL Includes Fixture
and Instrumentation
Capacitance
50 W
3V
VI
50%
0V
tPZH(2)
VOH
VO
A at 1.5 V
B at 0 V
S1 to GND
50%
GND
tPZL(2)
VCC
VO
50%
VOL
A at 0 V
B at 1.5 V
S1 to VCC
Copyright © 2016, Texas Instruments Incorporated
Figure 13. SN65HVD1781 Measurement of Receiver Enable Times With Driver Disabled
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8 Detailed Description
8.1 Overview
The SN65HVD1780-Q1, SN65HVD1781-Q1, and SN65HVD1782-Q1 devices are half-duplex RS-485
transceivers available in three speed grades suitable for data transmission up to 115 kbps, 1 Mbps, and 10
Mbps.
These devices feature a wide common-mode operating range and bus-pin fault protection up to ±70 V. Each
device has an active-high driver enable and active-low receiver enable. A standby current of less than 1 µA can
be achieved by disabling both driver and receiver.
8.2 Functional Block Diagram
VCC
R
RE
A
B
DE
D
GND
Copyright © 2016, Texas Instruments Incorporated
8.3 Feature Description
Internal ESD protection circuits protect the transceiver bus terminals against ±16-kV Human Body Model (HBM)
electrostatic discharges.
Device operation is specified over a wide temperature range from –40°C to 125°C.
8.3.1 Bus Fault Conditions
The SN65HVD178x-Q1 family of RS-485 transceivers is designed to survive bus pin faults up to ±70 V. The
SN65HVD1782-Q1 device will not survive a bus pin fault with a direct short to voltages above 30 V when all of
the following occurs:
• The device is powered on
• The driver is enabled (DE = HIGH), and one of of the following is true
– D = HIGH AND the bus fault is applied to the A pin
– D = LOW AND the bus fault is applied to the B pin
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Feature Description (continued)
Under other conditions, the device survives shorts to bus pin faults up to ±70 V. Table 1 summarizes the
conditions under which the device may be damaged, and the conditions under which the device will not be
damaged.
Table 1. Bus Fault Conditions for the HVD1782
POWER
DE
D
A
B
OFF
X
X
–70 V < VA < 70 V
–70 V < VB < 70 V
RESULTS
Device survives
ON
LO
X
–70 V < VA < 70 V
–70 V < VB < 70 V
Device survives
ON
HI
L
–70 V < VA < 70 V
–70 V < VB < 30 V
Device survives
ON
HI
L
–70 V < VA < 70 V
30 V < VB
ON
HI
H
–70 V < VA < 30 V
–70 V < VB < 30 V
Device survives
ON
HI
H
30 V < VA
–70 V < VB < 30 V
Damage may occur
Damage may occur
8.3.2 Receiver Failsafe
The SN65HVD178x-Q1 family of half-duplex transceivers provides internal biasing of the receiver input
thresholds in combination with large input-threshold hysteresis. At a positive input threshold of VIT+ = –35 mV
and an input hysteresis of VHYS = 30 mV, the receiver output remains logic high under bus-idle, bus-short, or
open bus conditions in the presence of up to 130-mVPP differential noise without the need for external failsafe
biasing resistors.
8.3.3 Hot-Plugging
These devices are designed to operate in hot swap or hot-pluggable applications. Key features for hot-pluggable
applications are power-up and power-down glitch free operation, default disabled input and output pins, and
receiver failsafe.
As shown in the Functional Block Diagram, an internal power-on reset circuit keeps the driver outputs in a high
impedance state until the supply voltage has reached a level at which the device will reliably operate. This circuit
ensures that no problems occur on the bus pin outputs as the power supply turns on or off.
As shown in Device Functional Modes, the driver and receiver enable inputs (DE and RE) are disabled by
default. This default ensures that the device neither drives the bus nor reports data on the R pin until the
associated controller actively drivers the enable pins.
8.4 Device Functional Modes
When the driver enable pin, DE, is logic high, the differential outputs A and B follow the logic states at data input
D. A logic high at D causes A to turn high and B to turn low. In this case the differential output voltage defined as
VOD = VA – VB is positive. When D is low, the output states reverse, B turns high, A becomes low, and VOD is
negative.
When DE is low, both outputs turn high-impedance. In this condition the logic state at D is irrelevant. The DE pin
has an internal pull-down resistor to ground, thus when left open the driver is disabled (high-impedance) by
default. The D pin has an internal pull-up resistor to VCC, thus, when left open while the driver is enabled, output
A turns high and B turns low.
Table 2. Driver Function Table
14
INPUT
ENABLE
D
DE
A
H
H
H
L
Actively drive bus High
L
H
L
H
Actively drive bus Low
X
L
Z
Z
Driver disabled
X
OPEN
Z
Z
Driver disabled by default
OPEN
H
H
L
Actively drive bus High by default
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OUTPUTS
DRIVER STATE
B
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When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage
defined as VID = VA – VB is positive and higher than the positive input threshold, VIT+, the receiver output, R,
turns high. When VID is negative and lower than the negative input threshold, VIT–, the receiver output, R, turns
low. If VID is between VIT+ and VIT– the output is indeterminate.
When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of VID
are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is
disconnected from the bus (open-circuit), the bus lines are shorted (short-circuit), or the bus is not actively driven
(idle bus).
Table 3. Receiver Function Table
DIFFERENTIAL INPUT
ENABLE
OUTPUT
VID = VA – VB
RE
R
VID > VIT+
L
H
Receive valid bus High
VIT– < VID < VIT+
L
?
Indeterminate bus state
RECEIVER STATE
VID < VIT–
L
L
Receive valid bus Low
X
H
Z
Receiver disabled
X
OPEN
Z
Receiver disabled by default
Open-circuit bus
L
H
Fail-safe high output
Short-circuit bus
L
H
Fail-safe high output
Idle (terminated) bus
L
H
Fail-safe high output
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN65HVD178x-Q1 family of devices is a half-duplex RS-485 transceiver commonly used for asynchronous
data transmissions. The driver and receiver enable pins allow for the configuration of different operating modes.
R
R
R
R
R
R
RE
A
RE
A
RE
A
DE
B
DE
B
DE
B
D
D
D
D
D
D
Copyright © 2016, Texas Instruments Incorporated
Figure 14. Half-Duplex Transceiver Configurations
Using independent enable lines provides the most flexible control as it allows for the driver and the receiver to be
turned on and off individually. While this configuration requires two control lines, it allows for selective listening
into the bus traffic, whether the driver is transmitting data or not.
Combining the enable signals simplifies the interface to the controller by forming a single direction-control signal.
In this configuration, the transceiver operates as a driver when the direction-control line is high, and as a receiver
when the direction-control line is low.
Additionally, only one line is required when connecting the receiver-enable input to ground and controlling only
the driver-enable input. In this configuration, a node not only receives the data from the bus, but also the data it
sends and can verify that the correct data have been transmitted.
9.2 Typical Application
An RS-485 bus consists of multiple transceivers connecting in parallel to a bus cable. To eliminate line
reflections, each cable end is terminated with a termination resistor, RT, whose value matches the characteristic
impedance, Z0, of the cable. This method, known as parallel termination, allows for higher data rates over longer
cable length.
R
R
RE
B
DE
D
R
A
R
A
RT
RT
D
A
B
A
R
DE
D
B
D
R
D
R
RE
B
RE
DE
D
D
R
RE
DE D
Copyright © 2016, Texas Instruments Incorporated
Figure 15. Typical RS-485 Network With Half-Duplex Transceivers
16
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SLLSE49D – SEPTEMBER 2010 – REVISED JULY 2017
Typical Application (continued)
9.2.1 Design Requirements
RS-485 is a robust electrical standard suitable for long-distance networking that may be used in a wide range of
applications with varying requirements, such as distance, data rate, and number of nodes.
9.2.1.1 Data Rate and Bus Length
There is an inverse relationship between data rate and bus length, meaning the higher the data rate, the shorter
the cable length; and conversely, the lower the data rate, the longer the cable may be without introducing data
errors. While most RS-485 systems use data rates between 10 kbps and 100 kbps, some applications require
data rates up to 250 kbps at distances of 4000 feet and longer. Longer distances are possible by allowing for
small signal jitter of up to 5 or 10%.
10000
Cable Length (ft)
5%, 10%, and 20% Jitter
1000
Conservative
Characteristics
100
10
100
1k
10k
100k
1M
10M
100M
Data Rate (bps)
Figure 16. Cable Length vs Data Rate Characteristic
9.2.1.2 Bus Loading
The RS-485 standard specifies that a compliant driver must be able to driver 32 unit loads (UL), where 1 unit
load represents a load impedance of approximately 12 kΩ. Because the SN65HVD7x-Q1 family of devices
consists of 1/10 UL transceivers, it is possible to connect up to 320 receivers to the bus.
9.2.2 Detailed Design Procedure
Although the SN65HVD178x-Q1 family of devices is internally protected against human-body-model ESD strikes
up to 16 kV, additional protection against higher-energy transients can be provided at the application level by
implementing external protection devices.
Figure 17 shows a protection circuit intended to withstand 8-kV IEC ESD (per IEC 61000-4-2) as well as 4-kV
EFT (per IEC 61000-4-4).
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Typical Application (continued)
3.3 V
100 nF
100 nF
VCC
10 k
R1
R
RxD
MCU/
UART
DIR
RE
A
DE
B
TVS
D
TxD
R2
GND
10 k
Copyright © 2016, Texas Instruments Incorporated
Figure 17. RS-485 Transceiver with External Transient Protection
Table 4. Bill of Materials
DEVICE
FUNCTION
ORDER NUMBER
MANUFACTURER
XCVR
RS-485 Transceiver
SN65HVD178x-Q1
TI
R1, R2
10-Ω, Pulse-Proof Thick-Film
Resistor
CRCW0603010RJNEAHP
Vishay
TVS
Bidirectional 600-W Transient
Suppressor
SMBJ43CA
Littlefuse
9.2.2.1 Stub Length
When connecting a node to the bus, the distance between the transceiver inputs and the cable trunk, known as
the stub, should be as short as possible. Stubs present a non-terminated piece of bus line which can introduce
reflections as the length of the stub increases. As a general guideline, the electrical length, or round-trip delay, of
a stub should be less than one-tenth of the rise time of the driver, thus giving a maximum physical stub length as
shown in Equation 1.
Lstub ≤ 0.1 × tr × v × c
where
•
•
•
tr is the 10/90 rise time of the driver
c is the speed of light (3 × 108 m/s)
v is the signal velocity of the cable or trace as a factor of c
(1)
9.2.2.2 Receiver Failsafe
The differential receivers of the SN65HVD178x-Q1 family have receiver input thresholds that are offset so that
receiver output state is known for the following three fault conditions:
• Open bus conditions, such as a disconnected connector
• Shorted bus conditions, such as cable damage shorting the twisted-pair together
• Idle bus conditions that occur when no driver on the bus is actively driving
In any of these cases, the differential receiver will output a failsafe logic High state so that the output of the
receiver is not indeterminate.
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Receiver failsafe is accomplished by offsetting the receiver thresholds such that the input indeterminate range
does not include zero volts differential. In order to comply with the RS-422 and RS-485 standards, the receiver
output must output a High when the differential input VID is more positive than 200 mV, and must output a Low
when VID is more negative than –200 mV. The receiver parameters which determine the failsafe performance are
VIT(+), VIT(–), and VHYS (the separation between VIT(+) and VIT(–)). As shown in the Electrical Characteristics table,
differential signals more negative than –200mV will always cause a Low receiver output, and differential signals
more positive than 200 mV will always cause a High receiver output.
When the differential input signal is close to zero, it is still above the maximum VIT(+) threshold of –35 mV, and
the receiver output will be High. Only when the differential input is more than VHYS below VIT(+) will the receiver
output transition to a Low state. Therefore, the noise immunity of the receiver inputs during a bus fault condition
includes the receiver hysteresis value, VHYS, as well as the value of VIT(+).
R
Vhys (min)
30 mV
-65
-35
0
+65
VID (mV)
Vn max = 130 mVpp
Figure 18. Noise Immunity Under Bus Fault Conditions
9.2.3 Application Curve
SN65HVD1781-Q1 D Input
Differential Output
R Output
1-Mbps Operation
Figure 19. SN65HVD1781-Q1 PRBS Data Pattern
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10 Power Supply Recommendations
To ensure reliable operation at all data rates and supply voltages, each supply should be buffered with a 100-nF
ceramic capacitor located as close to the supply pins as possible. The TPS7A6150-Q1 is a linear voltage
regulator suitable for the 5-V supply.
11 Layout
11.1 Layout Guidelines
On-chip IEC-ESD protection is good for laboratory and portable equipment but often insufficient for EFT and
surge transients occurring in industrial environments. Therefore robust and reliable bus node design requires the
use of external transient protection devices.
Because ESD and EFT transients have a wide frequency bandwidth from approximately 3 MHz to 3 GHz, highfrequency layout techniques must be applied during PCB design.
1. Place the protection circuitry close to the bus connector to prevent noise transients from entering the board.
2. Use VCC and ground planes to provide low-inductance. High-frequency currents follow the path of least
inductance and not the path of least impedance.
3. Design the protection components into the direction of the signal path. Do not force the transient currents to
divert from the signal path to reach the protection device.
4. Apply 100-nF to 220-nF bypass capacitors as close as possible to the VCC pins of the transceiver, UART, or
controller ICs on the board.
5. Use at least two vias for VCC and ground connections of bypass capacitors and protection devices to
minimize effective via inductance.
6. Use 1-kΩ to 10-kΩ pullup and pulldown resistors for enable lines to limit noise currents in these lines during
transient events.
7. While pure TVS protection is sufficient for surge transients up to 1 kV, higher transients require metal-oxide
varistors (MOVs) which reduce the transients to a few hundred volts of clamping voltage, and transient
blocking units (TBUs) that limit transient current to less than 1 mA.
11.2 Layout Example
5
Via to ground
C
R
6
Via to VCC
4
R
JMP
1
R
MCU
5
TVS
6
R
SN65HVD178x
5
Figure 20. Half-Duplex Layout Example
20
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• RS-485 Half-Duplex Evaluation Module
• SN65HVD17xx Fault-Protected RS-485 Transceivers With Extended Common-Mode Range
• TPS7A6xxx-Q1 300-mA 40-V Low-Dropout Regulator With 25-µA Quiescent Current
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2010–2017, Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN65HVD1780QDRQ1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1780Q
SN65HVD1781QDRQ1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1781Q
SN65HVD1782QDRQ1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1782Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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