SN65HVD1794, SN65HVD1795
SN65HVD1796
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SLLS935A – AUGUST 2008 – REVISED AUGUST 2012
70-V Fault-Protected RS-485 Transceiver With Cable Invert
Check for Samples: SN65HVD1794, SN65HVD1795, SN65HVD1796
FEATURES
1
•
•
•
•
•
Bus-Pin Fault Protection to > ±70 V
Cable Invert Function Allows Correction for
Reversed Bus Pins
Common-Mode Voltage Range (–20 V to 25 V)
More Than Doubles TIA/EIA 485 Requirement
Bus I/O Protection
– ±16 kV JEDEC HBM Protection
Reduced Unit Load for Up to 256 Nodes
•
•
•
Failsafe Receiver for Open-Circuit, ShortCircuit and Idle-Bus Conditions
Low Power Consumption
– ICC 5 mA Quiescent During Operation
Power-Up, Power-Down Glitch-Free Operation
APPLICATIONS
•
Designed for RS-485 and RS-422 Networks
DESCRIPTION
These devices are designed to survive overvoltage faults such as direct shorts to power supplies, mis-wiring
faults, connector failures, cable crushes, and tool mis-applications. They are also robust to ESD events, with high
levels of protection to human-body model specifications.
These devices combine a differential driver and a differential receiver, which operate from a single power supply.
The driver differential outputs and the receiver differential inputs are connected internally to for a bus port
suitable for half-duplex (two-wire bus) communication. A cable invert pin (INV) allows active correction of miswires that may occur during installation. Upon detecting communication errors, the user can apply a logic HIGH
to the INV pin, effectively inverting the polarity of the differential bus port, thereby correcting for the reversed bus
wires.
These devices feature a wide common-mode voltage range, making them suitable for multi-point applications
over long cable runs. These devices are characterized from –40°C to 105°C.
INV Input Can Correct
for Crossed Wires
VFAULT up to 70 V
Table 1. PRODUCT SELECTION GUIDE
PART NUMBER
SN65HVD1794
DUPLEX
SIGNALING RATE
NODES
CABLE LENGTH
Half
115 kbps
Up to 256
1500 m
SN65HVD1795
PREVIEW
Half
1 Mbps
Up to 256
150 m
SN65HVD1796
PREVIEW
Half
10 Mbps
Up to 64
50 m
For similar features with 3.3 V supply operation, see the SN65HVD1781 (SLLS877).
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2012, Texas Instruments Incorporated
SN65HVD1794, SN65HVD1795
SN65HVD1796
SLLS935A – AUGUST 2008 – REVISED AUGUST 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DEVICE INFORMATION
D Package
(Top View)
1
R
R
1
8
VCC
INV
2
7
B
DE
3
6
A
2
5
4
D
INV
6
A
4
GND
7
D
B
3
P0066-04
DE
S0311-01
Figure 1. SN65HVD17xx With Inverting Feature to Correct for Miswired Cables
DRIVER FUNCTION TABLE
INPUT
ENABLE
INVERT
D
DE
INV
OUTPUTS
A
H
H
L
H
L
Actively drive normal bus High
L
H
L
L
H
Actively drive normal bus Low
H
H
H
L
H
Actively drive inverted bus High (drive normal bus
Low)
L
H
H
H
L
Actively drive inverted bus Low (drive normal bus
High)
X
L
X
Z
Z
Driver disabled
B
X
OPEN
X
Z
Z
Driver disabled by default
OPEN
H
L
H
L
Actively drive bus High by default
OPEN
H
H
L
H
Actively drive bus Low by default (inverted cable)
RECEIVER FUNCTION TABLE
DIFFERENTIAL INPUT
VID = VA – VB
VIT+ < VID
VIT– < VID < VIT+
VID < VIT–
Open-circuit bus
Short-circuit bus
Idle (terminated) bus
2
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INVERT
OUTPUT
INV
R
L or OPEN
H
Receive valid bus High
H
L
Receive inverted bus Low
X
?
Indeterminate bus state
L or OPEN
L
Receive valid bus Low
H
H
Receive inverted bus High
L or OPEN
H
Fail-safe high output
H
L
Failsafe inverted output
L or OPEN
H
Fail-safe high output
H
L
Failsafe inverted output
L or OPEN
H
Fail-safe high output
H
L
Failsafe inverted output
Copyright © 2008–2012, Texas Instruments Incorporated
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SLLS935A – AUGUST 2008 – REVISED AUGUST 2012
ABSOLUTE MAXIMUM RATINGS (1)
VCC
VALUE
UNIT
Supply voltage
–0.5 to 7
V
Voltage range at A and B pins with respect to GND
–70 to 70
V
Voltage range across A and B pins (differential)
–70 to 70
V
–0.3 to VCC + 0.3
V
Input voltage range at any logic pin
Voltage input range, transient pulse, A and B, through 100 Ω
Receiver output current
TJ
–100 to 100
V
–24 to 24
mA
170
°C
Junction temperature
Continuous total power dissipation
See Dissipation Rating Table
IEC 60749-26 ESD (human-body model), bus terminals and GND
±16
kV
JEDEC Standard 22, Test Method A114 (human-body model), bus terminals and GND
±16
kV
JEDEC Standard 22, Test Method A114 (human-body model), all pins
±4
kV
JEDEC Standard 22, Test Method C101 (charged-device model), all pins
±2
kV
±400
V
JEDEC Standard 22, Test Method A115 (machine model), all pins
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
PACKAGE DISSIPATION RATINGS
PACKAGE
JEDEC THERMAL
MODEL
TA < 25°C
RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 85°C
RATING
TA = 105°C
RATING
High-K
905 mW
7.25 mW/°C
470 mW
325 mW
Low-K
516 mW
4.1 mW/°C
268 mW
186 mW
High-K
2119 mW
16.9 mW/°C
1100 mW
763 mW
Low-K
976 mW
7.8 mW/°C
508 mW
352 mW
SOIC (D) 8-pin
PDIP (P) 8-pin
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
VCC
Supply voltage
4.5
5
5.5
UNIT
V
VI
Input voltage at any bus terminal (separately or common mode) (1)
–20
25
V
VIH
High-level input voltage (driver, driver enable, and invert inputs)
2
VCC
V
VIL
Low-level input voltage (driver, driver enable, and invert inputs)
0
0.8
V
VID
Differential input voltage
–25
25
V
Output current, driver
–60
60
mA
Output current, receiver
–8
8
mA
RL
Differential load resistance
54
CL
Differential load capacitance
IO
50
HVD1794
1/tUI
Signaling rate
Ω
60
pF
115
HVD1795
1
HVD1796
10
kbps
Mbps
TA
Operating free-air temperature (See application section for thermal information)
–40
105
°C
TJ
Junction temperature
–40
150
°C
(1)
By convention, the least positive (most negative) limit is designated as minimum in this data sheet.
Copyright © 2008–2012, Texas Instruments Incorporated
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ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
|VOD|
Driver differential output voltage magnitude
TEST CONDITIONS
RS-485 with
common-mode load,
VCC > 4.75 V, see
Figure 2
MIN
TA ≤ 85°C
1.5
TA ≤ 105°C
1.4
RL = 54 Ω, 4.75 V ≤ VCC ≤ 5.25 V
RL = 100 Ω, 4.75 V ≤ VCC ≤ 5.25 V
TYP
MAX
UNIT
V
1.5
2
2
2.5
–0.2
0
0.2
V
1
VCC/2
3
V
–100
0
100
Δ|VOD|
Change in magnitude of driver differential output
RL = 54 Ω
voltage
VOC(SS)
Steady-state common-mode output voltage
ΔVOC
Change in differential driver output commonmode voltage
VOC(PP)
Peak-to-peak driver common-mode output
voltage
COD
Differential output capacitance
VIT+
Positive-going receiver differential input voltage
threshold
VIT–
Negative-going receiver differential input
voltage threshold
VHYS
Receiver differential input voltage threshold
hysteresis
(VIT+ – VIT–)
VOH
Receiver high-level output voltage
IOH = –8 mA
VOL
Receiver low-level output voltage
IOL = 8 mA
II
Driver input, driver enable, and invert input
current
–100
100
μA
IOS
Driver short-circuit output current
–250
250
mA
Center of two 27-Ω load resistors, See
Figure 3
ICC
Bus input current (disabled driver)
Supply current (quiescent)
Supply current (dynamic)
4
mV
23
pF
VCC = 4.5 to 5.5 V or
VCC = 0 V, DE at 0 V
–10
–150
mV
30
50
mV
2.4
VCC
– 0.3
V
0.2
0.4
TA ≤ 105°C
0.2
0.5
VI = 12 V
VI = –7 V
75
–100
VI = –7 V
V
125
–40
VI = 12 V
96
mV
–200
TA ≤ 85°C
94, 95
II
500
–100
VCM = –20 V to 25 V
mV
500
μA
–400
Driver enabled
DE = 5V
4
6
Driver disabled
DE = GND
2
4
mA
See TYPICAL CHARACTERISTICS section
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SLLS935A – AUGUST 2008 – REVISED AUGUST 2012
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.4
1.7
2.6
μs
0.8
2
μs
20
250
ns
0.1
5
μs
0.2
3
μs
300
ns
200
ns
25
ns
DRIVER (HVD1794)
tr, tf
Driver differential output rise/fall time
tPHL, tPLH
Driver propagation delay
tSK(P)
Driver differential output pulse skew,
|tPHL – tPLH|
tPHZ, tPLZ
Driver disable time
tPZH, tPZL
Driver enable time
RL = 54 Ω, CL = 50 pF, See Figure 4
See Figure 5 and Figure 6
DRIVER (HVD1795)
tr, tf
Driver differential output rise/fall time
tPHL, tPLH
Driver propagation delay
tSK(P)
Driver differential output pulse skew,
|tPHL – tPLH|
tPHZ, tPLZ
Driver disable time
tPZH, tPZL
Driver enable time
50
RL = 54 Ω, CL = 50 pF, See Figure 4
See Figure 5 and Figure 6
3
μs
500
ns
30
ns
50
ns
10
ns
DRIVER (HVD1796)
tr, tf
Driver differential output rise/fall time
tPHL, tPLH
Driver propagation delay
tSK(P)
Driver differential output pulse skew,
|tPHL – tPLH|
tPHZ, tPLZ
Driver disable time
tPZH, tPZL
Driver enable time
3
RL = 54 Ω, CL = 50 pF, See Figure 4
3
μs
500
ns
4
15
ns
100
200
See Figure 5 and Figure 6
RECEIVER (ALL DEVICES UNLESS OTHERWISE NOTED)
tr, tf
Receiver output rise/fall time
tPHL, tPLH
Receiver propagation delay time
tSK(P)
Receiver output pulse skew,
|tPHL – tPLH|
Copyright © 2008–2012, Texas Instruments Incorporated
94, 95
CL = 15 pF, See Figure 7
96
70
94, 95
96
6
20
5
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ns
ns
5
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THERMAL INFORMATION
PARAMETER
TEST CONDITIONS
SOIC-8
RθJA Junction-to-ambient thermal resistance (no airflow)
DIP-8
RθJB Junction-to-board thermal resistance
RθJC Junction-to-case thermal resistance
JEDIC low-K model
242
JEDEC high-K model
59
JEDIC low-K model
128
62
DIP-8
39
SOIC-8
61
DIP-8
61
94
95
Power dissipation
138
SOIC-8
94
PD
VALUE
JEDEC high-K model
VCC = 5.5 V, TJ = 150°C, RL = 300 Ω,
CL = 50 pF (driver), CL = 15 pF (receiver)
5-V supply, unterminated (1)
UNIT
°C/W
°C/W
°C/W
290
VCC = 5.5 V, TJ = 150°C, RL = 100 Ω,
CL = 50 pF (driver), CL = 15 pF (receiver)
5-V supply, RS-422 load (1)
320
mW
96
94
95
VCC = 5.5 V, TJ = 150°C, RL = 54 Ω,
CL = 50 pF (driver), CL = 15 pF (receiver)
5-V supply, RS-485 load (1)
400
96
TSD
(1)
Thermal-shutdown junction temperature
170
°C
Driver enabled, 50% duty cycle square-wave signal at signaling rate: 115 kbps for HVD1794, 1 Mbps for HVD1795, 10 Mbps for
HVD1796
PARAMETER MEASUREMENT INFORMATION
Input generator rate is 100 kbps, 50% duty cycle, rise and fall times less than 6 nsec, output impedance 50 Ω.
375 W ±1%
VCC
DE
0 V or 3 V
D
A
VOD
60 W ±1%
B
+
_
–20 V < V(test) < 25 V
375 W ±1%
S0301-01
Figure 2. Measurement of Driver Differential Output Voltage With Common-Mode Load
VCC
DE
Input
27 W ±1%
A
D
A
VA
B
VB
VOC(PP)
VOC
B
27 W ±1%
CL = 50 pF ±20%
DVOC(SS)
VOC
CL Includes Fixture and
Instrumentation Capacitance
S0302-01
Figure 3. Measurement of Driver Differential and Common-Mode Output With RS-485 Load
6
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SLLS935A – AUGUST 2008 – REVISED AUGUST 2012
PARAMETER MEASUREMENT INFORMATION (continued)
3V
VCC
DE
D
Input
Generator
VI
50 W
CL = 50 pF ±20%
A
VOD
B
RL = 54 W
±1%
CL Includes Fixture
and Instrumentation
Capacitance
VI
50%
50%
tPLH
VOD
tPHL
»2V
90% 90%
0V
10%
0V
10%
tr
» –2 V
tf
Note: VI is solid line when INV = LO,
VI is dashed when INV = HI
Figure 4. Measurement of Driver Differential Output Rise and Fall Times and Propagation Delays
3V
D
DE
Input
Generator
VI
50 W
A
3V
S1
VO
B
CL = 50 pF ±20%
VI
50%
RL = 110 W
± 1%
CL Includes Fixture
and Instrumentation
Capacitance
50%
VO
0V
0.5 V
tPZH
VOH
90%
50%
»0V
tPHZ
S0304-01
NOTE: D at 3 V to test non-inverting output, D at 0 V to test inverting output.
Figure 5. Measurement of Driver Enable and Disable Times With Active High Output and Pulldown Load
3V
A
3V
D
DE
Input
Generator
S1
RL = 110 W
±1%
VO
»3V
VI
50%
50%
0V
B
tPZL
tPLZ
CL = 50 pF ±20%
VI
50 W
CL Includes Fixture
and Instrumentation
Capacitance
»3V
VO
50%
10%
VOL
S0305-01
NOTE: D at 0 V to test non-inverting output, D at 3 V to test inverting output.
Figure 6. Measurement of Driver Enable and Disable Times With Active-Low Output and Pullup Load
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PARAMETER MEASUREMENT INFORMATION (continued)
A
Input
Generator
VO
R
50 W
VI
B
1.5 V
CL = 15 pF ±20%
CL Includes Fixture
and Instrumentation
Capacitance
3V
VI
50%
50%
0V
tPLH
tPHL
90% 90%
VO
50%
10%
50%
10%
tr
VOH
VOL
tf
Note: VI is solid line when INV = LO,
VI is dashed when INV = HI
Figure 7. Measurement of Receiver Output Rise and Fall Times and Propagation Delays
TYPICAL CHARACTERISTICS
DRIVER OUTPUT CURRENT
vs
SUPPLY VOLTAGE
RMS SUPPLY CURRENT
vs
SIGNALING RATE
70
50
ICC − RMS Supply Current − mA
IO − Driver Output Current − mA
60
120
TA = 25°C
DE at VCC
D at VCC
RL = 54 Ω
40
30
20
10
TA = 25°C
RE at VCC
DE at VCC
RL = 54 Ω
CL = 50 pF
VCC = 5 V
100
80
60
0
−10
0.0
40
0.6
1.2
1.8
2.4
3.0
3.6
VCC − Supply Voltage − V
Figure 8.
8
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4.2
4.8
5.4
G001
0
2
4
6
8
10
Signaling Rate − Mbps
G002
Figure 9.
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SLLS935A – AUGUST 2008 – REVISED AUGUST 2012
TYPICAL CHARACTERISTICS (continued)
BUS PIN CURRENT
vs
BUS PIN VOLTAGE
2.0
IIN − Bus Pin Current − mA
1.5
1.0
0.5
0.0
−0.5
−1.0
−1.5
−2.0
−90
−60
−30
0
30
60
90
VIN − Bus Pin Voltage − V
G004
Figure 10.
VOD - Differential Output Voltage - V
DIFFERENTIAL OUTPUT VOLTAGE
vs
DIFFERENTIAL LOAD CURRENT
4.4
4.2
4
3.8
3.6
3.4
3.2
3
2.8
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
Load = 100 W
Load = 300 W
VCC = 5.5 V
VCC = 5 V
Load = 60 W
VCC = 4.5 V
0 2 4
6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50
Idiff - Differential Load Current - mA
Figure 11.
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ADDITIONAL OPTIONS
The SN65HVD17xx family also has options for J1708 applications, for always-enabled full-duplex versions
(industry-standard SN65LBC179 footprint) and for inverting-polarity versions, which allow users to correct a
reversal of the bus wires without re-wiring. Contact your local Texas Instruments representative for information
on these options.
PART NUMBER
SN65HVD17xx
FOOTPRINT/FUNCTION
SLOW
MEDIUM
FAST
Half-duplex (176 pinout)
85
86
87
Full-duplex no enables (179 pinout)
88
89
90
Full-duplex with enables (180 pinout)
91
92
93
Half-duplex with cable invert
94
95
96
Full-duplex with cable invert and enables
97
98
99
J1708
08
09
10
D Package
(Top View)
R
1
R
VCC
8
1
2
RE
RE
2
7
B
DE
3
6
A
6
A
4
5
4
D
GND
D
7
B
P0066-03
3
DE
S0309-01
Figure 12. SN65HVD1708E Transceiver for J1708 Applications
5
PW Package
(Top View)
D
VCC
R
D
Y
3
1
8
A
2
7
B
3
6
Z
6
Z
8
A
2
GND
4
5
Y
R
7
B
P0074-01
S0310-01
Figure 13. SN65HVD17xx Always-Enabled Driver Receiver
10
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APPLICATION INFORMATION
Hot-Plugging
These devices are designed to operate in "hot swap" or "hot pluggable" applications. Key features for hotpluggable applications are power-up, power-down glitch free operation, default disabled input/output pins, and
receiver failsafe. As shown in Figure 8, an internal Power-On Reset circuit keeps the driver outputs in a highimpedance state until the supply voltage has reached a level at which the device will reliably operate. This
ensures that no spurious transitions (glitches) will occur on the bus pin outputs as the power supply turns on or
turns off.
As shown in the device FUNCTION TABLE, the ENABLE inputs have the feature of default disable on both the
driver enable and receiver enable. This ensures that the device will neither drive the bus nor report data on the R
pin until the associated controller actively drives the enable pins.
Likewise, the receiver output is "failsafe" to open-circuit, short-circuit, or idle (terminated only) bus conditions.
This eliminates false transitions on the receiver output until a valid RS-485 signal is applied to the receiver input
pins.
Cable Invert
For many RS-485 applications, wiring of data cables takes place during equipment installation, and the possibility
of miss-wiring is a significant issue. When the twisted-pair wires are reversed due to installation mistakes, normal
RS-485 communication is not possible. The Cable Invert (INV) pin allows designers to compensate for this
installation mistake. Under normal circumstances, the INV pin can be set to logic LOW, and the transceiver
operates with normal polarity. If, after initial network start-up, a node cannot communicate properly, the local
controller can set the INV pin high, which will invert the polarity of the A and B differential bus pins. This will
compensate for a reversal of the bus wires, allowing proper communication.
Receiver Failsafe
The differential receiver is “failsafe” to invalid bus states caused by open bus conditions such as a disconnected
connector, shorted bus conditions such as cable damage shorting the twisted-pair together or idle bus conditions
that occur when no driver is actively driving a valid RS-485 bus state on the network. In any of these cases, the
differential receiver outputs a failsafe state, so that small noise signals do not cause spurious transitions at the
receiver output. When INV is logic Low or Open (normal operation), the receiver output will be failsafe High.
When INV is logic High to correct for a twisted-pair reversal, the receiver output will be failsafe Low under those
fault conditions.
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Changes from Original (August 2008) to Revision A
•
12
Page
Added Voltage range across A and B pins (differential) in Absolute Maximum Ratings table ............................................. 3
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Product Folder Links: SN65HVD1794, SN65HVD1795 SN65HVD1796
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Sep-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
B0 W
Reel
Diameter
Cavity
A0
B0
K0
W
P1
A0
Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
SN65HVD1794DR
Package Package Pins
Type Drawing
SOIC
D
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
6.4
B0
(mm)
K0
(mm)
P1
(mm)
5.2
2.1
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Sep-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN65HVD1794DR
SOIC
D
8
2500
356.0
356.0
35.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Sep-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name
Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
SN65HVD1794D
D
SOIC
8
75
506.6
8
3940
4.32
Pack Materials-Page 3
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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