SN65HVD21AD

SN65HVD21A www.ti.com SLLSE36 – DECEMBER 2010 6 Mbps, Extended Common-Mode RS-485 Transceiver Check for Samples: SN65HVD21A FEATURES 1 • • • • • • DESCRIPTION Common-Mode Voltage Range (–20 V to 25 V) More Than Doubles TIA/EIA-485 Requirement Reduced Unit-Load for up to 256 Nodes Bus I/O Protection to Over 16-kV HBM Failsafe Receiver for Open-Circuit, Short-Circuit and Idle-Bus Conditions Low Standby Supply Current 1-µA Max More Than 100 mV Receiver Hysteresis The SN65HVD21A offers performance far exceeding typical RS−485 devices. In addition to meeting all requirements of the TIA/EIA−485−A standard, the device operates over an extended range of common-mode voltage, and has features such as high ESD protection, wide receiver hysteresis, and failsafe operation. This device is ideally suited for long-cable networks, and other applications where the environment is too harsh for ordinary transceivers. APPLICATIONS • • The device is designed for bidirectional data transmission on multipoint twisted-pair cables. Example applications are digital motor controllers, remote sensors and terminals, industrial process control, security stations, and environmental control systems. Long Cable Solutions – Factory Automation – Security Networks – Building HVAC Severe Electrical Environments – Electrical Power Inverters – Industrial Drives – Avionics The device combines a 3-state differential driver and a differential receiver, which operate from a single 5-V power supply. The driver differential outputs and the receiver differential inputs are connected internally to form a differential bus port that offers minimum loading to the bus. This port features an extended common-mode voltage range making the device suitable for multipoint applications over long cable runs. Device Operates Over a Wider Common-Mode Voltage Range -20 V +25 V SUPER485 RS485 -7 V -20 V -15 V -10 V +12 V -5 V 0 5V 10 V 15 V 20 V 25 V 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated SN65HVD21A SLLSE36 – DECEMBER 2010 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) The SN65HVD21A allows up to 256 connected nodes at moderate data rates (up to 6 Mbps). The driver output slew rate is controlled to provide reliable switching with shaped transitions which reduce high-frequency noise emissions. The receivers also include a failsafe circuit that provides a high-level output within 250 microseconds after loss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines, or the absence of any active transmitters on the bus. This feature prevents noise from being received as valid data under these fault conditions. This feature may also be used for Wired-Or bus signaling. The SN65HVD21A is characterized for operation over the temperature range of –40°C to 85°C. PRODUCT SELECTION GUIDE PART NUMBERS SN65HVD21A (1) CABLE LENGTH AND SIGNALING RATE (1) Up to 150 m at 5 Mbps (with slew rate limit) NODES MARKING Up to 256 D: VP21A Distance and signaling rate predictions based upon Belden 3105A cable and 15% eye pattern jitter. AVAILABLE OPTIONS PLASTIC SMALL-OUTLINE (1) D−PACKAGE (JEDEC MS-012) SN65HVD21AD (1) Add R suffix for taped and reeled carriers. Table 1. DRIVER FUNCTION TABLE INPUT D ENABLE DE A OUTPUTS B H L X X OPEN H H L OPEN H H L Z Z H L H Z Z L H = high level, L= low level, X = don’t care, Z = high impedance (off), ? = indeterminate Table 2. RECEIVER FUNCTION TABLE DIFFERENTIAL INPUT VID = (VA – VB) ENABLE RE OUTPUT R 0.2 V ≤ VID L H –0.2 V < VID < 0.2 V L VID ≤ –0.2 V L L X H Z H (see Note X OPEN Z Open circuit L H Short Circuit L H Idle (terminated) bus L H (1) ) H = high level, L= low level, Z = high impedance (off) (1) 2 If the differential input VID remains within the transition range for more than 250 µs, the integrated failsafe circuitry detects a bus fault, and set the receiver output to a high state. See Figure 15. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD21A SN65HVD21A www.ti.com SLLSE36 – DECEMBER 2010 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) SN65HVD2X Supply voltage (2), VCC –0.5 V to 7 V Voltage at any bus I/O terminal –27 V to 27 V Voltage input, transient pulse, A and B, (through 100 Ω, see Figure 16) –60 V to 60 V Voltage input at any D, DE or RE terminal –0.5 V to VCC+ 0.5 V Receiver output current, IO –10 mA to 10 mA Human Body Model (3) Electrostatic discharge A, B, GND 16 kV All pins 5 kV Charged-Device Model (4) All pins 1.5 kV Machine Model (5) All pins 200 V Continuous total power dissipation See Thermal Table Junction temperature, TJ (1) (2) (3) (4) (5) 150°C Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. Tested in accordance with JEDEC Standard 22, Test Method A114-A. Tested in accordance with JEDEC Standard 22, Test Method C101. Tested in accordance with JEDEC Standard 22, Test Method A115-A RECOMMENDED OPERATING CONDITIONS MIN NOM MAX 4.5 5 5.5 V −20 25 V 2 VCC 0 0.8 −25 25 −110 110 −8 8 Operating free-air temperature, TA (1) −40 85 °C Junction temperature, TJ −40 130 °C Supply voltage, VCC Voltage at any bus I/O terminal High-level input voltage, VIH Low-level input voltage, VIL Differential input voltage, VID Output current (1) A, B D, DE, RE A with respect to B Driver Receiver UNIT V V mA Maximum free-air temperature operation is allowed as long as the device recommended junction temperature is not exceeded. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD21A 3 SN65HVD21A SLLSE36 – DECEMBER 2010 www.ti.com DRIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions PARAMETER VIK Input clamp voltage II = −18 mA VO Open-circuit output voltage A or B, No load |VOD(SS)| Steady-state differential output voltage MIN TYP (1) –1.5 0.75 TEST CONDITIONS 0 MAX V VCC No load (open circuit) 3.3 4.2 RL = 54 Ω, See Figure 1 1.8 2.5 With common-mode loading, See Figure 2 1.8 UNIT V VCC V Δ|VOD(SS)| Change in steady-state differential output voltage between logic states See Figure 1 and Figure 3 VOC(SS) Steady-state common-mode output voltage See Figure 1 ∆VOC(SS) Change in steady-state common-mode output voltage, VOC(H) – VOC(L) See Figure 1 and Figure 4 –0.1 VOC(PP) Peak-to-peak common-mode output voltage, VOC(MAX) – VOC(MIN) RL = 54 Ω, CL = 50 pF, See Figure 1 and Figure 4 0.35 VOD(RING) Differential output voltage over and under shoot RL = 54 Ω, CL = 50 pF, See Figure 5 II Input current D, DE –100 100 IO Output current with power off. High impedance state output current. VO < = -7 V to 12 V, Other input = 0 V -100 125 VO < = -20 V to 25 V, Other input = 0 V -200 250 IOS Short-circuit output current VO = –20 V to 25 V, See Figure 9 –250 250 mA COD Differential output capacitance 20 pF (1) –0.1 2.1 2.5 0.1 V 2.9 V 0.1 V V 10% µA µA All typical values are at VCC = 5 V and 25°C. DRIVER SWITCHING CHARACTERISTICS over recommended operating conditions PARAMETER Differential output propagation delay, low-to-high tPHL Differential output propagation delay, high-to-low tr Differential output rise time tf Differential output fall time tPZH Propagation delay time, high-impedance-to-high-level output tPHZ Propagation delay time, high-level output-to-high-impedance tPZL Propagation delay time, high-impedance-to-high-level output tPLZ Propagation delay time, high-level output-to-high-impedance td(standby) Time from an active differential output to standby td(wake) Wake-up time from standby to an active differential output tsk(p ) Pulse skew | tPLH – tPHL| (1) 4 MIN TYP (1) MAX RL = 54 Ω, CL = 50 pF, See Figure 3 20 32 60 ns RL = 54 Ω, CL = 50 pF, See Figure 3 20 40 50 ns RE at 0 V, See Figure 6 100 ns RE at 0 V, See Figure 7 100 ns 2 µs 8 µs 6 ns TEST CONDITIONS tPLH RE at VCC, See Figure 8 UNIT All typical values are at VCC = 5 V and 25°C Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD21A SN65HVD21A www.ti.com SLLSE36 – DECEMBER 2010 RECEIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions PARAMETER TEST CONDITIONS VIT(+) Positive-going differential input voltage threshold VIT(–) Negative-going differential input voltage threshold VHYS Hysteresis voltage (VIT+ – VIT–) See Figure 10 TYP (1) MAX 60 200 VO = 2.4 V, IO = –8 mA VO = 0.4 V, IO = 8 mA VCM = −7 V to 12 V VIT(F+) Positive-going differential input failsafe voltage threshold See Figure 15 VIT(F–) Negative-going differential input failsafe voltage threshold See Figure 15 VIK Input clamp voltage II = –18 mA VOH High-level output voltage VID = 200 mV, IOH = −8 mA, See Figure 11 VOL Low-level output voltage VID = –200 mV, IOL = 8 mA, See Figure 11 II(BUS) Bus input current (power on or power off) II Input current RI Input resistance CID Differential input capacitance (1) MIN –200 –60 100 130 40 120 200 120 250 −40 VCM = −20 V to 25 V VCM = −7 V to 12 V –200 –120 VCM = −20 V to 25 V –250 –120 UNIT mV mV mV mV –1.5 V 4 V 0.4 VI = –7 to 12 V, Other input = 0 V –100 125 VI = −20 to 25 V, Other input = 0 V –200 250 RE –100 100 V µA µA 96 kΩ VID = 0.5 + 0.4 sine (2p × 1.5 × 106t) 20 pF All typical values are at 25°C. RECEIVER SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS tPLH Propagation delay time, low-to-high level output tPHL Propagation delay time high-to low level output tr Receiver output rise time tf Receiver output fall time tPZH Receiver output enable time to high level tPHZ Receiver output disable time from high level tPZL Receiver output enable time to low level tPLZ Receiver output disable time from low level tr(standby) Time from an active receiver output to standby tr(wake) Wake-up time from standby to an active receiver output tsk(p) Pulse skew |tPLH – tPHL| tp(set) Delay time, bus fail to failsafe set tp(reset) Delay time, bus recovery to failsafe reset MIN TYP MAX See Figure 11 25 50 ns See Figure 11 2 4 ns 90 120 ns 16 35 90 120 16 35 See Figure 12 See Figure 13 UNIT ns 2 See Figure 14, DE at 0 V µs 8 5 250 See Figure 15, pulse rate = 1 kHz 350 µs 50 ns SUPPLY CURRENT over recommended operating conditions (unless otherwise noted) PARAMETER ICC Supply current TEST CONDITIONS MIN TYP MAX UNIT Driver enabled (DE at VCC), Receiver enabled (RE at 0 V), No load, VI = 0 V or VCC 8 12 mA Driver enabled (DE at VCC), Receiver disabled (RE at VCC), No load, VI = 0 V or VCC 7 11 mA Driver disabled (DE at 0 V), Receiver enabled (RE at 0 V), No load 5 8 mA 1 µA Driver disabled (DE at 0 V), Receiver disabled (RE at VCC) D open Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD21A 5 SN65HVD21A SLLSE36 – DECEMBER 2010 www.ti.com EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS RE Inputs D Input DE Input VCC VCC 100 kΩ 1 kΩ 1 kΩ Input Input 100 kΩ 9V 9V A Input B Input VCC VCC R1 R3 R1 R3 Input Input 29 V R2 29 V 29 V A and B Outputs R2 R Output VCC VCC 5Ω Output Output 9V 29 V 6 R1/R2 R3 36 kΩ 180 kΩ Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD21A SN65HVD21A www.ti.com SLLSE36 – DECEMBER 2010 PARAMETER MEASUREMENT INFORMATION NOTE: Test load capacitance includes probe and jig capacitance (unless otherwise specified). Signal generator characteristics: rise and fall time