SN65HVD230
SN65HVD231
SN65HVD232
SLOS346K – MARCH 2001 – REVISED FEBRUARY 2011
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3.3-V CAN TRANSCEIVERS
Check for Samples: SN65HVD230, SN65HVD231, SN65HVD232
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
1
2
•
•
•
•
•
•
•
•
•
•
•
(1)
Operates With a 3.3-V Supply
Low Power Replacement for the PCA82C250
Footprint
Bus/Pin ESD Protection Exceeds 16 kV HBM
High Input Impedance Allows for 120 Nodes on
a Bus
Controlled Driver Output Transition Times for
Improved Signal Quality on the SN65HVD230
and SN65HVD231
Unpowered Node Does Not Disturb the Bus
Compatible With the Requirements of the ISO
11898 Standard
Low-Current SN65HVD230 Standby Mode
370 μA Typical
Low-Current SN65HVD231 Sleep Mode 40 nA
Typical
Designed for Signaling Rates(1) up to 1
Megabit/Second (Mbps)
Thermal Shutdown Protection
Open-Circuit Fail-Safe Design
Glitch-Free Power-Up and Power-Down
Protection for Hot-Plugging Applications
Motor Control
Industrial Automation
Basestation Control and Status
Robotics
Automotive
UPS Control
SN65HVD230D (Marked as VP230)
SN65HVD231D (Marked as VP231)
(TOP VIEW)
D
GND
VCC
R
1
8
2
7
3
6
4
5
RS
CANH
CANL
Vref
SN65HVD232D (Marked as VP232)
(TOP VIEW)
D
GND
VCC
R
1
8
2
7
3
6
4
5
NC
CANH
CANL
NC
NC – No internal connection
The signaling rate of a line is the number of voltage
transitions that are made per second expressed in the units
bps (bits per second).
LOGIC DIAGRAM (POSITIVE LOGIC)
SN65HVD230, SN65HVD231
Logic Diagram (Positive Logic)
VCC
3
5
SN65HVD232
Logic Diagram (Positive Logic)
Vref
D
D
RS
R
1
1
8
4
R
7
6
4
7
6
CANH
CANL
CANH
CANL
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TMS320Lx240x is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
© 2001–2011, Texas Instruments Incorporated
SN65HVD230
SN65HVD231
SN65HVD232
SLOS346K – MARCH 2001 – REVISED FEBRUARY 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION
The SN65HVD230, SN65HVD231, and SN65HVD232 controller area network (CAN) transceivers are designed
for use with the Texas Instruments TMS320Lx240x™
; 3.3-V DSPs with CAN controllers, or with
equivalent devices. They are intended for use in applications employing the CAN serial communication physical
layer in accordance with the ISO 11898 standard. Each CAN transceiver is designed to provide differential
transmit capability to the bus and differential receive capability to a CAN controller at speeds up to 1 Mbps.
Designed for operation in especially-harsh environments, these devices feature cross-wire protection,
loss-of-ground and overvoltage protection, overtemperature protection, as well as wide common-mode range.
The transceiver interfaces the single-ended CAN controller with the differential CAN bus found in industrial,
building automation, and automotive applications. It operates over a -2-V to 7-V common-mode range on the
bus, and it can withstand common-mode transients of ±25 V.
On the SN65HVD230 and SN65HVD231, pin 8 provides three different modes of operation: high-speed, slope
control, and low-power modes. The high-speed mode of operation is selected by connecting pin 8 to ground,
allowing the transmitter output transistors to switch on and off as fast as possible with no limitation on the rise
and fall slopes. The rise and fall slopes can be adjusted by connecting a resistor to ground at pin 8, since the
slope is proportional to the pin's output current. This slope control is implemented with external resistor values of
10 kΩ, to achieve a 15-V/μs slew rate, to 100 kΩ, to achieve a 2-V/μs slew rate. See the Application Information
section of this data sheet.
The circuit of the SN65HVD230 enters a low-current standby mode during which the driver is switched off and
the receiver remains active if a high logic level is applied to pin 8. The DSP controller reverses this low-current
standby mode when a dominant state (bus differential voltage > 900 mV typical) occurs on the bus.
The unique difference between the SN65HVD230 and the SN65HVD231 is that both the driver and the receiver
are switched off in the SN65HVD231 when a high logic level is applied to pin 8 and remain in this sleep mode
until the circuit is reactivated by a low logic level on pin 8.
The Vref pin 5 on the SN65HVD230 and SN65HVD231 is available as a VCC/2 voltage reference.
The SN65HVD232 is a basic CAN transceiver with no added options; pins 5 and 8 are NC, no connection.
Table 1. AVAILABLE OPTIONS (1)
PART NUMBER
LOW POWER MODE
INTEGRATED SLOPE
CONTROL
Vref PIN
SN65HVD230
Standby mode
Yes
Yes
SN65HVD231
Sleep mode
Yes
Yes
SN65HVD232
No standby or sleep
mode
No
No
(1)
TA
MARKED AS:
VP230
40°C to 85°C
VP231
VP232
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
FUNCTION TABLES
DRIVER (SN65HVD230, SN65HVD231) (1)
INPUT D
L
H
(1)
2
RS
V(Rs) < 1.2 V
OUTPUTS
BUS STATE
CANH
CANL
H
L
Dominant
Z
Z
Recessive
Open
X
Z
Z
Recessive
X
V(Rs) > 0.75 VCC
Z
Z
Recessive
H = high level; L = low level; X = irrelevant; ? = indeterminate; Z = high impedance
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Table 2.
DRIVER (SN65HVD232) (1)
OUTPUTS
INPUT D
(1)
CANH
BUS STATE
CANL
L
H
L
Dominant
H
Z
Z
Recessive
Open
Z
Z
Recessive
H = high level; L = low level; Z = high impedance
Table 3.
RECEIVER (SN65HVD230) (1)
(1)
DIFFERENTIAL INPUTS
RS
OUTPUT R
L
VID ≥ 0.9 V
X
0.5 V < VID < 0.9 V
X
?
VID ≤ 0.5 V
X
H
Open
X
H
H = high level; L = low level; X = irrelevant; ? = indeterminate
Table 4.
RECEIVER (SN65HVD231) (1)
DIFFERENTIAL INPUTS
RS
OUTPUT R
VID ≥ 0.9 V
L
0.5 V < VID < 0.9 V
V(Rs) < 1.2 V
?
VID ≤ 0.5 V
(1)
H
X
V(Rs) > 0.75 VCC
X
1.2 V < V(Rs) < 0.75 VCC
?
Open
X
H
H
H = high level; L = low level; X = irrelevant; ? = indeterminate
Table 5.
RECEIVER (SN65HVD232) (1)
(1)
DIFFERENTIAL INPUTS
OUTPUT R
VID ≥ 0.9 V
L
0.5 V < VID < 0.9 V
?
VID ≤ 0.5 V
H
Open
H
H = high level; L = low level; X = irrelevant; ? = indeterminate
Table 6.
TRANSCEIVER MODES (SN65HVD230, SN65HVD231)
V(Rs)
OPERATING MODE
V(Rs) > 0.75 VCC
Standby
10 kΩ to 100 kΩ to ground
Slope control
V(Rs) < 1 V
High speed (no slope control)
© 2001–2011, Texas Instruments Incorporated
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TERMINAL FUNCTIONS
TERMINAL
NAME
DESCRIPTION
NO.
SN65HVD230, SN65HVD231
CANL
6
Low bus output
CANH
7
High bus output
D
1
Driver input
GND
2
Ground
R
4
Receiver output
RS
8
Standby/slope control
VCC
3
Supply voltage
Vref
5
Reference output
CANL
6
Low bus output
CANH
7
High bus output
D
1
Driver input
GND
2
Ground
SN65HVD232
NC
5, 8
No connection
R
4
Receiver output
VCC
3
Supply voltage
4
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EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
CANH and CANL Inputs
D Input
VCC
VCC
110 kΩ
16 V
9 kΩ
100 kΩ
45 kΩ
Input
1 kΩ
Input
20 V
9 kΩ
9V
CANH and CANL Outputs
R Output
VCC
VCC
16 V
5Ω
Output
Output
9V
20 V
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
(2)
UNIT
Supply voltage range, VCC
-0.3 V to 6 V
Voltage range at any bus terminal (CANH or CANL)
-4 V to 16 V
Voltage input range, transient pulse, CANH and CANL, through 100 Ω (see Figure 7)
-25 V to 25 V
Input voltage range, VI (D or R)
-0.5 V to VCC + 0.5 V
±11 mA
Receiver output current, IO
Human body model (3)
Electrostatic discharge
Charged-device model
(4)
CANH, CANL and GND
16 kV
All Pins
4 kV
All pins
1 kV
Continuous total power dissipation
(1)
(2)
(3)
(4)
See the Thermal Information Table
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods amy affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
Tested in accordance with JEDEC Standard 22, Test Method A114-A.
Tested in accordance with JEDEC Standard 22, Test Method C101.
THERMAL INFORMATION
THERMAL METRIC (1)
SN65HVD230
SN65HVD231
SN65HVD232
D (8 Pins)
D (8 Pins)
D (8 Pins)
θJA
Junction-to-ambient thermal resistance
76.8
101.5
101.5
θJCtop
Junction-to-case (top) thermal resistance
33.4
43.3
43.3
θJB
Junction-to-board thermal resistance
15.3
42.2
42.4
ψJT
Junction-to-top characterization parameter
1.4
4.8
4.8
ψJB
Junction-to-board characterization parameter
14.9
41.8
41.8
θJCbot
Junction-to-case (bottom) thermal resistance
n/a
n/a
n/a
(1)
UNITS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX UNIT
Supply voltage, VCC
3.6
V
Voltage at any bus terminal (common mode) VIC
-2
(1)
3
7
V
Voltage at any bus terminal (separately) VI
-2.5
7.5
V
High-level input voltage, VIH
D, R
Low-level input voltage, VIL
D, R
2
Differential input voltage, VID (see Figure 5)
Input voltage, V(Rs)
Input voltage for standby or sleep, V(Rs)
Wave-shaping resistance, Rs
Driver
High-level output current, IOH
6
V
6
V
0
VCC
V
0.75 VCC
VCC
V
0
100
kΩ
mA
-8
Driver
48
Receiver
8
Operating free-air temperature, TA
(1)
0.8
-6
-40
Receiver
Low-level output current, IOL
V
-40
85
mA
°C
The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
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DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TYP (1)
MIN
MAX
Dominant
VI = 0 V,
See Figure 1 and Figure 3
CANH
2.45
VCC
CANL
0.5
1.25
VOL
Recessive
VI = 3 V,
See Figure 1 and Figure 3
CANH
2.3
CANL
2.3
VOD(D)
Dominant
VOH
Bus output
voltage
Differential
output voltage
VOD(R)
Recessive
VI = 0 V,
See Figure 1
1.5
2
3
VI = 0 V,
See Figure 2
1.2
2
3
VI = 3 V,
See Figure 1
-120
0
12
VI = 3 V,
No load
-0.5
-0.2
0.05
UNIT
V
V
mV
V
IIH
High-level input current
VI = 2 V
-30
μA
IIL
Low-level input current
VI = 0.8 V
-30
μA
IOS
Short-circuit output current
Co
Output capacitance
Supply
current
ICC
-250
250
VCANL = 7 V
-250
250
mA
See receiver
Standby
SN65HVD230
V(Rs) = VCC
370
600
Sleep
SN65HVD231
V(Rs) = VCC, D at VCC
0.04
1
Dominant
VI = 0 V,
No load
Dominant
10
17
Recessive
VI = VCC,
No load
Recessive
10
17
All devices
(1)
VCANH = -2 V
μA
mA
All typical values are at 25°C and with a 3.3-V supply.
DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
MIN
TYP
MAX
UNIT
SN65HVD230 AND SN65HVD231
tPLH
Propagation delay time, low-to-high-level
output
V(Rs) = 0 V
35
85
RS with 10 kΩ to ground
70
125
RS with 100 kΩ to ground
500
870
70
120
RS with 10 kΩ to ground
130
180
RS with 100 kΩ to ground
870
1200
V(Rs) = 0 V
tPHL
Propagation delay time, high-to-low-level
output
V(Rs) = 0 V
tsk(p)
Pulse skew (|tPHL - tPLH|)
RS with 10 kΩ to ground
Differential output signal rise time
tf
Differential output signal fall time
tr
Differential output signal rise time
tf
Differential output signal fall time
tr
Differential output signal rise time
tf
Differential output signal fall time
ns
35
CL = 50 pF,
See Figure 4
60
RS with 100 kΩ to ground
tr
ns
ns
370
V(Rs) = 0 V
RS with 10 kΩ to ground
RS with 100 kΩ to ground
25
50
100
ns
40
55
80
ns
80
120
160
ns
80
125
150
ns
600
800
1200
ns
600
825
1000
ns
SN65HVD232
tPLH
Propagation delay time, low-to-high-level output
35
85
tPHL
Propagation delay time, high-to-low-level output
70
120
tsk(p)
Pulse skew (|tPHL - tPLH|)
tr
Differential output signal rise time
25
50
100
tf
Differential output signal fall time
40
55
80
CL = 50 pF,
See Figure 4
© 2001–2011, Texas Instruments Incorporated
35
ns
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RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VIT+
Positive-going input threshold voltage
VIT-
Negative-going input threshold voltage
Vhys
Hysteresis voltage (VIT+ - VIT-)
VOH
High-level output voltage
-6 V ≤ VID ≤ 500 mV, IO = -8 mA, See Figure 5
VOL
Low-level output voltage
900 mV ≤ VID ≤ 6 V, IO = 8 mA, See Figure 5
See Table 7
UNIT
750
900
mV
650
mV
100
VIH = 7 V,
Bus input current
MAX
500
2.4
0.4
VIH = 7 V
II
TYP (1)
VCC = 0 V
Other input at 0 V,
D=3V
VIH = -2 V
VIH = -2 V,
VCC = 0 V
100
250
100
350
-200
-30
-100
-20
V
μA
μA
Ci
CANH, CANL input capacitance
Pin-to-ground,
VI = 0.4 sin(4E6πt) + 0.5 V
V(D) = 3 V,
32
pF
Cdiff
Differential input capacitance
Pin-to-pin,
VI = 0.4 sin(4E6πt) + 0.5 V
V(D) = 3 V,
16
pF
Rdiff
Differential input resistance
Pin-to-pin,
RI
CANH, CANL input resistance
ICC
Supply current
(1)
V(D) = 3 V
40
70
100
kΩ
20
35
50
kΩ
See driver
All typical values are at 25°C and with a 3.3-V supply.
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
tPLH
Propagation delay time, low-to-high-level output
tPHL
Propagation delay time, high-to-low-level output
tsk(p)
Pulse skew (|tPHL - tPLH|)
tr
Output signal rise time
tf
Output signal fall time
TEST CONDITIONS
MIN
See Figure 6
See Figure 6
TYP MAX
UNIT
35
50
ns
35
50
ns
10
ns
1.5
ns
1.5
ns
DEVICE SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
t(LOOP1)
t(LOOP2)
8
Total loop delay, driver input to receiver
output, recessive to dominant
Total loop delay, driver input to receiver
output, dominant to recessive
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TEST CONDITIONS
MIN
TYP
MAX
V(Rs) = 0 V,
See Figure 9
70
115
RS with 10 kΩ to ground,
See Figure 9
105
175
RS with 100 kΩ to ground,
See Figure 9
535
920
V(Rs) = 0 V,
See Figure 9
100
135
RS with 10 kΩ to ground,
See Figure 9
155
185
RS with 100 kΩ to ground,
See Figure 9
830
990
UNIT
ns
ns
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DEVICE CONTROL-PIN CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
t(WAKE)
TEST CONDITIONS
SN65HVD230 wake-up time from standby mode
with RS
SN65HVD231 wake-up time from sleep mode
with RS
Reference output voltage
I(Rs)
Input current for high-speed
TYP (1)
MAX
0.55
1.5
μs
3
5
μs
UNIT
See Figure 8
-5 μA < I(Vref) < 5 μA
Vref
(1)
MIN
-50 μA < I(Vref) < 50 μA
0.45 VCC
0.55 VCC
0.4 VCC
0.6 VCC
-450
0
V(Rs) < 1 V
V
μA
All typical values are at 25°C and with a 3.3-V supply.
PARAMETER MEASUREMENT INFORMATION
VCC
IO
II
D
IO
60 Ω
0 V or 3 V
VOD
CANH
VI
CANL
Figure 1. Driver Voltage and Current Definitions
167 Ω
VOD
0V
60 Ω
167 Ω
±
–2 V ≤ VTEST ≤ 7 V
Figure 2. Driver VOD
Dominant
CANH
Recessive
CANL
≈3V
VOH
≈ 2.3 V
VOL
≈1V
VOH
CANH
CANL
Figure 3. Driver Output Voltage Definitions
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PARAMETER MEASUREMENT INFORMATION (continued)
RL = 60 Ω
Signal
Generator
(see Note A)
CL = 50 pF
(see Note B)
VO
50 Ω
RS = 0 Ω to 100 kΩ for SN65HVD230 and SN65HVD231
N/A for SN65HVD232
3V
Input
1.5 V
0V
tPLH
tPHL
VOD(D)
90%
0.9 V
Output
0.5 V
10%
tr
VOD(R)
tf
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 500 kHz, 50% duty cycle, tr ≤ 6
ns, tf ≤ 6 ns, Zo = 50 Ω.
B.
CL includes probe and jig capacitance.
Figure 4. Driver Test Circuit and Voltage Waveforms
IO
VID
V
)V
CANL
VIC + CANH
2
VCANH
VO
VCANL
Figure 5. Receiver Voltage and Current Definitions
10
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PARAMETER MEASUREMENT INFORMATION (continued)
Output
Signal
Generator
(see Note A)
50 Ω
1.5 V
CL = 15 pF
(see Note B)
2.9 V
Input
2.2 V
1.5 V
tPLH
tPHL
VOH
90%
Output
1.3 V
10%
tr
VOL
tf
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 500 kHz, 50% duty cycle, tr ≤ 6
ns, tf ≤ 6 ns, Zo = 50 Ω.
B.
CL includes probe and jig capacitance.
Figure 6. Receiver Test Circuit and Voltage Waveforms
100 Ω
Pulse Generator,
15 µs Duration,
1% Duty Cycle
Figure 7. Overvoltage Protection
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PARAMETER MEASUREMENT INFORMATION (continued)
Table 7. Receiver Characteristics Over Common Mode With V(Rs) = 1.2 V
VIC
VID
VCANH
VCANL
R OUTPUT
-2 V
900 mV
-1.55 V
-2.45 V
L
7V
900 mV
8.45 V
6.55 V
L
1V
6V
4V
-2 V
L
4V
6V
7V
1V
L
-2 V
500 mV
-1.75 V
-2.25 V
H
7V
500 mV
7.25 V
6.75 V
H
1V
-6 V
-2 V
4V
H
4V
-6 V
1V
7V
H
X
X
Open
Open
H
VOL
VOH
VCC
10 kΩ
D
R
60 Ω
0V
Output
CL = 15 pF
RS
Generator
PRR = 150 kHz
50% Duty Cycle
tr, tf < 6 ns
Zo = 50 Ω
Signal
Generator
50 Ω
+
V(Rs)
–
VCC
1.5 V
V(Rs)
0V
t(WAKE)
R Output
1.3 V
Figure 8. t(WAKE) Test Circuit and Voltage Waveforms
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0 Ω, 10 kΩ or
100 kΩ ±5%
RS
DUT
CANH
VI
D
60 Ω ±1%
CANL
R
+
15 pF ±20%
VO
VCC
VI
50%
50%
0V
t(LOOP2)
t(LOOP1)
VOH
VO
50%
50%
VOL
A.
All VI input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 6 ns, Pulse Repetition
Rate (PRR) = 125 kHz, 50% duty cycle.
Figure 9. t(LOOP) Test Circuit and Voltage Waveforms
TYPICAL CHARACTERISTICS
SUPPLY CURRENT (RMS)
vs
FREQUENCY
LOGIC INPUT CURRENT (PIN D)
vs
INPUT VOLTAGE
22
0
VCC = 3.3 V
60-Ω Load
RS at 0 V
−2
I I(L) − Logic Input Current − µ A
I CC − Supply Current (RMS) − mA
21
20
19
18
17
16
15
−4
−6
−8
−10
−12
−14
14
13
−16
0
250
500
f − Frequency − kbps
Figure 10.
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750
1000
0
0.6
1.1 1.6
2.1
2.6
VI − Input Voltage − V
3.1
3.6
Figure 11.
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TYPICAL CHARACTERISTICS (continued)
BUS INPUT CURRENT
vs
BUS INPUT VOLTAGE
DRIVER LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
160
I OL− Driver Low-Level Output Current − mA
I I − Bus Input Current − µ A
400
300
200
VCC = 0 V
100
0
VCC = 3.6 V
−100
−200
−300
−400
−7 −6 −4 −3 −1 0
140
120
100
80
60
40
20
0
1
3
4
6
7
8 10 11
0
12
VI − Bus Input Voltage − V
Figure 12.
Figure 13.
DRIVER HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
DOMINANT VOLTAGE (VOD)
vs
FREE-AIR TEMPERATURE
VCC = 3.6 V
2.5
100
VOD− Dominant Voltage − V
I OH − Driver High-Level Output Current − mA
4
3
120
80
60
40
VCC = 3.3 V
VCC = 3 V
2
1.5
1
0.5
20
0
0
0
0.5
1
1.5
2
2.5
3
VO(CANH) − High-Level Output Voltage − V
Figure 14.
14
1
2
3
VO(CANL)− Low-Level Output Voltage − V
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3.5
−55
−40
0
25
70
85
125
TA − Free-Air Temperature − °C
Figure 15.
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TYPICAL CHARACTERISTICS (continued)
38
RS = 0
37
36
VCC = 3 V
35
VCC = 3.3 V
34
VCC = 3.6 V
33
32
31
30
−55
−40
0
25
70
85
125
RECEIVER HIGH-TO-LOW PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
t PHL− Receiver High-to-Low Propagation Delay Time − ns
t PLH − Receiver Low-to-High Propagation Delay Time − ns
RECEIVER LOW-TO-HIGH PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
40
RS = 0
39
VCC = 3 V
38
VCC = 3.3 V
37
VCC = 3.6 V
36
35
34
−55
−40
0
25
70
85
125
TA − Free-Air Temperature − °C
Figure 16.
Figure 17.
DRIVER LOW-TO-HIGH PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
DRIVER HIGH-TO-LOW PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
55
RS = 0
VCC = 3 V
50
45
40
VCC = 3.3 V
35
VCC = 3.6 V
30
25
20
15
10
−55
−40
0
25
70
85
TA − Free-Air Temperature − °C
Figure 18.
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125
t PHL− Driver High-to-Low Propagation Delay Time − ns
t PLH − Driver Low-to-High Propagation Delay Time − ns
TA − Free-Air Temperature − °C
90
RS = 0
VCC = 3.6 V
85
80
75
VCC = 3.3 V
70
VCC = 3 V
65
60
55
50
−55
−40
0
25
70
85
125
TA − Free-Air Temperature − °C
Figure 19.
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TYPICAL CHARACTERISTICS (continued)
90
RS = 10 kΩ
80
70
VCC = 3 V
VCC = 3.3 V
60
50
VCC = 3.6 V
40
30
20
10
0
−55
−40
0
25
70
85
125
DRIVER HIGH-TO-LOW PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
t PHL − Driver High-to-Low Propagation Delay Time − ns
t PLH − Driver Low-to-High Propagation Delay Time − ns
DRIVER LOW-TO-HIGH PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
150
140
VCC = 3.3 V
130
VCC = 3 V
120
110
100
90
80
−55
−40
0
25
70
85
125
TA − Free-Air Temperature − °C
Figure 20.
Figure 21.
DRIVER LOW-TO-HIGH PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
DRIVER HIGH-TO-LOW PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
800
RS = 100 kΩ
700
VCC = 3 V
600
VCC = 3.3 V
500
VCC = 3.6 V
400
300
200
100
0
−55
−40
0
25
70
85
TA − Free-Air Temperature − °C
Figure 22.
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125
t PHL− Driver High-to-Low Propagation Delay Time − ns
t PLH − Driver Low-to-High Propagation Delay Time − ns
TA − Free-Air Temperature − °C
16
RS = 10 kΩ
VCC = 3.6 V
1000
RS = 100 kΩ
VCC = 3.6 V
950
VCC = 3.3 V
900
850
VCC = 3 V
800
750
700
−55
−40
0
25
70
85
125
TA − Free-Air Temperature − °C
Figure 23.
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TYPICAL CHARACTERISTICS (continued)
DRIVER OUTPUT CURRENT
vs
SUPPLY VOLTAGE
DIFFERENTIAL DRIVER OUTPUT FALL TIME
vs
SOURCE RESISTANCE (Rs)
µs
t f − Differential Driver Output Fall Time −
I O − Driver Output Current − mA
50
40
30
20
10
1.50
1.40
1.30
VCC = 3.3 V
1.20
1.10
1.00
VCC = 3.6 V
0.90
0.80
0.70
0.60
VCC = 3 V
0.50
0.40
0.30
0.20
0.10
0
0
1
1.5
2
2.5
3
3.5
4
0
VCC − Supply Voltage − V
50
100
150
200
Rs − Source Resistance − kΩ
Figure 24.
Figure 25.
REFERENCE VOLTAGE
vs
REFERENCE CURRENT
3
V ref − Reference Voltage − V
2.5
2
VCC = 3.6 V
1.5
VCC = 3 V
1
0.5
0
−50
−5
5
50
Iref − Reference Current − µA
Figure 26.
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APPLICATION INFORMATION
This application provides information concerning the implementation of the physical medium attachment layer in
a CAN network according to the ISO 11898 standard. It presents a typical application circuit and test results, as
well as discussions on slope control, total loop delay, and interoperability in 5-V systems.
INTRODUCTION
ISO 11898 is the international standard for high-speed serial communication using the controller area network
(CAN) bus protocol. It supports multimaster operation, real-time control, programmable data rates up to 1 Mbps,
and powerful redundant error checking procedures that provide reliable data transmission. It is suited for
networking intelligent devices as well as sensors and actuators within the rugged electrical environment of a
machine chassis or factory floor. The SN65HVD230 family of 3.3-V CAN transceivers implement the lowest
layers of the ISO/OSI reference model. This is the interface with the physical signaling output of the CAN
controller of the Texas Instruments TMS320Lx240x 3.3-V DSPs, as illustrated in Figure 27.
ISO 11898 Specification
Implementation
Application Specific Layer
TMS320Lx2403/6/7
3.3-V
DSP
Logic Link Control
Data-Link
Layer
Medium Access Control
Embedded
CAN
Controller
Physical Signaling
Physical
Layer
Physical Medium Attachment
SN65HVD230
Medium Dependent Interface
CAN Bus-Line
Figure 27. The Layered ISO 11898 Standard Architecture
The SN65HVD230 family of CAN transceivers are compatible with the ISO 11898 standard; this ensures
interoperability with other standard-compliant products.
APPLICATION OF THE SN65HVD230
Figure 28 illustrates a typical application of the SN65HVD230 family. The output of a DSP's CAN controller is
connected to the serial driver input, pin D, and receiver serial output, pin R, of the transceiver. The transceiver is
then attached to the differential bus lines at pins CANH and CANL. Typically, the bus is a twisted pair of wires
with a characteristic impedance of 120 Ω, in the standard half-duplex multipoint topology of Figure 29. Each end
of the bus is terminated with 120-Ω resistors in compliance with the standard to minimize signal reflections on the
bus.
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Electronic Control Unit (ECU)
TMS320Lx2403/6/7
CAN-Controller
CANTX/IOPC6
CANRX/IOPC7
D
R
SN65HVD230
CANH
CANL
CAN Bus Line
Figure 28. Details of a Typical CAN Node
ECU
1
ECU
2
ECU
n
CANH
120 Ω
120 Ω
CAN Bus Line
CANL
Figure 29. Typical CAN Network
The SN65HVD230/231/232 3.3-V CAN transceivers provide the interface between the 3.3-V TMS320Lx2403/6/7
CAN DSPs and the differential bus line, and are designed to transmit data at signaling rates up to 1 Mbps as
defined by the ISO 11898 standard.
FEATURES of the SN65HVD230, SN65HVD231, and SN65HVD232
The SN65HVD230/231/232 are pin-compatible (but not functionally identical) with one another and, depending
upon the application, may be used with identical circuit boards.
These transceivers feature 3.3-V operation and standard compatibility with signaling rates up to 1 Mbps, and also
offer 16-kV HBM ESD protection on the bus pins, thermal shutdown protection, bus fault protection, and
open-circuit receiver failsafe. The fail-safe design of the receiver assures a logic high at the receiver output if the
bus wires become open circuited. If a high ambient operating environment temperature or excessive output
current result in thermal shutdown, the bus pins become high impedance, while the D and R pins default to a
logic high.
The bus pins are also maintained in a high-impedance state during low VCC conditions to ensure glitch-free
power-up and power-down bus protection for hot-plugging applications. This high-impedance condition also
means that an unpowered node does not disturb the bus. Transceivers without this feature usually have a very
low output impedance. This results in a high current demand when the transceiver is unpowered, a condition that
could affect the entire bus.
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OPERATING MODES
RS (pin 8) of the SN65HVD230 and SN65HVD231 provides for three different modes of operation: high-speed
mode, slope-control mode, and low-power mode.
High-Speed
The high-speed mode can be selected by applying a logic low to RS (pin 8). The high-speed mode of operation is
commonly employed in industrial applications. High-speed allows the output to switch as fast as possible with no
internal limitation on the output rise and fall slopes. The only limitations of the high-speed operation are cable
length and radiated emission concerns, each of which is addressed by the slope control mode of operation.
If the low-power standby mode is to be employed in the circuit, direct connection to a DSP output pin can be
used to switch between a logic-low level (< 1 V) for high speed operation, and the logic-high level (> 0.75 VCC)
for standby. Figure 30 shows a typical DSP connection, and Figure 31 shows the HVD230 driver output signal in
high-speed mode on the CAN bus.
D
GND
VCC
R
1
8
2
7
3
6
4
5
RS
IOPF6
CANH
CANL
Vref
TMS320LF2406
or
TMS320LF2407
Figure 30. RS (Pin 8) Connection to a TMS320LF2406/07 for High Speed/Standby Operation
1 Mbps
Driver Output
NRZ Data
1
Figure 31. Typical High Speed SN65HVD230 Output Waveform Into a 60-Ω Load
Slope Control
Electromagnetic compatibility is essential in many applications using unshielded bus cable to reduce system
cost. To reduce the electromagnetic interference generated by fast rise times and resulting harmonics, the rise
and fall slopes of the SN65HVD230 and SN65HVD231 driver outputs can be adjusted by connecting a resistor
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from RS (pin 8) to ground or to a logic low voltage, as shown in Figure 32. The slope of the driver output signal is
proportional to the pin's output current. This slope control is implemented with an external resistor value of 10 kΩ
to achieve a ≉ 15 V/μs slew rate, and up to 100 kΩ to achieve a ≉ 2.0 V/μs slew rate as displayed in Figure 33.
Typical driver output waveforms from a pulse input signal with and without slope control are displayed in
Figure 34. A pulse input is used rather than NRZ data to clearly display the actual slew rate.
D
GND
VCC
R
1
8
2
7
3
6
4
5
10 kΩ
to
100 kΩ
RS
IOPF6
TMS320LF2406
or
TMS320LF2407
CANH
CANL
Vref
Figure 32. Slope Control/Standby Connection to a DSP
DRIVER OUTPUT SIGNAL SLOPE
vs
SLOPE CONTROL RESISTANCE
Driver Outout Signal Slop – V/ µ s
25
20
15
10
5
0
0
10
4.7
20
30 40
50 33
60 47
70
6.8 10
15 22
Slope Control Resistance – kΩ
80
68
90
100
Figure 33. HVD230 Driver Output Signal Slope vs Slope Control Resistance Value
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RS = 0 Ω
RS = 10 kΩ
RS = 100 kΩ
Figure 34. Typical SN65HVD230 250-kbps Output Pulse Waveforms With Slope Control
Standby Mode (Listen Only Mode) of the HVD230
If a logic high (> 0.75 VCC) is applied to RS (pin 8) in Figure 30 and Figure 32, the circuit of the SN65HVD230
enters a low-current, listen only standby mode, during which the driver is switched off and the receiver remains
active. In this listen only state, the transceiver is completely passive to the bus. It makes no difference if a slope
control resistor is in place as shown in Figure 32. The DSP can reverse this low-power standby mode when the
rising edge of a dominant state (bus differential voltage > 900 mV typical) occurs on the bus. The DSP, sensing
bus activity, reactivates the driver circuit by placing a logic low (< 1.2 V) on RS (pin 8).
The Babbling Idiot Protection of the HVD230
Occasionally, a runaway CAN controller unintentionally sends messages that completely tie up the bus (what is
referred to in CAN jargon as a babbling idiot). When this occurs, the DSP can engage the listen-only standby
mode to disengage the driver and release the bus, even when access to the CAN controller has been lost. When
the driver circuit is deactivated, its outputs default to a high-impedance state.
Sleep Mode of the HVD231
The unique difference between the SN65HVD230 and the SN65HVD231 is that both driver and receiver are
switched off in the SN65HVD231 when a logic high is applied to RS (pin 8). The device remains in a very low
power-sleep mode until the circuit is reactivated with a logic low applied to RS (pin 8). While in this sleep mode,
the bus-pins are in a high-impedance state, while the D and R pins default to a logic high.
LOOP PROPAGATION DELAY
Transceiver loop delay is a measure of the overall device propagation delay, consisting of the delay from the
driver input to the differential outputs, plus the delay from the receiver inputs to its output.
The loop delay of the transceiver displayed in Figure 35 increases accordingly when slope control is being used.
This increased loop delay means that the total bus length must be reduced to meet the CAN bit-timing
requirements of the overall system. The loop delay becomes ≉ 100 ns when employing slope control with a
10-kΩ resistor, and ≉ 500 ns with a 100-kΩ resistor. Therefore, considering that the rule-of-thumb propagation
22
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delay of typical bus cable is 5 ns/m, slope control with the 100-kΩ resistor decreases the allowable bus length by
the difference between the 500-ns max loop delay and the loop delay with no slope control, 70.7 ns. This
equates to (500-70.7 ns)/5 ns, or approximately 86 m less bus length. This slew-rate/bus length trade-off to
reduce electromagnetic interference to adjoining circuits from the bus can also be solved with a quality shielded
bus cable.
(
)
Figure 35. 70.7-ns Loop Delay Through the HVD230 With RS = 0
ISO 11898 COMPLIANCE OF SN65HVD230 FAMILY OF 3.3-V CAN TRANSCEIVERS
Introduction
Many users value the low power consumption of operating their CAN transceivers from a 3.3 V supply. However,
some are concerned about the interoperability with 5-V supplied transceivers on the same bus. This report
analyzes this situation to address those concerns.
Differential Signal
CAN is a differential bus where complementary signals are sent over two wires and the voltage difference
between the two wires defines the logical state of the bus. The differential CAN receiver monitors this voltage
difference and outputs the bus state with a single-ended output signal.
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NOISE MARGIN
900 mV Threshold
RECEIVER DETECTION WINDOW
75% SAMPLE POINT
500 mV Threshold
NOISE MARGIN
Figure 36. Typical SN65HVD230 Differential Output Voltage Waveform
The CAN driver creates the difference voltage between CANH and CANL in the dominant state. The dominant
differential output of the SN65HVD230 is greater than 1.5 V and less than 3 V across a 60-ohm load. The
minimum required by ISO 11898 is 1.5 V and maximum is 3 V. These are the same limiting values for 5 V
supplied CAN transceivers. The bus termination resistors drive the recessive bus state and not the CAN driver.
A CAN receiver is required to output a recessive state with less than 500 mV and a dominant state with more
than 900 mV difference voltage on its bus inputs. The CAN receiver must do this with common-mode input
voltages from -2 V to 7 volts. The SN65HVD230 family receivers meet these same input specifications as 5-V
supplied receivers.
Common-Mode Signal
A common-mode signal is an average voltage of the two signal wires that the differential receiver rejects. The
common-mode signal comes from the CAN driver, ground noise, and coupled bus noise. Obviously, the supply
voltage of the CAN transceiver has nothing to do with noise. The SN65HVD230 family driver lowers the
common-mode output in a dominant bit by a couple hundred millivolts from that of most 5-V drivers. While this
does not fully comply with ISO 11898, this small variation in the driver common-mode output is rejected by
differential receivers and does not effect data, signal noise margins or error rates.
Interoperability of 3.3-V CAN in 5-V CAN Systems
The 3.3-V supplied SN65HVD23x family of CAN transceivers are electrically interchangeable with 5-V CAN
transceivers. The differential output is the same. The recessive common-mode output is the same. The dominant
common-mode output voltage is a couple hundred millivolts lower than 5-V supplied drivers, while the receivers
exhibit identical specifications as 5-V devices.
Electrical interoperability does not assure interchangeability however. Most implementers of CAN buses
recognize that ISO 11898 does not sufficiently specify the electrical layer and that strict standard compliance
alone does not ensure interchangeability. This comes only with thorough equipment testing.
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CANH
Bus Lines -- 40 m max
Stub Lines -- 0.3 m max
120 W
120
CANL
5V
VCC
Vref
0.1mF
SN65HVD251
RS
5V
VCC
Vref
RS
GND
D
CANTX
0.1mF
SN65HVD251
3.3 V
VCC
Vref
RS
GND
R
D
CANRX
CANTX
0.1mF
SN65HVD230
GND
R
D
CANRX
CANTX
R
CANRX
TMS320LF243
TMS320LF243
TMS320LF2407A
Sensor, Actuator, or Control
Equipment
Sensor, Actuator, or Control
Equipment
Sensor, Actuator, or Control
Equipment
Figure 37. 3.3-V and 5-V CAN Transceiver System
Trigger
Input
TEKTRONIX
HFS-9003
Pattern
Generator
TEKTRONIX
784D
Oscilloscope
TEKTRONIX
P6243
Single-Ended
Probes
One Meter Belden Cable # 3105A
120 W
120 W
SN65HVD230
SN65HVD230
Competitor X251
SN65HVD251
– +
HP E3516A
3.3-V Power
Supply
– +
HP E3516A
5-V Power
Supply
Figure 38. 3.3-V and 5-V CAN Transceiver System Testing
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REVISION HISTORY
Changes from Revision I (October 2007) to Revision J
Page
•
Deleted Low-to-High Propagation Delay Time vs Common-Mode Input Voltage Characteristics ...................................... 17
•
Deleted Driver Schematic Diagram .................................................................................................................................... 17
•
Added Figure 37 ................................................................................................................................................................. 25
•
Added Figure 38 ................................................................................................................................................................. 25
Changes from Revision J (January 2009) to Revision K
•
26
Page
Replaced the DISSIPATION RATING TABLE with the Thermal Information table .............................................................. 6
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PACKAGE OPTION ADDENDUM
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11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
SN65HVD230D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
VP230
SN65HVD230DG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
VP230
SN65HVD230DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
VP230
SN65HVD230DRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
VP230
SN65HVD231D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
VP231
SN65HVD231DG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
VP231
SN65HVD231DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
VP231
SN65HVD231DRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
VP231
SN65HVD232D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
VP232
SN65HVD232DG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
VP232
SN65HVD232DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
VP232
SN65HVD232DRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
VP232
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Jan-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN65HVD230DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
SN65HVD231DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
SN65HVD232DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Jan-2011
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN65HVD230DR
SOIC
D
8
2500
340.5
338.1
20.6
SN65HVD231DR
SOIC
D
8
2500
340.5
338.1
20.6
SN65HVD232DR
SOIC
D
8
2500
340.5
338.1
20.6
Pack Materials-Page 2
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