SN65HVD231QDRG4Q1

SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 3.3-V CAN TRANSCEIVERS D Thermal Shutdown Protection D Open-Circuit Fail-Safe Design FEATURES D Qualified for Automotive Applications D ESD Protection Exceeds 2000 V Per D D D D D D D D D MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Operates With a 3.3-V Supply Low Power Replacement for the PCA82C250 Footprint Bus/Pin ESD Protection Exceeds 15-kV HBM Controlled Driver Output Transition Times for Improved Signal Quality on the SN65HVD230Q and SN65HVD231Q Unpowered Node Does Not Disturb the Bus Compatible With the Requirements of the ISO 11898 Standard Low-Current SN65HVD230Q Standby Mode 370 µA Typical Low-Current SN65HVD231Q Sleep Mode 0.1 µA Typical Designed for Signaling Rates‡ Up To 1 Megabit/Second (Mbps) SN65HVD230QD SN65HVD231QD (TOP VIEW) D GND VCC R 1 8 2 7 3 6 4 5 RS CANH CANL Vref SN65HVD232QD (TOP VIEW) D GND VCC R 1 8 2 7 3 6 4 5 NC CANH CANL NC NC − No internal connection logic diagram (positive logic) VCC SN65HVD230Q, SN65HVD231Q SN65HVD232Q Logic Diagram (Positive Logic) Logic Diagram (Positive Logic) 3 5 Vref D D RS R 1 1 8 4 R 7 6 4 7 6 CANH CANL CANH CANL Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. ‡ The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second). Copyright  2008, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com 1 SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 DESCRIPTION The SN65HVD230Q, SN65HVD231Q, and SN65HVD232Q controller area network (CAN) transceivers are designed for use with the Texas Instruments TMS320Lx240x 3.3-V DSPs with CAN controllers, or with equivalent devices. They are intended for use in applications employing the CAN serial communication physical layer in accordance with the ISO 11898 standard. Each CAN transceiver is designed to provide differential transmit capability to the bus and differential receive capability to a CAN controller at speeds up to 1 Mbps. Designed for operation in especially-harsh environments, these devices feature cross-wire protection, loss-of-ground and overvoltage protection, overtemperature protection, as well as wide common-mode range. The transceiver interfaces the single-ended CAN controller with the differential CAN bus found in industrial, building automation, and automotive applications. It operates over a –2-V to 7-V common-mode range on the bus, and it can withstand common-mode transients of ± 25 V. On the SN65HVD230Q and SN65HVD231Q, RS (pin 8) provides three different modes of operation: high-speed, slope control, and low-power modes. The high-speed mode of operation is selected by connecting pin 8 to ground, allowing the transmitter output transistors to switch on and off as fast as possible with no limitation on the rise and fall slopes. The rise and fall slopes can be adjusted by connecting a resistor to ground at pin 8, since the slope is proportional to the pin’s output current. This slope control is implemented with external resistor values of 10 kΩ, to achieve a 15-V/µs slew rate, to 100 kΩ, to achieve a 2-V/µs slew rate. The circuit of the SN65HVD230Q enters a low-current standby mode during which the driver is switched off and the receiver remains active if a high logic level is applied to RS (pin 8). The DSP controller reverses this low-current standby mode when a dominant state (bus differential voltage > 900 mV typical) occurs on the bus. The unique difference between the SN65HVD230Q and the SN65HVD231Q is that both the driver and the receiver are switched off in the SN65HVD231Q when a high logic level is applied to RS (pin 8) and remain in this sleep mode until the circuit is reactivated by a low logic level on RS. The Vref (pin 5 on the SN65HVD230Q and SN65HVD231Q) is available as a VCC/2 voltage reference. The SN65HVD232Q is a basic CAN transceiver with no added options; pins 5 and 8 are NC, no connection. AVAILABLE OPTIONS{} FUNCTION NUMBER LOW POWER MODE INTEGRATED SLOPE CONTROL Vref PIN ’230 370-µA standby mode Yes Yes ’231 10-µA sleep mode Yes Yes ’232 No standby or sleep mode No No PART NUMBER Q100 SN65HVD230QD No SN65HVD231QD No SN65HVD232QD No SN65HVD230QDQ1 Yes SN65HVD231QDQ1 Yes SN65HVD232QDQ1 Yes TA MARKED AS: HV230Q −40°C 40°C to t 125°C HV231Q HV232Q 230Q1 −40°C 40°C to t 125°C 231Q1 232Q1 † For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at http://www.ti.com. ‡ Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging. The D package is available taped and reeled. Add the suffix R to device type (e.g., SN65HVD230QDRQ1). 2 www.ti.com SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 Function Tables DRIVER (SN65HVD230Q, SN65HVD231Q) OUTPUTS INPUT D RS CANH L V(Rs) < 1.2 12V H Open X BUS STATE CANL H L Dominant Z Z Recessive Z Z Recessive X V(Rs) > 0.75 VCC Z Z H = high level; L = low level; X = irrelevant; ? = indeterminate Recessive DRIVER (SN65HVD232Q) OUTPUTS INPUT D CANH BUS STATE CANL L H L Dominant H Z Z Recessive Open Z Z Recessive H = high level; L = low level RECEIVER (SN65HVD230Q) DIFFERENTIAL INPUTS RS OUTPUT R L VID ≥ 0.9 V X 0.5 V < VID < 0.9 V X ? VID ≤ 0.5 V X H Open X H H = high level; L = low level; X = irrelevant; ? = indeterminate RECEIVER (SN65HVD231Q) DIFFERENTIAL INPUTS RS OUTPUT R VID ≥ 0.9 V L 0.5 V < VID < 0.9 V ? V(Rs) < 1.2 V VID ≤ 0.5 V H X V(Rs) > 0.75 VCC H X 1.2 V < V(Rs) < 0.75 VCC X ? Open H H = high level; L = low level; X = irrelevant; ? = indeterminate RECEIVER (SN65HVD232Q) DIFFERENTIAL INPUTS OUTPUT R VID ≥ 0.9 V L 0.5 V < VID < 0.9 V ? VID ≤ 0.5 V H Open H H = high level; L = low level; X = irrelevant; ? = indeterminate www.ti.com 3 SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 Function Tables (Continued) TRANSCEIVER MODES (SN65HVD230Q, SN65HVD231Q) OPERATING MODE V(Rs) V(RS) > 0.75 VCC Standby 10 kΩ to 100 kΩ to ground Slope control V(RS) < 1 V High speed (no slope control) Terminal Functions SN65HVD230Q, SN65HVD231Q TERMINAL NAME DESCRIPTION NO. CANL 6 Low bus output CANH 7 High bus output D 1 Driver input GND 2 Ground R 4 Receiver output RS 8 Standby/slope control VCC 3 Supply voltage Vref 5 Reference output SN65HVD232Q TERMINAL NAME CANL 6 Low bus output CANH 7 High bus output D 1 Driver input 2 Ground GND NC 4 DESCRIPTION NO. 5, 8 No connection R 4 Receiver output VCC 3 Supply voltage www.ti.com SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 equivalent input and output schematic diagrams CANH and CANL Inputs D Input VCC VCC 110 kΩ 16 V 9 kΩ 100 kΩ 45 kΩ Input 1 kΩ Input 20 V 9 kΩ 9V CANH and CANL Outputs R Output VCC VCC 16 V 5Ω Output Output 9V 20 V www.ti.com 5 SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 absolute maximum ratings over operating free-air temperature (see Note 1) (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V Voltage range at any bus terminal (CANH or CANL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −7 V to 16 V Voltage input range, transient pulse, CANH and CANL, through 100 Ω (see Figure 7) . . . . . . . . . . . . −25 V to 25 V Input voltage range, VI (D or R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Electrostatic discharge: Human body model (see Note 2) CANH, CANL and GND . . . . . . . . . . . . . . . . . . 15 kV All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 kV Charged-device model (see Note 3) All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 kV Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating table Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. 2. Tested in accordance with JEDEC Standard 22, Test Method A114-A. 3. Tested in accordance with JEDEC Standard 22, Test Method C101. DISSIPATION RATING TABLE ‡ PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR‡ ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING TA = 125°C POWER RATING D 725 mW 5.8 mW/°C 464 mW 377 mW 145 mW This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. recommended operating conditions PARAMETER MIN Supply voltage, VCC Voltage at any bus terminal (common mode) VIC Voltage at any bus terminal (separately) VI High-level input voltage, VIH D, R Low-level input voltage, VIL D, R Differential input voltage, VID (see Figure 5) V(RS) V(RS) for standby or sleep Driver Receiver V 7 V −2.5 7.5 V 2 V 0.8 V −6 6 V 0 VCC V VCC V 100 kΩ −40 mA −8 Driver Low level output current Low-level current, IOL 6 48 Receiver Operating free-air temperature, TA § 8 −40 125 The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet. www.ti.com UNIT −2§ 0 High level output current High-level current, IOH MAX 3.6 0.75 VCC Rs wave-shaping resistance NOM 3 mA °C SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 driver electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER VOH Dominant VI = 0 V, See Figure 1 and Figure 3 CANH CANH Recessive VI = 3 V, See Figure 1 and Figure 3 Bus output voltage VOL VOD(D) Dominant Differential output voltage VOD(R) Recessive MIN TYP† MAX 2.45 VCC CANL 0.5 1.25 V 2.3 CANL UNIT 2.3 VI = 0 V, See Figure 1 1.5 2 3 VI = 0 V, See Figure 2 1.2 2 3 VI = 3 V, See Figure 1 −120 0 12 VI = 3 V, No load −0.5 −0.2 0.05 V mV V IIH High-level input current VI = 2 V −30 µA IIL Low-level input current VI = 0.8 V −30 µA IOS Short circuit output current Short-circuit Co Output capacitance ICC Supply current VCANH = −2 V −250 250 VCANL = 7 V −250 250 mA See receiver Standby SN65HVD230Q Sleep SN65HVD231Q All devices † TEST CONDITIONS 370 V(RS) = VCC 600 0.1 Dominant VI = 0 V, No load Dominant 10 17 Recessive VI = VCC , No load Recessive 10 17 TYP MAX 35 85 RS with 10 kΩ to ground 70 125 RS with 100 kΩ to ground 500 870 70 120 µA A mA All typical values are at 25°C and with a 3.3-V supply. driver switching characteristics at TA = 25°C (unless otherwise noted) SN65HVD230Q and SN65HVD231Q PARAMETER TEST CONDITIONS MIN V(RS) = 0 V tPLH Propagation delay time, low low-to-high-level to high level output V(RS) = 0 V tPHL Propagation delay time, high high-to-low-level to low level output RS with 10 kΩ to ground 130 180 RS with 100 kΩ to ground 870 1200 V(RS) = 0 V tsk(p) Pulse skew (|tP(HL) − tP(LH)|) RS with 10 kΩ to ground Differential output signal rise time tf Differential output signal fall time tr Differential output signal rise time tf Differential output signal fall time tr Differential output signal rise time tf Differential output signal fall time V(RS) = 0 V RS with 10 kΩ to ground RS with 100 kΩ to ground www.ti.com ns ns 35 CL = 50 pF, See Figure 4 60 RS with 100 kΩ to ground tr UNIT ns 370 25 50 100 ns 40 55 80 ns 80 120 160 ns 80 125 150 ns 600 800 1200 ns 600 825 1000 ns 7 SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 driver switching characteristics at TA = 25°C (unless otherwise noted) SN65HVD232Q PARAMETER TEST CONDITIONS MIN TYP MAX 35 85 UNIT ns 70 120 ns tPLH Propagation delay time, low-to-high-level output tPHL Propagation delay time, high-to-low-level output tsk(p) Pulse skew (|tP(HL) − tP(LH)|) tr Differential output signal rise time 25 50 100 ns tf Differential output signal fall time 40 55 80 ns 35 CL = 50 pF, See Figure 4 ns receiver electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN VIT+ Positive-going input threshold voltage VIT− Negative-going input threshold voltage Vhys Hysteresis voltage (VIT+ − VIT−) VOH High-level output voltage −6 V ≤ VID ≤ 500 mV, IO = −8 mA, See Figure 5 VOL Low-level output voltage 900 mV ≤ VID ≤ 6 V, IO = 8 mA, See Figure 5 See Table 1 500 VIH = 7 V, Bus input current MAX UNIT 750 900 mV 650 mV 100 VIH = 7 V II TYP† VCC = 0 V VIH = −2 V Other input at 0 V, D=3V VIH = −2 V, VCC = 0 V 2.4 V 0.4 100 250 100 350 −200 −30 −100 −20 µA A A µA Ci CANH, CANL input capacitance Pin-to-ground, VI = 0.4 sin(4E6πt) + 0.5 V V(D) = 3 V, 32 pF Cdiff Differential input capacitance Pin-to-pin, VI = 0.4 sin(4E6πt) + 0.5 V V(D) = 3 V, 16 pF Rdiff Differential input resistance Pin-to-pin, V(D) = 3 V RT CANH, CANL input resistance ICC † 40 70 100 kΩ 20 35 50 kΩ MIN TYP MAX See driver Supply current All typical values are at 25°C and with a 3.3-V supply. receiver switching characteristics at TA = 25°C (unless otherwise noted) TEST CONDITIONS PARAMETER UNIT tPLH Propagation delay time, low-to-high-level output 35 50 ns tPHL Propagation delay time, high-to-low-level output 35 50 ns tsk(p) Pulse skew (|tP(HL) − tP(LH)|) 10 ns tr Output signal rise time tf Output signal fall time t(loop) Total loop delay, driver input to receiver output V(RS) = 0 V 70 135 t(loop) Total loop delay, driver input to receiver output RS with 10 kΩ to ground 105 175 t(loop) Total loop delay, driver input to receiver output RS with 100 kΩ to ground 535 920 8 See Figure 6 See Figure 6 www.ti.com 1.5 ns 1.5 ns ns SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 device control-pin characteristics over recommended operating conditions (unless otherwise noted) PARAMETER t(WAKE) TEST CONDITIONS SN65HVD230Q wake-up time from standby mode with RS MIN See Figure 8 TYP† MAX UNIT 0.55 1.5 µS 3 µS SN65HVD231Q wake-up time from sleep mode with RS † −5 µA < I(Vref) < 5 µA 0.45 VCC 0.55 VCC 0.4 VCC 0.6 VCC Vref Reference output voltage −50 µA < I(Vref) < 50 µA I(RS) Input current for high-speed V(RS) < 1 V −450 0 V µA All typical values are at 25°C and with a 3.3 V supply. PARAMETER MEASUREMENT INFORMATION VCC IO II D IO 60 Ω 0 V or 3 V VOD CANH VI CANL Figure 1. Driver Voltage and Current Definitions 167 Ω VOD 0V 60 Ω 167 Ω ± −2 V ≤ VTEST ≤ 7 V Figure 2. Driver VOD Dominant CANH Recessive CANL ≈3V VOH ≈ 2.3 V VOL ≈1V VOH CANH CANL Figure 3. Driver Output Voltage Definitions www.ti.com 9 SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 PARAMETER MEASUREMENT INFORMATION RL = 60 Ω Signal Generator (see Note A) CL = 50 pF (see Note B) VO 50 Ω RS = 0 Ω to 100 kΩ for SN65HVD230Q and SN65HVD231Q N/A for SN65HVD232Q 3V Input 1.5 V 0V tP(LH) tP(HL) VOD(D) 90% 0.9 V Output 0.5 V 10% tr VOD(R) tf NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 500 kHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, Zo = 50 Ω. B. CL includes probe and jig capacitance. Figure 4. Driver Test Circuit and Voltage Waveforms IO VID V IC V )V CANL + CANH 2 VCANH VCANL Figure 5. Receiver Voltage and Current Definitions 10 www.ti.com VO SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 PARAMETER MEASUREMENT INFORMATION Output Signal Generator (see Note A) 50 Ω 1.5 V CL = 15 pF (see Note B) 2.9 V Input 2.2 V 1.5 V tP(LH) tP(HL) VOH 90% Output 1.3 V 10% tr VOL tf NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 500 kHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, Zo = 50 Ω. B. CL includes probe and jig capacitance. Figure 6. Receiver Test Circuit and Voltage Waveforms 100 Ω Pulse Generator, 15 µs Duration, 1% Duty Cycle Figure 7. Overvoltage Protection www.ti.com 11 SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 PARAMETER MEASUREMENT INFORMATION Table 1. Receiver Characteristics Over Common Mode With V(RS) at 1.2 V VIC VID VCANH VCANL R OUTPUT −2 V 900 mV −1.55 V −2.45 V L 7V 900 mV 8.45 V 6.55 V L 1V 6V 4V −2 V L 4V 6V 7V 1V L −2 V 500 mV −1.75 V −2.25 V H 7V 500 mV 7.25 V 6.75 V H 1V −6 V −2 V 4V H 4V −6 V 1V 7V H X X Open Open H VOL VOH VCC 10 kΩ D R 60 Ω 0V Output CL = 15 pF RS Generator PRR = 150 kHz 50% Duty Cycle tr, tf < 6 ns Zo = 50 Ω Signal Generator 50 Ω + V(RS) − VCC 1.5 V V(RS) 0V t(WAKE) 1.3 V R Output Figure 8. t(WAKE) Test Circuit and Voltage Waveforms 12 www.ti.com SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 TYPICAL CHARACTERISTICS LOGIC INPUT CURRENT (D PIN) vs INPUT VOLTAGE 33 0 32 −2 I I(L) − Logic Input Current − µ A I CC − Supply Current (RMS) − mA SUPPLY CURRENT (RMS) vs FREQUENCY 31 30 29 28 27 26 25 −4 −6 −8 −10 −12 −14 0 250 500 −16 750 1000 1250 1500 1750 2000 f − Frequency − kbps 0 1.1 1.6 2.1 2.6 3.1 3.6 VI − Input Voltage − V Figure 9 Figure 10 BUS INPUT CURRENT vs BUS INPUT VOLTAGE DRIVER LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 400 180 300 200 VCC = 0 V 100 VCC = 3.6 V 0 −100 −200 −300 −400 −7 −6 −4 −3 −1 0 I OL − Driver Low-Level Output Current − mA I I − Bus Input Current − µ A 0.6 160 140 120 100 80 60 40 20 0 1 3 4 6 7 0 8 10 11 12 VI − Bus Input Voltage − V 1 2 3 VO(CANL)− Low-Level Output Voltage − V 4 Figure 12 Figure 11 www.ti.com 13 SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 TYPICAL CHARACTERISTICS DRIVER HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE DOMINANT VOLTAGE (VOD) vs FREE-AIR TEMPERATURE 3 VCC = 3.6 V 100 2.5 VOD− Dominant Voltage − V I OH − Driver High-Level Output Current − mA 120 80 60 40 VCC = 3 V 2 1.5 1 0.5 20 0 VCC = 3.3 V 0 0.5 1 1.5 2 2.5 3 0 3.5 −55 −40 25 70 85 125 TA − Free-Air Temperature − °C VO(CANH) − High-Level Output Voltage − V RECEIVER LOW-TO-HIGH PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE RECEIVER HIGH-TO-LOW PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 38 RS = 0 37 36 VCC = 3 V 35 VCC = 3.3 V 34 VCC = 3.6 V 33 32 31 30 −55 −40 0 25 70 85 125 t PHL− Receiver High-to-Low Propagation Delay Time − ns Figure 14 t PLH − Receiver Low-to-High Propagation Delay Time − ns Figure 13 40 RS = 0 39 VCC = 3 V 38 VCC = 3.3 V 37 VCC = 3.6 V 36 35 34 −55 −40 0 25 70 85 TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C Figure 16 Figure 15 14 0 www.ti.com 125 SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 DRIVER LOW-TO-HIGH PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 55 RS = 0 VCC = 3 V 50 45 40 VCC = 3.3 V 35 VCC = 3.6 V 30 25 20 15 10 −55 −40 0 25 70 85 125 t PHL− Driver High-to-Low Propagation Delay Time − ns t PLH − Driver Low-to-High Propagation Delay Time − ns TYPICAL CHARACTERISTICS DRIVER HIGH-TO-LOW PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 90 RS = 0 VCC = 3.6 V 85 80 75 VCC = 3.3 V 70 VCC = 3 V 65 60 55 50 −55 −40 RS = 10 kΩ 80 50 VCC = 3 V VCC = 3.3 V VCC = 3.6 V 40 30 20 10 0 −55 −40 0 25 85 125 70 85 125 DRIVER HIGH-TO-LOW PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE t PHL − Driver High-to-Low Propagation Delay Time − ns t PLH − Driver Low-to-High Propagation Delay Time − ns DRIVER LOW-TO-HIGH PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 60 70 Figure 18 Figure 17 70 25 TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C 90 0 TA − Free-Air Temperature − °C 150 RS = 10 kΩ VCC = 3.6 V 140 VCC = 3.3 V 130 VCC = 3 V 120 110 100 90 80 −55 −40 0 25 70 85 125 TA − Free-Air Temperature − °C Figure 19 Figure 20 www.ti.com 15 SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 DRIVER LOW-TO-HIGH PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 800 RS = 100 kΩ 700 VCC = 3 V 600 VCC = 3.3 V 500 VCC = 3.6 V 400 300 200 100 0 −55 −40 0 25 70 85 125 DRIVER HIGH-TO-LOW PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE t PHL− Driver High-to-Low Propagation Delay Time − ns t PLH − Driver Low-to-High Propagation Delay Time − ns TYPICAL CHARACTERISTICS 1000 RS = 100 kΩ VCC = 3.6 V 950 VCC = 3.3 V 900 850 VCC = 3 V 800 750 700 −55 −40 25 70 85 125 TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C Figure 22 Figure 21 DRIVER OUTPUT CURRENT vs SUPPLY VOLTAGE DIFFERENTIAL DRIVER OUTPUT FALL TIME vs Source Resistance (RS) 50 µs 1.50 t f − Differential Output Fall Time − 40 I O − Driver Output Current − mA 0 30 20 10 0 1.40 1.30 VCC = 3.3 V 1.20 1.10 VCC = 3.6 V 1.00 0.90 0.80 0.70 0.60 VCC = 3 V 0.50 0.40 0.30 0.20 0.10 −10 0 1 1.5 2 2.5 3 3.5 4 50 100 150 Rs − Source Resistance − kΩ VCC − Supply Voltage − V Figure 23 16 0 Figure 24 www.ti.com 200 SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 TYPICAL CHARACTERISTICS REFERENCE VOLTAGE vs REFERENCE CURRENT 3 V ref − Reference Voltage − V 2.5 2 VCC = 3.6 V 1.5 VCC = 3 V 1 0.5 0 −50 −5 5 50 Iref − Reference Current − µA Figure 25 APPLICATION INFORMATION This application provides information concerning the implementation of the physical medium attachment layer in a CAN network according to the ISO 11898 standard. It presents a typical application circuit and test results, as well as discussions on slope control, total loop delay, and interoperability in 5-V systems. introduction ISO 11898 is the international standard for high-speed serial communication using the controller area network (CAN) bus protocol. It supports multimaster operation, real-time control, programmable data rates up to 1 Mbps, and powerful redundant error checking procedures that provide reliable data transmission. It is suited for networking intelligent devices as well as sensors and actuators within the rugged electrical environment of a machine chassis or factory floor. The SN65HVD230Q family of 3.3-V CAN transceivers implement the lowest layers of the ISO/OSI reference model. This is the interface with the physical signaling output of the CAN controller of the Texas Instruments TMS320Lx240x 3.3-V DSPs, as illustrated in Figure 26. www.ti.com 17 SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 APPLICATION INFORMATION ISO 11898 Specification Implementation Application Specific Layer TMS320Lx2403/6/7 3.3-V DSP Logic Link Control Data-Link Layer Embedded Medium Access Control CAN Controller Physical Signaling Physical Layer Physical Medium Attachment SN65HVD230 Medium Dependant Interface CAN Bus−Line Figure 26. The Layered ISO 11898 Standard Architecture The SN65HVD230Q family of CAN transceivers are compatible with the ISO 11898 standard; this ensures interoperability with other standard-compliant products. application of the SN65HVD230Q Figure 27 illustrates a typical application of the SN65HVD230Q family. The output of a DSP’s CAN controller is connected to the serial driver input, pin D, and receiver serial output, pin R, of the transceiver. The transceiver is then attached to the differential bus lines at pins CANH and CANL. Typically, the bus is a twisted pair of wires with a characteristic impedance of 120 Ω, in the standard half-duplex multipoint topology of Figure 28. Each end of the bus is terminated with 120-Ω resistors in compliance with the standard to minimize signal reflections on the bus. 18 www.ti.com SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 APPLICATION INFORMATION Electronic Control Unit (ECU) TMS320Lx2403/6/7 CAN-Controller CANTX/IOPC6 CANRX/IOPC7 D R SN65HVD230 CANH CANL CAN Bus Line Figure 27. Details of a Typical CAN Node ECU 1 ECU 2 ECU n CANH 120 Ω CAN Bus Line 120 Ω CANL Figure 28. Typical CAN Network The SN65HVD230Q/231Q/232Q 3.3-V CAN transceivers provide the interface between the 3.3-V TMS320Lx2403/6/7 CAN DSPs and the differential bus line, and are designed to transmit data at signaling rates up to 1 Mbps as defined by the ISO 11898 standard. features of the SN65HVD230Q, SN65HVD231Q, and SN65HVD232Q The SN65HVD230Q/231Q/232Q are pin-compatible (but not functionally identical) with one another and, depending upon the application, may be used with identical circuit boards. These transceivers feature 3.3-V operation and standard compatibility with signaling rates up to 1 Mbps, and also offer 16-kV HBM ESD protection on the bus pins, thermal shutdown protection, bus fault protection, and open-circuit receiver failsafe. The failsafe design of the receiver assures a logic high at the receiver output if the bus wires become open circuited. If a high ambient operating environment temperature or excessive output current result in thermal shutdown, the bus pins become high impedance, while the D and R pins default to a logic high. www.ti.com 19 SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 APPLICATION INFORMATION features of the SN65HVD230Q, SN65HVD231Q, and SN65HVD232Q (continued) The bus pins are also maintained in a high-impedance state during low VCC conditions to ensure glitch-free power-up and power-down bus protection for hot-plugging applications. This high-impedance condition also means that an unpowered node will not disturb the bus. Transceivers without this feature usually have a very low output impedance. This results in a high current demand when the transceiver is unpowered, a condition that could affect the entire bus. operating modes RS (pin 8) of the SN65HVD230Q and SN65HVD231Q provides for three different modes of operation: high-speed mode, slope-control mode, and low-power standby mode. high-speed mode The high-speed mode can be selected by applying a logic low to Rs (pin 8). The high-speed mode of operation is commonly employed in industrial applications. High-speed allows the output to switch as fast as possible with no internal limitation on the output rise and fall slopes. The only limitations of the high-speed operation are cable length and radiated emission concerns, each of which is addressed by the slope control mode of operation. If the low-power standby mode is to be employed in the circuit, direct connection to a DSP output pin can be used to switch between a logic-low level (< 1 V) for high speed mode operation, and the logic-high level (> 0.75 VCC) for standby mode operation. Figure 29 shows a typical DSP connection, and Figure 30 shows the SN65HVD230Q driver output signal in high-speed mode on the CAN bus. SN65HVD230Q D GND VCC R 1 8 2 7 3 6 4 5 RS IOPF6 TMS320LF2406 or TMS320LF2407 CANH CANL Vref Figure 29. RS (Pin 8) Connection to a TMS320LF2406/07 for High-Speed or Standby Mode Operation 20 www.ti.com SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 APPLICATION INFORMATION high-speed mode (continued) 1 Mbps Driver Output NRZ Data 1 Figure 30. Typical SN65HVD230Q High-Speed Mode Output Waveform Into a 60-Ω Load slope-control mode Electromagnetic compatibility is essential in many applications using unshielded bus cable to reduce system cost. To reduce the electromagnetic interference generated by fast rise times and resulting harmonics, the rise and fall slopes of the SN65HVD230Q and SN65HVD231Q driver outputs can be adjusted by connecting a resistor from RS (pin 8) to ground or to a logic low voltage, as shown in Figure 31. The slope of the driver output signal is proportional to the pin’s output current. This slope control is implemented with an external resistor value of 10 kΩ to achieve a ≈ 15 V/µs slew rate, and up to 100 kΩ to achieve a ≈ 2.0 V/µs slew rate as displayed in Figure 32. Typical driver output waveforms from a pulse input signal with and without slope control are displayed in Figure 33. A pulse input is used rather than NRZ data to clearly display the actual slew rate. SN65HVD230Q D GND VCC R 1 8 2 7 3 6 4 5 RS 10 kΩ to 100 kΩ IOPF6 TMS320LF2406 or TMS320LF2407 CANH CANL Vref Figure 31. Slope-Control or Standby Mode Connection to a DSP www.ti.com 21 SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 APPLICATION INFORMATION DRIVER OUTPUT SIGNAL SLOPE vs SLOPE CONTROL RESISTANCE Driver Output Signal Slope − V/µs 25 20 15 10 5 0 0 10 4.7 20 30 40 50 33 60 47 70 6.8 10 15 22 Slope Control Resistance − kΩ 80 68 90 100 Figure 32. SN65HVD230Q Driver Output Signal Slope vs Slope Control Resistance Value RS = 0 Ω RS = 10 kΩ RS = 100 kΩ Figure 33. Typical SN65HVD230Q 250-kbps Output Pulse Waveforms With Slope Control 22 www.ti.com SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 APPLICATION INFORMATION standby mode (listen only mode) of the SN65HVD230Q If a logic high (> 0.75 VCC) is applied to RS (pin 8) in Figures 29 and 31, the circuit of the SN65HVD230Q enters a low-current, listen only standby mode during which the driver is switched off and the receiver remains active. In this listen only state, the transceiver is completely passive to the bus. It makes no difference if a slope control resistor is in place as shown in Figure 31. The DSP can reverse this low-power standby mode when the rising edge of a dominant state (bus differential voltage > 900 mV typical) occurs on the bus. The DSP, sensing bus activity, reactivates the driver circuit by placing a logic low (< 1.2 V) on RS (pin 8). the babbling idiot protection of the SN65HVD231Q Occasionally, a runaway CAN controller unintentionally sends messages that completely tie up the bus (what is referred to in CAN jargon as a babbling idiot). When this occurs, the DSP can engage the listen-only standby mode to disengage the driver and release the bus, even when access to the CAN controller has been lost. When the driver circuit is deactivated, its outputs default to a high-impedance state. sleep mode of the SN65HVD231Q The unique difference between the SN65HVD230Q and the SN65HVD231Q is that both driver and receiver are switched off in the SN65HVD231Q when a logic high is applied to RS (pin 8). The device remains in a very low power-sleep mode until the circuit is reactivated with a logic low applied to RS (pin 8). While in this sleep mode, the bus pins are in a high-impedance state, while the D and R pins default to a logic high. loop propagation delay Transceiver loop delay is a measure of the overall device propagation delay, consisting of the delay from the driver input to the differential outputs, plus the delay from the receiver inputs to its output. The loop delay of the transceiver displayed in Figure 34 increases accordingly when slope control is being used. This increased loop delay means that the total bus length must be reduced to meet the CAN bit-timing requirements of the overall system. The loop delay becomes ≈100 ns when employing slope control with a 10-kΩ resistor, and ≈500 ns with a 100-kΩ resistor. Therefore, considering that the rule-of-thumb propagation delay of typical bus cable is 5 ns/m, slope control with the 100-kΩ resistor decreases the allowable bus length by the difference between the 500-ns max loop delay and the loop delay with no slope control, 70.7 ns. This equates to (500–70.7 ns)/5 ns, or approximately 86 m less bus length. This slew-rate/bus length trade-off to reduce electromagnetic interference to adjoining circuits from the bus can also be solved with a high-quality shielded bus cable. www.ti.com 23 SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 APPLICATION INFORMATION Figure 34. 70.7-ns Loop Delay Through the SN65HVD230Q With RS = 0 24 www.ti.com SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 APPLICATION INFORMATION interoperability with 5-V CAN systems It is essential that the 3.3-V SN65HVD230Q family performs seamlessly with 5-V transceivers because of the large number of 5-V devices installed. Figure 35 displays a test bus of a 3.3-V node with the SN65HVD230Q, and three 5-V nodes: one for each of TI’s SN65LBC031 and UC5350 transceivers, and one using a competitor X250 transceiver. Tektronix HFS−9003 Pattern Generator Tektronix 784D Oscilloscope Trigger Input Tektronix P6243 Single-Ended Probes One Meter Belden Cable #82841 120 Ω 120 Ω SN65HVD230Q SN65LBC031 UC5350 Competitor X250 HP E3516A 5-V Power Supply HP E3516A 3.3-V Power Supply Figure 35. 3.3-V/5-V CAN Transceiver Test Bed www.ti.com 25 SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 APPLICATION INFORMATION Driver Input CAN Bus Receiver Output Figure 36. SN65HVD230Q’s Input, CAN Bus, and X250’s RXD Output Waveforms Figure 36 displays the SN65HVD230Q’s input signal, the CAN bus, and the competitor X250’s receiver output waveforms. The input waveform from the Tektronix HFS-9003 Pattern Generator in Figure 35 to the SN65HVD230Q is a 250-kbps pulse for this test. The circuit is monitored with Tektronix P6243, 1-GHz single-ended probes in order to display the CAN dominant and recessive bus states. Figure 36 displays the 250-kbps pulse input waveform to the SN65HVD230Q on channel 1. Channels 2 and 3 display CANH and CANL respectively, with their recessive bus states overlaying each other to clearly display the dominant and recessive CAN bus states. Channel 4 is the receiver output waveform of the competitor X250. 26 www.ti.com PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN65HVD230QD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HV230Q SN65HVD230QDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HV230Q SN65HVD230QDG4Q1 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 230Q1 SN65HVD230QDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HV230Q SN65HVD230QDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HV230Q SN65HVD230QDRG4Q1 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 230Q1 SN65HVD231QD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HV231Q SN65HVD231QDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HV231Q SN65HVD231QDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HV231Q SN65HVD231QDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HV231Q SN65HVD231QDRG4Q1 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 231Q1 SN65HVD231QDRQ1 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 231Q1 SN65HVD232QD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HV232Q SN65HVD232QDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HV232Q SN65HVD232QDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HV232Q SN65HVD232QDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HV232Q SN65HVD232QDRG4Q1 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 232Q1 SN65HVD232QDRQ1 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 232Q1 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of