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SN65HVD233, SN65HVD234, SN65HVD235
SLLS557H – NOVEMBER 2002 – REVISED NOVEMBER 2018
SN65HVD23x 3.3-V CAN Bus Transceivers
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
The SN65HVD233, SN65HVD234, and SN65HVD235
are used in applications employing the controller area
network (CAN) serial communication physical layer in
accordance with the ISO 11898 standard. As a CAN
transceiver, each provides transmit and receive
capability between the differential CAN bus and a
CAN controller, with signaling rates up to 1 Mbps.
1
•
•
•
•
•
•
•
Single 3.3-V Supply Voltage
Bus Pins Fault Protection Exceeds ±36 V
Bus Pins ESD Protection Exceeds ±16 kV HBM
Compatible With ISO 11898-2
GIFT/ICT Compliant
Data Rates up to 1 Mbps
Extended –7 V to 12 V Common Mode Range
High-Input Impedance Allows for 120 Nodes
LVTTL I/Os are 5-V Tolerant
Adjustable Driver Transition Times for Improved
Emissions Performance
Unpowered Node Does Not Disturb the Bus
Low Current Standby Mode, 200-μA (Typical)
SN65HVD233: Loopback Mode
SN65HVD234: Ultra Low Current Sleep Mode
– 50-nA Typical Current Consumption
SN65HVD235: Autobaud Loopback Mode
Thermal Shutdown Protection
Power up and Down With Glitch-Free Bus Inputs
and Outputs
– High-Input Impedance With Low VCC
– Monolithic Output During Power Cycling
Designed for operation in especially harsh
environments, the devices feature cross-wire
protection, overvoltage protection up to ±36 V, loss of
ground
protection,
overtemperature
(thermal
shutdown) protection, and common-mode transient
protection of ±100 V. These devices operate over a
wide –7 V to 12 V common-mode range. These
transceivers are the interface between the host CAN
controller on the microprocessor and the differential
CAN bus used in industrial, building automation,
transportation, and automotive applications.
Device Information(1)
PART NUMBER
SN65HVD234
SOIC (8)
4.90 mm × 3.91 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Block Diagram
VCC
VCC
VCC
VCC
D
BIAS UNIT
•
•
•
•
Industrial Automation, Control, Sensors, and Drive
Systems
Motor and Robotic Control
Building and Climate Control (HVAC)
Backplane Communication and Control
CAN Bus Standards such as CANopen,
DeviceNet, CAN Kingdom, NMEA 2000,
SAE J1939
BODY SIZE (NOM)
SN65HVD235
2 Applications
•
PACKAGE
SN65HVD233
VCC
RS
LBK / EN /AB
SLOPE CONTROL
and MODE
LOGIC
R
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN65HVD233, SN65HVD234, SN65HVD235
SLLS557H – NOVEMBER 2002 – REVISED NOVEMBER 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
1
1
1
2
4
4
5
5
Absolute Maximum Ratings ..................................... 5
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 6
Power Dissipation Ratings ........................................ 6
Electrical Characteristics: Driver ............................... 7
Electrical Characteristics: Receiver .......................... 8
Switching Characteristics: Driver .............................. 8
Switching Characteristics: Receiver.......................... 9
Switching Characteristics: Device ........................... 9
Typical Characteristics .......................................... 10
9 Parameter Measurement Information ................ 12
10 Detailed Description ........................................... 19
10.1
10.2
10.3
10.4
Overview ...............................................................
Functional Block Diagrams ...................................
Feature Description...............................................
Device Functional Modes......................................
19
19
19
21
11 Application and Implementation........................ 23
11.1 Application Information.......................................... 23
11.2 Typical Application ................................................ 24
11.3 System Example ................................................... 26
12 Power Supply Recommendations ..................... 28
13 Layout................................................................... 28
13.1 Layout Guidelines ................................................. 28
13.2 Layout Example .................................................... 29
14 Device and Documentation Support ................. 30
14.1
14.2
14.3
14.4
14.5
14.6
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
30
30
30
30
30
30
15 Mechanical, Packaging, and Orderable
Information ........................................................... 30
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (January 2015) to Revision H
•
Page
Deleted: "ISO 11783" from the last Application Bullet............................................................................................................ 1
Changes from Revision F (August 2008) to Revision G
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
•
Changed the Functional Block Diagrams ............................................................................................................................... 4
•
Added the THERMAL SHUTDOWN paragraph to the Application Information section ....................................................... 21
•
Changed the BUS CABLE paragraph to BUS LOADING, LENGTH AND NUMBER OF NODES paragraph in the
Application Information section............................................................................................................................................. 24
•
Added the CAN TERMINATION paragraph to the Application Information section ............................................................. 24
Changes from Revision E (October 2007) to Revision F
•
Page
Changed Figure 17, Receiver Test Circuit and Voltage Waveform. From: CL = 50 pF ±20% to: CL = 15 pF ±20% ........... 13
Changes from Revision D (June 2005) to Revision E
Page
•
Added 60-Ω load test condition to Figure 3 ......................................................................................................................... 10
•
Deleted INTEROPERABILITY WITH 5-V CAN SYSTEMS section...................................................................................... 26
•
Added ISO 11898 COMPLIANCE OF SN65HVD230 FAMILY OF 3.3-V CAN TRANSCEIVERS section .......................... 26
2
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Product Folder Links: SN65HVD233 SN65HVD234 SN65HVD235
SN65HVD233, SN65HVD234, SN65HVD235
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SLLS557H – NOVEMBER 2002 – REVISED NOVEMBER 2018
Changes from Revision C (March 2005) to Revision D
•
Page
Added Features Bullet: GIFT/ICT Compliant (SN65HVD234)................................................................................................ 1
Changes from Revision B (June 2003) to Revision C
•
Page
Added IO, Receiver output current to the Abs Max Table ...................................................................................................... 5
Changes from Revision A (March 2003) to Revision B
Page
•
Changed the data sheet from Product Preview to Production for part number SN65HVD234 and SN65HVD235. .............. 1
•
Changed the APPLICATION INFORMATION section.......................................................................................................... 23
Changes from Original (November 2002) to Revision A
•
Page
Changed the data sheet from Product Preview to Production for part number SN65HVD233.............................................. 1
Copyright © 2002–2018, Texas Instruments Incorporated
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3
SN65HVD233, SN65HVD234, SN65HVD235
SLLS557H – NOVEMBER 2002 – REVISED NOVEMBER 2018
www.ti.com
5 Description (continued)
Modes: The RS pin (pin 8) of the SN65HVD233, SN65HVD234, and SN65HVD235 provides three modes of
operation: high-speed, slope control, and low-power standby mode. The high-speed mode of operation is
selected by connecting pin 8 directly to ground, allowing the driver output transistors to switch on and off as fast
as possible with no limitation on the rise and fall slope. The rise and fall slope can be adjusted by connecting a
resistor between the RS pin and ground. The slope will be proportional to the pin's output current. With a resistor
value of 10 kΩ the device driver will have a slew rate of ~15 V/μs and with a value of 100 kΩ the device will have
~2.0 V/μs slew rate. For more information about slope control, refer to Feature Description.
The SN65HVD233, SN65HVD234, and SN65HVD235 enter a low-current standby (listen only) mode during
which the driver is switched off and the receiver remains active if a high logic level is applied to the RS pin. If the
local protocol controller needs to transmit a message to the bus it will have to return the device to either highspeed mode or slope control mode via the RS pin.
Loopback (SN65HVD233): A logic high on the loopback (LBK) pin (pin 5) of the SN65HVD233 places the bus
output and bus input in a high-impedance state. Internally, the D to R path of the device remains active and
available for driver to receiver loopback that can be used for self-diagnostic node functions without disturbing the
bus. For more information on the loopback mode, refer to Feature Description.
Ultra Low-Current Sleep (SN65HVD234): The SN65HVD234 enters an ultra low-current sleep mode in which
both the driver and receiver circuits are deactivated if a low logic level is applied to EN pin (pin 5). The device
remains in this sleep mode until the circuit is reactivated by applying a high logic level to pin 5.
Autobaud Loopback (SN65HVD235): The AB pin (pin 5) of the SN65HVD235 implements a bus listen-only
loopback feature which allows the local node controller to synchronize its baud rate with that of the CAN bus. In
autobaud mode, the bus output of the driver is placed in a high-impedance state while the bus input of the
receiver remains active. There is an internal D pin to R pin loopback to assist the controller in baud rate
detection, or the autobaud function. For more information on the autobaud mode, refer to Feature Description.
6 Device Comparison Table (1)
LOW POWER MODE
SLOPE
CONTROL
DIAGNOSTIC
LOOPBACK
AUTOBAUD
LOOPBACK
SN65HVD233D
200-μA standby mode
Adjustable
Yes
No
SN65HVD234D
200-μA standby mode or 50-nA sleep mode
Adjustable
No
No
SN65HVD235D
200-μA standby mode
Adjustable
No
Yes
PART NUMBER
(1)
4
For the most current package and ordering information, see Mechanical, Packaging, and Orderable Information, or see the TI web site
at www.ti.com.
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SLLS557H – NOVEMBER 2002 – REVISED NOVEMBER 2018
7 Pin Configuration and Functions
SN65HVD233D
(Marked as VP233)
(TOP VIEW)
D
GND
VCC
R
1
8
2
7
3
6
4
5
SN65HVD234D
(Marked as VP234)
(TOP VIEW)
RS
CANH
CANL
LBK
D
GND
VCC
R
1
8
2
7
3
6
4
5
SN65HVD235D
(Marked as VP235)
(TOP VIEW)
D
GND
VCC
R
RS
CANH
CANL
EN
1
8
2
7
3
6
4
5
RS
CANH
CANL
AB
Pin Functions
PIN
NAME
NO.
TYPE
CAN transmit data input (LOW for dominant and HIGH for recessive bus states), also called TXD, driver
input
D
1
GND
2
GND
VCC
3
Supply
R
4
O
CAN receive data output (LOW for dominant and HIGH for recessive bus states), also called RXD, receiver
output
I
SN65HVD233: Loopback mode input pin
5
I
SN65HVD234: Enable input pin. Logic high for enabling a normal mode (high speed or slope control)
mode. Logic low for sleep mode.
I
SN65HVD235: Autobaud loopback mode input pin
CANL
6
I/O
Low level CAN bus line
CANH
7
I/O
High level CAN bus line
RS
8
I
LBK
EN
AB
I
DESCRIPTION
Ground connection
Transceiver 3.3-V supply voltage
Mode select pin: strong pulldown to GND = high speed mode, strong pullup to VCC = low power mode, 10kΩ to 100-kΩ pulldown to GND = slope control mode
8 Specifications
8.1 Absolute Maximum Ratings (1) (2)
over operating free-air temperature range unless otherwise noted
MIN
VCC
MAX
UNIT
Supply voltage
–0.3
7
V
Voltage at any bus terminal (CANH or CANL)
–36
36
V
Voltage input, transient pulse, CANH and CANL, through 100 Ω (see
Figure 18)
–100
100
V
VI
Input voltage, (D, RS, EN, LBK, AB)
–0.5
7
V
VO
Output voltage
–0.5
7
V
IO
Receiver output current
–10
10
mA
Continuous total power dissipation
See Power Dissipation Ratings
TJ
Operating junction temperature
150
Tstg
Storage temperature
125
(1)
(2)
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground pin.
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SN65HVD233, SN65HVD234, SN65HVD235
SLLS557H – NOVEMBER 2002 – REVISED NOVEMBER 2018
www.ti.com
8.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Human body model (HBM), per ANSI/ESDA/JEDEC JS001 (1)
Electrostatic
discharge
CANH, CANL and GND
UNIT
±16000
All pins
3000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
VCC
Supply voltage
Voltage at any bus terminal (separately or common mode)
MIN
MAX
3
3.6
–7
12
UNIT
VIH
High-level input voltage
D, EN, AB, LBK
2
5.5
VIL
Low-level input voltage
D, EN, AB, LBK
0
0.8
VID
Differential input voltage between CANH and CANL
–6
6
0
100
kΩ
0.75 VCC
5.5
V
Resistance from RS to ground
VI(Rs)
Input Voltage at RS for standby
IOH
High-level output current
IOL
Low-level output current
TJ
Operating junction temperature
TA
(1)
Operating free-air temperature
Driver
–50
Receiver
–10
mA
Driver
50
Receiver
10
HVD233, HVD234, HVD235
(1)
HVD233, HVD234, HVD235
V
–40
mA
150
°C
125
°C
Maximum free-air temperature operation is allowed as long as the device maximum junction temperature is not exceeded.
8.4 Thermal Information
over operating free-air temperature range (unless otherwise noted)
PARAMETERS
TEST CONDITIONS
RθJA
Junction-to-ambient thermal resistance (1)
RθJB
Junction-to-board thermal resistance
RθJC
Junction-to-case thermal resistance
Average power dissipation
T(SD)
Thermal shutdown junction temperature
(1)
(2)
(3)
UNIT
185
High-K (3) board, no air flow
101
High-K (3) board, no air flow
82.8
°C/W
26.5
°C/W
36.4
mW
170
°C
RL = 60 Ω, RS at 0 V, input to D a 1-MHz 50% duty
cycle square wave VCC at 3.3 V, TA = 25°C
P(AVG)
VALUE
Low-K (2) board, no air flow
°C/W
See SZZA003 for an explanation of this parameter.
JESD51-3 low effective thermal conductivity test board for leaded surface mount packages.
JESD51-7 high effective thermal conductivity test board for leaded surface mount packages.
8.5 Power Dissipation Ratings
PACKAGE
(1)
6
CIRCUIT
BOARD
TA ≤ 25°C
POWER RATING
DERATING FACTOR (1)
ABOVE TA = 25°C
TA = 85°C
POWER RATING
TA = 125°C
POWER RATING
D
Low-K
596.6 mW
5.7 mW/°C
255.7 mW
28.4 mW
D
High-K
1076.9 mW
10.3 mW/°C
461.5 mW
51.3 mW
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
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SLLS557H – NOVEMBER 2002 – REVISED NOVEMBER 2018
8.6 Electrical Characteristics: Driver
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VO(D)
Bus output voltage
(Dominant)
CANH
VO
Bus output voltage
(Recessive)
CANH
VOD(D)
VOD
CANL
CANL
Differential output voltage (Dominant)
Differential output voltage (Recessive)
VOC(pp)
MIN TYP (1)
TEST CONDITIONS
Peak-to-peak common-mode output voltage
IIH
High-level input current
D, EN, LBK,
AB
IIL
Low-level input current
D, EN, LBK,
AB
D at 0 V, RS at 0 V, See Figure 12 and
Figure 13
2.45
VCC
0.5
1.25
2.3
D at 3 V, RS at 0 V, See Figure 12 and
Figure 13
D at 0 V, RS at 0 V, See Figure 12 and
Figure 13
1.5
2
3
D at 0 V, RS at 0 V, See Figure 13 and
Figure 14
1.2
2
3
CO
Output capacitance
IIRs(s)
RS input current for standby
D at 3 V, RS at 0 V, See Figure 12 and
Figure 13
–120
12
D at 3 V, RS at 0 V, No Load
–0.5
0.05
See Figure 21
1
(1)
Supply current
mV
V
V
D = 2 V or EN = 2 V or LBK = 2 V or AB = 2 V
–30
30
μA
D = 0.8 V or EN = 0.8 V or LBK = 0.8 V or AB
= 0.8 V
–30
30
μA
–250
VCANL = –7 V, CANH Open, See Figure 26
1
–1
VCANL = 12 V, CANH Open, See Figure 26
ICC
V
V
VCANH = 12 V, CANL Open, See Figure 26
Short-circuit output current
UNIT
V
2.3
VCANH = –7 V, CANL Open, See Figure 26
IOS
MAX
mA
250
See receiver input capacitance
RS at 0.75 VCC
–10
μA
Sleep
EN at 0 V, D at VCC, RS at 0 V or VCC
0.05
2
Standby
RS at VCC, D at VCC, AB at 0 V, LBK at 0 V,
EN at VCC
200
600
Dominant
D at 0 V, No Load, AB at 0 V, LBK at 0 V,
RS at 0 V, EN at VCC
6
Recessive
D at VCC, No Load, AB at 0 V, LBK at 0 V,
RS at 0 V, EN at VCC
6
μA
mA
All typical values are at 25°C and with a 3.3-V supply.
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SLLS557H – NOVEMBER 2002 – REVISED NOVEMBER 2018
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8.7 Electrical Characteristics: Receiver
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Hysteresis voltage (VIT+ – VIT–)
VOH
High-level output voltage
IO = –4 mA, See Figure 17
VOL
Low-level output voltage
IO = 4 mA, See Figure 17
AB at 0 V, LBK at 0 V, EN at VCC, See Table 1
CANH or CANL at 12 V,
VCC at 0 V
Bus input current
MAX
750
900
500
650
CANH or CANL at –7 V
CANH or CANL at –7 V,
VCC at 0 V
0.4
Other bus pin at 0 V,
D at 3 V, AB at 0 V,
LBK at 0 V, RS at 0 V,
EN at VCC
150
500
200
600
–610
–150
–450
–130
Input capacitance (CANH or CANL)
Pin-to-ground, VI = 0.4 sin (4E6πt) + 0.5 V, D at 3 V,
AB at 0 V, LBK at 0 V, EN at VCC
40
CID
Differential input capacitance
Pin-to-pin, VI = 0.4 sin (4E6πt) + 0.5 V, D at 3 V,
AB at 0 V, LBK at 0 V, EN at VCC
20
RID
Differential input resistance
RIN
Input resistance (CANH or CANL) to
ground
(1)
Supply current
mV
2.4
CI
ICC
UNIT
100
CANH or CANL at 12 V
II
MIN TYP (1)
D at 3 V, AB at 0 V, LBK at 0 V, EN at VCC
V
μA
pF
40
100
20
50
Sleep
EN at 0 V, D at VCC, RS at 0 V or VCC
0.05
2
Standby
RS at VCC, D at VCC, AB at 0 V, LBK at 0 V, EN at VCC
200
600
Dominant
D at 0 V, No Load, RS at 0 V, LBK at 0 V, AB at 0 V,
EN at VCC
6
Recessive
D at VCC, No Load, RS at 0 V, LBK at 0 V, AB at 0 V,
EN at VCC
6
kΩ
μA
mA
All typical values are at 25°C and with a 3.3-V supply.
8.8 Switching Characteristics: Driver
over operating free-air temperature range (unless otherwise noted)
TYP (1)
MAX
RS at 0 V, See Figure 15
35
85
RS with 10 kΩ to ground, See Figure 15
70
125
RS with 100 kΩ to ground, See Figure 15
500
870
70
120
RS with 10 kΩ to ground, See Figure 15
130
180
RS with 100 kΩ to ground, See Figure 15
870
1200
PARAMETER
TEST CONDITIONS
Propagation delay time,
low-to-high-level output
tPLH
MIN
RS at 0 V, See Figure 15
Propagation delay time,
high-to-low-level output
tPHL
tsk(p)
Pulse skew (|tPHL – tPLH|)
tr
Differential output signal rise time
tf
Differential output signal fall time
tr
Differential output signal rise time
tf
Differential output signal fall time
tr
Differential output signal rise time
tf
Differential output signal fall time
ten(s)
Enable time from standby to dominant
ten(z)
Enable time from sleep to dominant
RS at 0 V, See Figure 15
35
RS with 10 kΩ to ground, See Figure 15
60
RS with 100 kΩ to ground, See Figure 15
(1)
8
RS at 0 V, See Figure 15
RS with 10 kΩ to ground, See Figure 15
RS with 100 kΩ to ground, See Figure 15
See Figure 19 and Figure 20
UNIT
ns
ns
ns
370
20
70
20
70
30
135
30
135
350
1400
350
1400
0.6
1.5
1
5
ns
ns
ns
μs
All typical values are at 25°C and with a 3.3-V supply.
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SLLS557H – NOVEMBER 2002 – REVISED NOVEMBER 2018
8.9 Switching Characteristics: Receiver
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP (1)
MAX
UNIT
tPLH
Propagation delay time, low-to-high-level output
35
60
tPHL
Propagation delay time, high-to-low-level output
35
60
tsk(p)
Pulse skew (|tPHL – tPLH|)
tr
Output signal rise time
2
5
tf
Output signal fall time
2
5
MIN TYP (1)
MAX
See Figure 23
7.5
12
ns
See Figure 24
10
20
ns
See Figure 25
35
60
ns
(1)
See Figure 17
7
ns
All typical values are at 25°C and with a 3.3-V supply.
8.10 Switching Characteristics: Device
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
t(LBK)
Loopback delay, driver input to
receiver output
t(AB1)
Loopback delay, driver input to
receiver output
HVD233
HVD235
t(AB2)
Loopback delay, bus input to
receiver output
t(loop1)
Total loop delay, driver input to receiver output,
recessive to dominant
RS at 0 V, See Figure 22
70
135
RS with 10 kΩ to ground, See Figure 22
105
190
RS with 100 kΩ to ground, See Figure 22
535
1000
70
135
RS at 0 V, See Figure 22
t(loop2)
(1)
UNIT
Total loop delay, driver input to receiver output,
dominant to recessive
RS with 10 kΩ to ground, See Figure 22
105
190
RS with 100 kΩ to ground, See Figure 22
535
1000
ns
ns
All typical values are at 25°C and with a 3.3-V supply.
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8.11 Typical Characteristics
t (LOOPL2)− Dominant−To−Recessive Loop Time − ns
t (LOOPL1)− Ressive−To−Dominant Loop Time − ns
Rs, LBK, AB = 0 V; EN = VCC
90
Rs, LBK, AB = 0 V
EN = VCC
85
VCC = 3 V
80
VCC = 3.3 V
VCC = 3.6 V
75
70
65
60
5
80
45
TA − Free-Air Temperature − °C
−40
125
Figure 1. Recessive-to-Dominant Loop Time vs Free-Air
Temperature
Rs, LBK, AB = 0 V
EN = VCC
90
85
VCC = 3.6 V
80
VCC = 3.3 V
75
70
VCC = 3 V
65
−40
45
5
80
TA − Free-Air Temperature − °C
125
Figure 2. Dominant-to-Recessive Loop Time vs Free-Air
Temperature
20
160
VCC = 3.3 V,
Rs, LBK, AB = 0 V,
EN = VCC,
TA = 25°C,
60-W Load
19
VCC = 3.3 V,
Rs, LBK, AB = 0 V,
EN = VCC,
TA = 25°C
140
I OL − Driver Output Current − mA
I CC − Supply Current − mA
95
18
17
16
120
100
80
60
40
20
15
200
0
300
500
700
1000
0
1
2
3
VOL − Low-Level Output Voltage − V
f − Frequency − kbps
VCC = 3.3 V
TA = 25°C
60-Ω Load
Figure 3. Supply Current vs Frequency
2.2
VCC = 3.3 V,
Rs, LBK, AB = 0 V,
EN = VCC,
TA = 25°C
0.1
VCC = 3.6 V
0.08
0.06
0.04
0.02
0
0
VCC = 3.3 V
0.5
1
1.5
2
2.5
3
VOH − High-Level Output Voltage − V
3.5
2
VCC = 3.3 V
1.8
VCC = 3 V
1.6
1.4
RL = 60 Ω
Rs, LBK, AB = 0 V
EN = VCC
1.2
1
−40
5
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45
80
125
TA − Free-Air Temperature − °C
TA = 25°C
Figure 5. Driver High-Level Output Current vs High-Level
Output Voltage
10
TA = 25°C
Figure 4. Driver Low-Level Output Current vs Low-Level
Output Voltage
VOD − Differential Output Voltage − V
I OH − Driver High-Level Output Current − mA
0.12
VCC = 3.3 V
4
RL = 60-Ω
Figure 6. Differential Output Voltage vs Free-Air
Temperature
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Typical Characteristics (continued)
45
44
Rs, LBK, AB = 0 V
EN = VCC
See Figure 6
43
42
VCC = 3.3 V
VCC = 3 V
41
40
39
38
VCC = 3.6 V
37
36
35
−40
5
45
80
TA − Free-Air Temperature − °C
38
t PHL− Receiver High-To-Low Propagation Delay − ns
t PLH − Receiver Low-To-High Propagation Delay − ns
Rs, LBK, AB = 0 V; EN = VCC
125
Rs, LBK, AB = 0 V
EN = VCC
See Figure 6
37
36
35
VCC = 3 V
34
VCC = 3.3 V
33
VCC = 3.6 V
32
−40
5
45
80
TA − Free-Air Temperature − °C
See Figure 3
See Figure 3
Figure 8. Receiver High-to-Low Propagation Delay vs FreeAir Temperature
55
t PHL− Driver High-To-Low Proragation Delay − ns
t PLH − Driver Low-To-High Propagation Delay − ns
Figure 7. Receiver Low-to-High Propagation Delay vs FreeAir Temperature
50
Rs, LBK, AB = 0 V
EN = VCC
See Figure 4
VCC = 3.3 V
VCC = 3 V
45
40
35
VCC = 3.6 V
30
25
−40
5
45
125
80
65
60
VCC = 3 V
55
50
VCC = 3.3 V
45
VCC = 3.6 V
40
Rs, LBK, AB = 0 V
EN = VCC
See Figure 4
35
30
−40
125
TA − Free-Air Temperature − °C
5
45
80
TA − Free-Air Temperature − °C
125
See Figure 1
See Figure 1
Figure 9. Driver Low-to-High Propagation Delay vs Free-Air
Temperature
Figure 10. Driver High-to-Low Propagation Delay vs Free-Air
Temperature
35
Rs, LBK, AB = 0 V,
EN = VCC,
TA = 25°C
RL = 60 Ω
I O − Driver Output Current − mA
30
25
20
15
10
5
0
−5
0
0.6
RL = 60-Ω
1.2
1.8
2.4
VCC − Supply Voltage − V
3
3.6
TA = 25°C
Figure 11. Driver Output Current vs Supply Voltage
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9 Parameter Measurement Information
IO(CANH)
II
D
60 Ω ±1%
VO(CANH)
VOD
VI
VO(CANH) + VO(CANL)
IIRs
RS
2
VOC
IO(CANL)
+
VO(CANL)
VI(Rs)
-
Figure 12. Driver Voltage, Current, and Test Definition
Dominant
Recessive
≈3V
VO(CANH)
≈ 2.3 V
≈1V
VO(CANL)
Figure 13. Bus Logic State Voltage Definitions
D
VI
CANH
330 Ω ±1%
VOD
60 Ω ±1%
+
_
RS
CANL
-7 V ≤ VTEST ≤ 12 V
330 Ω ±1%
Figure 14. Driver VOD
CANH
CL = 50 pF ±20%
(see Note B)
D
VI
RL = 60 Ω ±1%
VCC/2
VI
VO
0V
tPLH
tPHL
RS +
(see Note A)
VI(Rs)
-
VO
VCC
VCC/2
0.9 V
VO(D)
90%
0.5 V
10%
CANL
tr
VO(R)
tf
A.
The input pulse is supplied by a generator having the following characteristics: Pulse repetition rate (PRR) ≤ 125 kHz,
50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
B.
CL includes fixture and instrumentation capacitance.
Figure 15. Driver Test Circuit and Voltage Waveforms
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Parameter Measurement Information (continued)
CANH
R
VIC =
VI(CANH)
VI(CANH + VI(CANL)
IO
VID
2
VO
CANL
VI(CANL)
Figure 16. Receiver Voltage and Current Definitions
2.9 V
CANH
2.2 V
VI
R
1.5 V
IO
VI
(see Note A)
1.5 V
CANL
2.2 V
tPLH
CL = 15 pF ±20%
(see Note B)
tPHL
VO
90%
50%
10%
VO
90%
tr
VOH
50%
10%
VOL
tf
A.
The input pulse is supplied by a generator having the following characteristics: Pulse repetition rate (PRR) ≤ 125 kHz,
50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
B.
CL includes fixture and instrumentation capacitance.
Figure 17. Receiver Test Circuit and Voltage Waveforms
Table 1. Differential Input Voltage Threshold Test
INPUT
OUTPUT
VCANH
VCANL
–6.1 V
–7 V
L
12 V
11.1 V
L
–1 V
–7 V
L
MEASURED
R
|VID|
900 mV
900 mV
VOL
6V
12 V
6V
L
6V
–6.5 V
–7 V
H
500 mV
12 V
11.5 V
H
500 mV
–7 V
–1 V
H
6V
12 V
H
6V
Open
Open
H
X
VOH
6V
CANH
R
100 Ω
Pulse Generator
15 µs Duration
1% Duty Cycle
tr, tf ≤ 100 ns
CANL
D at 0 V or VCC
Rs, AB, EN, LBK, at 0 V or VCC
NOTE: This test is conducted to test survivability only. Data stability at the R output is not specified.
Figure 18. Test Circuit, Transient Overvoltage Test
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HVD234
HVD233 or HVD235
RS
VI
CANH
D
0V
AB or LBK
VI
60 Ω ±1%
0V
VCC
CANL
R
+
15 pF ±20%
-
CANH
D
60 Ω ±1%
EN
CANL
VO
VO
+
RS
-
15 pF ±20%
VCC
50%
VI
0V
VOH
50%
VO
VOL
ten(s)
NOTE: All VI input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 6 ns, pulse repetition rate
(PRR) = 125 kHz, 50% duty cycle.
Figure 19. Ten(s) Test Circuit and Voltage Waveforms
HVD234
RS
D
0V
VI
VCC
CANH
60 Ω ±1%
VI
0V
EN
VOH
CANL
50%
VO
R
VO
+
50%
VOL
ten(z)
15 pF ±20%
-
NOTE: All VI input pulses are supplied by a generator having the following characteristics:
tr or tf ≤ 6 ns, pulse repetition rate (PRR) = 50 kHz, 50% duty cycle.
Figure 20. Ten(z) Test Circuit and Voltage Waveforms
CANH
VI
27 Ω ±1%
VOC(PP)
D
VOC
RS
CANL
27 Ω ±1%
VOC
50 pF ±20%
NOTE: All VI input pulses are supplied by a generator having the following characteristics:
tr or tf ≤ 6 ns, pulse repetition rate (PRR) = 125 kHz, 50% duty cycle.
Figure 21. VOC(pp) Test Circuit and Voltage Waveforms
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0Ω, 10 kΩ,
or 100 kΩ ±5%
DUT
RS
CANH
D
VI
60 Ω ±1%
LBK or AB
HVD233/235
EN
HVD234
R
VCC
+
VO
-
VCC
50%
VI
50%
0V
t(loop2)
CANL
t(loop1)
50%
VO
VOH
50%
VOL
15 pF ±20%
NOTE: All VI input pulses are supplied by a generator having the following characteristics:
tr or tf ≤ 6 ns, pulse repetition rate (PRR) = 125 kHz, 50% duty cycle.
Figure 22. T(loop) Test Circuit and Voltage Waveforms
RS
HVD233
+
VOD
-
D
VI
LBK
VCC
VCC
CANH
50%
VI
50%
0V
60 Ω ±1%
CANL
t(LBK1)
t(LBK2)
50%
VO
R
VO
VOL
t(LBK) = t(LBK1) = t(LBK2)
VOD
+
VOH
50%
≈ 2.3 V
15 pF ±20%
-
NOTE: All VI input pulses are supplied by a generator having the following characteristics:
tr or tf ≤ 6 ns, pulse repetition rate (PRR) = 125 kHz, 50% duty cycle.
Figure 23. T(LBK) Test Circuit and Voltage Waveforms
RS
VI
VCC
D
HVD235
CANH
+
60 Ω ±1%
VOD
CANL
≈ 2.3 V
VOD
VCC
50%
VI
0V
t(ABH)
AB
VO
R
50%
t(ABL)
50%
VOH
50%
VOL
t(AB1) = t(ABH) = t(ABL)
VO
+
-
15 pF ±20%
NOTE: All VI input pulses are supplied by a generator having the following characteristics: tr
or tf ≤ 6 ns, pulse repetition rate (PRR) = 125 kHz, 50% duty cycle.
Figure 24. T(AB1) Test Circuit and Voltage Waveforms
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RS
HVD235
CANH
D
VCC
VI
2.9 V
60 Ω ±1%
CANL
AB
VCC
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2.2 V
2.2 V
VI
1.5 V
t(ABH)
1.5 V
t(ABL)
50%
VO
VOH
50%
VOL
R
t(AB2) = t(ABH) = t(ABL)
VO
+
-
15 pF ±20%
NOTE: All VI input pulses are supplied by a generator having the following characteristics:
tr or tf ≤ 6 ns, pulse repetition rate (PRR) = 125 kHz, 50% duty cycle.
Figure 25. T(AB2) Test Circuit and Voltage Waveforms
IOS
IOS
D
0 V or VCC
15 s
CANH
IOS
+
_
0V
VI
12 V
CANL
0V
0V
VI
10 µs
and
VI
-7 V
Figure 26. IOS Test Circuit and Waveforms
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3.3 V
R2 ± 1%
R1 ± 1%
TA = 25°C
VCC = 3.3 V
CANH
+
VID
CANL -
R
R2 ± 1%
Vac
R1 ± 1%
VI
The R Output State Does Not Change During
Application of the Input Waveform.
VID
500 mV
900 mV
R1
50 Ω
50 Ω
R2
280 Ω
130 Ω
12 V
VI
-7 V
NOTE: All input pulses are supplied by a generator with f ≤ 1.5 MHz.
Figure 27. Common-Mode Voltage Rejection
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RS INPUT
D INPUT
CANH INPUT
VCC
VCC
VCC
110 kΩ
100 kΩ
INPUT
1 kΩ
9 kΩ
45 kΩ
INPUT
9V
+
_
INPUT
CANH and CANL OUTPUTS
CANL INPUT
VCC
9 kΩ
40 V
VCC
R OUTPUT
VCC
9 kΩ
110 kΩ
5Ω
45 kΩ
INPUT
OUTPUT
OUTPUT
9 kΩ
40 V
9V
40 V
EN INPUT
LBK or AB INPUT
VCC
INPUT
1 kΩ
9V
VCC
INPUT
100 kΩ
1 kΩ
9V
100 kΩ
Figure 28. Equivalent Input and Output Schematic Diagrams
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10 Detailed Description
10.1 Overview
This family of CAN transceivers is compatible with the ISO11898-2 High-Speed CAN (controller area network)
physical layer standard. They are designed to interface between the differential bus lines in CAN and the CAN
protocol controller at data rates up to 1 Mpbs.
10.2 Functional Block Diagrams
RS
CANH
D
CANL
LBK
R
LBK
Figure 29. SN65HVD33 Functional Block Diagram
RS
CANH
D
CANL
EN
R
Figure 30. SN65HVD34 Functional Block Diagram
RS
CANH
D
CANL
AB
R
Figure 31. SN65HVD35 Functional Block Diagram
10.3 Feature Description
10.3.1 Diagnostic Loopback (SN65HVD233)
The diagnostic loopback or internal loopback function of the SN65HVD233 is enabled with a high-level input on
pin 5, LBK. This mode disables the driver output while keeping the bus pins biased to the recessive state. This
mode also redirects the D data input (transmit data) through logic to the received data output pin), thus creating
an internal loopback of the transmit to receive data path. This mimics the loopback that occurs normally with a
CAN transceiver because the receiver loops back the driven output to the R (receive data) pin. This mode allows
the host protocol controller to input and read back a bit sequence or CAN messages to perform diagnostic
routines without disturbing the CAN bus. A typical CAN bus application is displayed in Figure 36.
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Feature Description (continued)
If the LBK pin is not used it may be tied to ground (GND). However, it is pulled low internally (defaults to a lowlevel input) and may be left open if not in use.
10.3.2 Autobaud Loopback (SN65HVD235)
The autobaud loopback mode of the SN65HVD235 is enabled by placing a high level input on pin 5, AB. In
autobaud mode, the driver output is disabled, thus blocking the D pin to bus path and the bus transmit function of
the transceiver. The bus pins remain biased to recessive. The receiver to R pin path or the bus receive function
of the device remains operational, allowing bus activity to be monitored. In addition, the autobaud mode adds an
internal logic loopback path from the D pin to R pin so the local node may transmit to itself in sync with bus traffic
while not disturbing messages on the bus. Thus if the local node’s CAN controller generates an error frame, it is
not transmitted to the bus, but is detected only by the local CAN controller. This is especially helpful to determine
if the local node is set to the same baud rate as the network, and if not adjust it to the network baud rate
(autobaud detection).
Autobaud detection is best suited to applications that have a known selection of baud rates. For example, a
popular industrial application has optional settings of 125 kbps, 250 kbps, or 500 kbps. Once the SN65HVD235
is placed into autobaud loopback mode the application software could assume the first baud rate of 125 kbps. It
then waits for a message to be transmitted by another node on the bus. If the wrong baud rate has been
selected, an error message is generated by the local CAN controller because the sample times will not be at the
correct time. However, because the bus-transmit function of the device has been disabled, no other nodes
receive the error frame generated by this node's local CAN controller.
The application would then make use of the status register indications of the local CAN controller for message
received and error warning status to determine if the set baud rate is correct or not. The warning status indicates
that the CAN controller error counters have been incremented. A message received status indicates that a good
message has been received. If an error is generated, the application would then set the CAN controller with the
next possibly valid baud rate, and wait to receive another message. This pattern is repeated until an error free
message has been received, thus the correct baud rate has been selected. At this point the application would
place the SN65HVD235 in a normal transmitting mode by setting pin 5 to a low-level, thus enabling bus-transmit
and bus-receive functions to normal operating states for the transceiver.
If the AB pin is not used it may be tied to ground (GND). However, it is pulled low internally (defaults to a lowlevel input) and may be left open if not in use.
10.3.3 Slope Control
The rise and fall slope of the SN65HVD233, SN65HVD234, and SN65HVD235 driver output can be adjusted by
connecting a resistor from the Rs (pin 8) to ground (GND), or to a low-level input voltage as shown in Figure 32.
The slope of the driver output signal is proportional to the pin's output current. This slope control is implemented
with an external resistor value of 10 kΩ to achieve a ~15 V/μs slew rate, and up to 100 kΩ to achieve a ~2.0 V/μs
slew rate . A typical slew rate verses pulldown resistance graph is shown in Figure 33. Typical driver output
waveforms with slope control are displayed in Figure 39.
10 kΩ
to
100 kΩ
D
GND
Vcc
R
1
2
3
4
8
Rs
7
6
5
CANH
CANL
LBK
IOPF6
TMS320LF2407
Figure 32. Slope Control/Standby Connection to a DSP
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Feature Description (continued)
25
Slope (V/us)
20
15
10
5
0
0
4.7 6.8
10
15
22
33
47
68
100
Slope Control Resistance - kΩ
Figure 33. HVD233 Driver Output Signal Slope vs Slope Control Resistance Value
10.3.4 Standby
If a high-level input (> 0.75 VCC) is applied to RS (pin 8), the circuit enters a low-current, listen only standby mode
during which the driver is switched off and the receiver remains active. If using this mode to save system power
while waiting for bus traffic, the local controller can monitor the R output pin for a falling edge which indicates that
a dominant signal was driven onto the CAN bus. The local controller can then drive the RS pin low to return to
slope control mode or high-speed mode.
10.3.5 Thermal Shutdown
If the junction temperature of the device exceeds the thermal shut down threshold the device turns off the CAN
driver circuits thus blocking the D pin to bus transmission path. The shutdown condition is cleared when the
junction temperature drops below the thermal shutdown temperature of the device. The CAN bus pins are high
impedance biased to recessive level during a thermal shutdown, and the receiver to R pin path remains
operational.
10.4 Device Functional Modes
10.4.1 Driver and Receiver
Table 2. Driver (SN65HVD233 or SN65HVD235)
INPUTS
D
OUTPUTS
LBK/AB
Rs
X
X
> 0.75 VCC
L
L or open
H or open
X
X
H
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≤ 0.33 VCC
≤ 0.33 VCC
CANH
CANL
BUS STATE
Recessive
Z
Z
H
L
Dominant
Z
Z
Recessive
Z
Z
Recessive
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Table 3. Receiver (SN65HVD233)
INPUTS
BUS STATE
OUTPUT
VID = V(CANH)–V(CANL)
LBK
D
R
Dominant
VID ≥ 0.9 V
L or open
X
L
Recessive
VID ≤ 0.5 V or open
L or open
H or open
H
L or open
H or open
?
L
L
H
H
?
0.5 V < VID
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