SN65HVD3082E, SN75HVD3082E, SN65HVD3085E, SN65HVD3088E
SLLS562M – AUGUST 2009 – REVISED FEBRUARY 2022
SNx5HVD308xE Low-Power RS-485 Transceivers
1 Features
•
•
•
•
•
•
•
Meets or exceeds the requirements of the TIA/
EIA-485A standard
Low quiescent power
– 0.3-mA Active mode
– 1-nA Shutdown mode
1/8 Unit load up to 256 nodes on a bus
Bus-pin ESD protection up to 15 kV
Industry-standard SN75176 footprint
Fail-safe receiver (bus open, bus shorted,
bus idle)
Glitch-free power-up and power-down bus inputs
and outputs
2 Applications
•
•
•
•
•
•
•
Energy meter networks
Motor control
Power inverters
Industrial automation
Building automation networks
Battery-powered applications
Telecommunications equipment
These devices are designed to operate with very
low supply current, typically 0.3 mA, exclusive of the
load. When in the inactive-shutdown mode, the supply
current drops to a few nanoamps, which makes these
devices ideal for power-sensitive applications.
The wide common-mode range and high ESD
protection levels of these devices, make them suitable
for demanding applications such as energy meter
networks, electrical inverters, status and command
signals across telecom racks, as well as cabled
chassis interconnects, and industrial automation
networks where noise tolerance is essential. These
devices match the industry-standard footprint of the
SN75176 device. The power-on-reset circuits keep
the outputs in a high-impedance state until the
supply voltage has stabilized. A thermal-shutdown
function protects the device from damage, due to
system fault conditions. The SN75HVD3082E is
characterized for operation from 0°C to 70°C and
SN65HVD308xE is characterized for operation from –
40°C to 85°C air temperature. The D package version
of the SN65HVD3082E has been characterized for
operation from –40°C to 105°C.
3 Description
Device Information
The SNx5HVD308xE are half-duplex transceivers
designed for RS-485 data bus networks. Powered
by a 5-V supply, they are fully compliant with TIA/
EIA-485A standard. With controlled transition times,
these devices are suitable for transmitting data over
long twisted-pair cables. The SN65HVD3082E and
SN75HVD3082E are optimized for signaling rates
up to 200 kbps. The SN65HVD3085E is suitable
for data transmission up to 1 Mbps, whereas the
SN65HVD3088E is suitable for applications that
require signaling rates up to
20 Mbps.
R
SN65HVD3082E
SN65HVD3088E
SN75HVD3082E
SN65HVD3085E
(1)
4.90 mm × 3.91 mm
VSSOP (DGK) (8)
3.00 mm × 3.00 mm
PDIP (P) (8)
9.81 mm × 6.35 mm
SOIC (D) (8)
4.90 mm × 3.91 mm
VSSOP (DGK) (8)
3.00 mm × 3.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
space
R
A
B
DE
BODY SIZE (NOM)
SOIC (D) (8)
R
RE
D
PACKAGE(1)
PART NUMBER
R
A
RT
RT
D
A
R
B
A
D
R RE DE D
R
RE
B
DE
D
B
D
D
R RE DE D
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN65HVD3082E, SN75HVD3082E, SN65HVD3085E, SN65HVD3088E
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SLLS562M – AUGUST 2009 – REVISED FEBRUARY 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information, SN65HVD308xE....................... 5
6.5 Thermal Information, SNx5HVD3082E....................... 5
6.6 Electrical Characteristics: Driver................................. 6
6.7 Electrical Characteristics: Receiver............................ 6
6.8 Electrical Characteristics.............................................7
6.9 Switching Characteristics: Driver................................ 7
6.10 Switching Characteristics..........................................8
6.11 Typical Characteristics.............................................. 9
7 Parameter Measurement Information.......................... 11
8 Detailed Description......................................................15
8.1 Overview................................................................... 15
8.2 Functional Block Diagram......................................... 15
8.3 Feature Description...................................................15
8.4 Device Functional Modes..........................................15
9 Application and Implementation.................................. 17
9.1 Application Information............................................. 17
9.2 Typical Application.................................................... 17
10 Power Supply Recommendations..............................21
11 Layout........................................................................... 21
11.1 Layout Guidelines................................................... 21
11.2 Layout Example...................................................... 21
11.3 Thermal Considerations for IC Packages............... 22
12 Device and Documentation Support..........................23
12.1 Device Support....................................................... 23
12.2 Related Links.......................................................... 23
12.3 Receiving Notification of Documentation Updates..23
12.4 Support Resources................................................. 23
12.5 Trademarks............................................................. 23
12.6 Electrostatic Discharge Caution..............................23
12.7 Glossary..................................................................23
13 Mechanical, Packaging, and Orderable
Information.................................................................... 24
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision L (November 2021) to Revision M (February 2022)
Page
• Added storage temperature Tstg to Absolute Maximum Ratings table................................................................4
• Changed the Thermal Information, SN65HVD308xE table................................................................................ 5
Changes from Revision K (July 2021) to Revision L (November 2021)
Page
• Deleted Feature: Available in a small MSOP-8 package ...................................................................................1
• Deleted Available in a Small MSOP-8 Package from the title.............................................................................1
• Changed the ψJT D package value from 78.8 to 8.8 in the Thermal Information, SNx5HVD3082E ..................5
Changes from Revision J (October 2017) to Revision K (July 2021)
Page
• Changed the Thermal Information tables........................................................................................................... 5
Changes from Revision I (September 2016) to Revision J (October 2017)
Page
• Changed 3.3 V to 5 V on the VCC pin in Figure 9-4 ......................................................................................... 19
Changes from Revision H (August 2015) to Revision I (September 2016)
Page
• Added text to the Description, "The D package version of the SN65HVD3082E has been characterized for
operation from -40°C to 105°C."......................................................................................................................... 1
• Changed the Operating free-air temperature for SN65HVD3082E (D package) From: MAX = 85°C To: 105°C
in Section 6.3 ..................................................................................................................................................... 5
2
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SLLS562M – AUGUST 2009 – REVISED FEBRUARY 2022
Changes from Revision G (May 2009) to Revision H (August 2015)
Page
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ............................................................................................................................................................... 1
• Deleted Dissipation Ratings table ......................................................................................................................1
• Deleted Package Thermal Information table ..................................................................................................... 6
Changes from Revision F (March 2009) to Revision G (May 2009)
Page
• Added Graph - Driver Rise and Fall Time vs Temperature ................................................................................9
• Added IDLE Bus to the Function Table.............................................................................................................15
• Added Receiver Fail-safe section..................................................................................................................... 19
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SLLS562M – AUGUST 2009 – REVISED FEBRUARY 2022
5 Pin Configuration and Functions
R
1
8
VCC
RE
DE
D
2
7
B
3
4
6
A
5
GND
Figure 5-1. D (SOIC), P (PDIP), and DGK (VSSOP) Packages, 8-Pin, Top View
Table 5-1. Pin Functions
PIN
NAME
TYPE
NO.
DESCRIPTION
A
6
Bus input/output
Driver output or receiver input (complementary to B)
B
7
Bus input/output
Driver output or receiver input (complementary to A)
D
4
Digital input
Driver data input
DE
3
Digital input
Driver enable, active high
GND
5
Reference potential
Local device ground
R
1
Digital output
Receive data output
RE
2
Digital input
VCC
8
Supply
Receiver enable, active low
4.5-V to 5.5-V supply
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range unless otherwise noted(1) (2)
Supply voltage, VCC
Voltage at A or B
MIN
MAX
UNIT
–0.5
7
V
–9
14
V
Voltage at any logic pin
–0.3
VCC + 0.3
V
Receiver output current
–24
24
mA
Voltage input, transient pulse, A and B, through 100 Ω (see Figure 7-13)
–50
50
V
170
°C
150
°C
Junction Temperature, TJ
Storage temperature, Tstg
(1)
(2)
-65
Operation outside the Absolute Maximum Ratingss may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
6.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
V(ESD)
Electrostatic discharge
Charged-device model (CDM), per JEDEC specification
Bus pins and GND
±15000
All pins
±4000
JESD22-C101(2)
Electrical Fast Transient/Burst, A, B, and GND(3)
(1)
(2)
(3)
4
±1000
UNIT
V
±4000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Tested in accordance with IEC 61000-4-4.
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SLLS562M – AUGUST 2009 – REVISED FEBRUARY 2022
6.3 Recommended Operating Conditions
over operating free-air temperature range unless otherwise noted(1)
MIN
NOM
MAX
UNIT
Supply voltage, VCC
4.5
5.5
Voltage at any bus terminal (separately or common mode) , VI
–7
12
High-level input voltage (D, DE, or RE inputs), VIH
2
VCC
V
Low-level input voltage (D, DE, or RE inputs), VIL
0
0.8
V
–12
12
V
–60
60
–8
8
Differential input voltage, VID
Driver
Output current, IO
Receiver
Differential load resistance, RL
54
60
Operating free-air temperature, TA
0.2
SN65HVD3085E
1
SN65HVD3088E
20
SN65HVD3082E (D package)
–40
105
SN65HVD3082E (DGK and P packages),
SN65HVD3085E, SN65HVD3088E
–40
85
0
70
–40
130
SN75HVD3082E
Junction temperature, TJ
(1)
mA
Ω
SN65HVD3082E, SN75HVD3082E
Signaling rate, 1/tUI
V
Mbps
°C
°C
The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
6.4 Thermal Information, SN65HVD308xE
SN65HVD3085E, SN65HVD3088E
THERMAL
METRIC(1)
SN65HVD3088E
D (SOIC)
DGK (VSSOP)
P (PDIP)
8 PINS
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
116.7
137.8
84.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
56.3
31.2
65.4
°C/W
RθJB
Junction-to-board thermal resistance
63.4
71.7
62.1
°C/W
ψJT
Junction-to-top characterization parameter
8.8
0.6
31.3
°C/W
ψJB
Junction-to-board characterization parameter
62.6
70.5
60.4
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Thermal Information, SNx5HVD3082E
SN65HVD3082E, SN75HVD3082E
THERMAL METRIC(1)
SN65HVD3082E
D (SOIC)
DGK (VSSOP)
P (PDIP)
UNIT
8 PINS
8 PINS
8 PINS
RθJA
Junction-to-ambient thermal resistance
114.4
142.2
88.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
55.1
35.8
65.9
°C/W
RθJB
Junction-to-board thermal resistance
61.6
75.6
69.0
°C/W
ψJT
Junction-to-top characterization parameter
8.8
0.8
35.2
°C/W
ψJB
Junction-to-board characterization parameter
60.8
74.8
64.3
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.6 Electrical Characteristics: Driver
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IO = 0, No Load
RL = 54 Ω (see Figure 7-1)
|VOD|
Differential output voltage
RL = 100 Ω
VTEST = –7 V to 12 V (see Figure
7-2)
Δ|VOD|
Change in magnitude of differential
output voltage
VOC(SS)
Steady-state common-mode output
voltage
See Figure 7-1 and Figure 7-2
MIN
TYP(1)
3
4.3
1.5
2.3
MAX
UNIT
V
2
1.5
–0.2
0
0.2
1
2.6
3
–0.1
0
0.1
See Figure 7-3
V
V
ΔVOC(SS)
Change in steady-state commonmode output voltage
VOC(PP)
Peak-to-peak common-mode output
voltage
See Figure 7-3
IOZ
High-impedance output current
See receiver input currents in
Electrical Characteristics: Receiver
II
Input current
D, DE
–100
100
µA
IOS
Short-circuit output current
−7 V ≤ VO ≤ 12 V (see Figure 7-7 )
–250
250
mA
TYP(1)
MAX
UNIT
–85
–10
mV
(1)
500
mV
All typical values are at 25°C and with a 5-V supply.
6.7 Electrical Characteristics: Receiver
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT+
Positive-going differential input
threshold voltage
IO = –8 mA
VIT–
Negative-going differential input
threshold voltage
IO = 8 mA
Vhys
Hysteresis voltage (VIT+ – VIT–)
VOH
High-level output voltage
VID = 200 mV, IOH = –8 mA (see
Figure 7-8)
VOL
Low-level output voltage
VID = –200 mV, IO = 8 mA (see
Figure 7-8)
IOZ
High-impedance-state output current VO = 0 or VCC, RE = VCC
MIN
–200
4
IIH
High-level input current, ( RE)
VIH = 2 V
IIL
Low-level input current, ( RE)
VIL = 0.8 V
Differential input capacitance
VI = 0.4 sin (4E6πt) + 0.5 V, DE at 0
V
Cdiff
(1)
6
VIH = 12 V, VCC = 0 V
Bus input current
mV
30
mV
4.6
V
0.15
0.4
V
1
μA
0.04
0.1
0.06
0.125
–1
VIH = 12 V, VCC = 5 V
II
–115
mA
VIH = –7 V, VCC = 5 V
–0.1
–0.04
VIH = –7 V, VCC = 0 V
–0.05
–0.03
–60
–30
μA
–60
–30
μA
7
pF
All typical values are at 25°C and with a 5-V supply.
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6.8 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
ICC
P(AVG)
(1)
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
Driver and receiver enabled
D at VCC or open, DE at VCC,
RE at 0 V, No load
425
900
µA
Driver enabled, receiver
disabled
D at VCC or open, DE at VCC,
RE at VCC, No load
330
600
µA
Receiver enabled, driver
disabled
D at VCC or open, DE at 0 V,
RE at 0 V, No load
300
600
µA
Driver and receiver disabled
D at VCC or open, DE at 0 V,
RE at VCC
0.001
2
µA
Average power dissipation
Input to D is a 50% duty cycle ALL HVD3082E
square wave at max specified
ALL HVD3085E
signal rate
ALL HVD3088E
RL = 54 Ω VCC = 5.5 V, TJ =
130°C
203
205
mW
276
All typical values are at 25°C and with a 5-V supply.
6.9 Switching Characteristics: Driver
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TYP
MAX
HVD3082E
MIN
700
1300
HVD3085E
150
500
tPLH
tPHL
Propagation delay time, lowto-high-level output
Propagation delay time, highto-low-level output
tr
tf
Differential output signal rise
time
Differential output signal fall
time
RL = 54 Ω, CL = 50 pF
(see Figure 7-4)
tsk(p)
Pulse skew (|tPHL – tPLH|)
RL = 54 Ω, CL = 50 pF
(see Figure 7-4)
HVD3088E
1.4
2
HVD3082E
2500
7000
tPZH
tPZL
Propagation delay time,
high-impedance-to-high-level RL = 110 Ω, RE at 0 V
output
(see Figure 7-5 and Figure
Propagation delay time, high- 7-6)
impedance-to-low-level output
HVD3085E
1000
2500
HVD3088E
13
30
HVD3082E
80
200
tPHZ
tPLZ
Propagation delay time,
high-level-to-high-impedance
output
Propagation delay time,
low-level-to-high-impedance
output
HVD3085E
60
100
tPZH(SHDN)
tPZL(SHDN)
Propagation delay time,
shutdown-to-high-level output RL = 110 Ω, RE at VCC
Propagation delay time,
(see Figure 7-5)
shutdown-to-low-level output
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RL = 54 Ω, CL = 50 pF
(see Figure 7-4)
HVD3088E
12
20
900
1500
HVD3085E
200
300
HVD3088E
7
15
HVD3082E
20
200
HVD3085E
5
50
HVD3082E
RL = 110 Ω, RE at 0 V
(see Figure 7-5 and Figure
7-6)
500
UNIT
ns
ns
ns
ns
ns
HVD3088E
12
30
HVD3082E
3500
7000
HVD3085E
2500
4500
HVD3088E
1600
2600
ns
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6.10 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Propagation delay time, highto-low-level output
tPHL
tsk(p)
TYP
MAX
75
200
HVD3082E
HVD3085E
Propagation delay time, lowto-high-level output
tPLH
MIN
HVD3086E
CL = 15 pF (see Figure 7-9)
HVD3082E
HVD3085E
79
Output signal rise time
tf
Output signal fall time
HVD3082E
HVD3085E
tPZH
Output enable time to high
level
Output enable time to low
level
tPZL
Output enable time from high
level
tPHZ
4
tPZH(SHDN)
tPZL(SHDN)
Propagation delay time,
shutdown-to-high-level output CL = 15 pF, DE at 0 V,
(see Figure 7-12)
Propagation delay time,
shutdown-to-low-level output
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30
1.5
3
1.8
3
5
50
HVD3088E
CL = 15 pF,
DE at 3 V
(see Figure 7-10 and Figure
7-11)
ns
ns
10
HVD3082E
HVD3085E
Output disable time from low
level
tPLZ
8
VID = –1.5 V to 1.5 V,
CL = 15 pF (see Figure 7-9)
200
100
HVD3088E
tr
ns
100
HVD3088E
Pulse skew (|tPHL – tPLH|)
UNIT
ns
ns
30
HVD3082E
HVD3085E
10
HVD3088E
50
ns
30
HVD3082E
HVD3085E
5
HVD3088E
50
ns
30
HVD3082E
HVD3085E
8
HVD3088E
50
ns
30
1600
3500
1700
3500
ns
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6.11 Typical Characteristics
80
10
No Load,
VCC = 5 V,
o
TA = 25 C
50% Square Wave Input
ICC - Supply Current - mA
II - Input Bias Current - mA
60
40
VCC = 0 V
20
VCC = 5 V
0
-20
Driver and Receiver
1
Receiver Only
-40
-60
0.1
-8
-6
-4
-2
0
2
4
6
8
10
12
1
10
Figure 6-1. Bus Input Current versus Bus Input Voltage
Figure 6-2. SN65HVD3082E RMS Supply Current versus
Signaling Rate
100
No Load,
VCC = 5 V,
o
TA = 25 C
50% Square Wave Input
ICC - Supply Current - mA
ICC - Supply Current - mA
100
10
Driver and Receiver
1
Receiver Only
No Load,
VCC = 5 V,
o
TA = 25 C
50% Square Wave Input
10
Driver and Receiver
1
Receiver Only
0.1
1
10
1000
100
0.1
Signal Rate - kbps
Figure 6-3. SN65HVD3085E RMS Supply Current versus
Signaling Rate
Figure 6-4. SN65HVD3088E RMS Supply Current versus Signal
Rate
5
5
o
4
4.5
RL = 120W
VO - Receiver Output Voltage - V
TA = 25 C
VCC = 5 V
4.5
VOD - Differential Output Voltage - V
100
Signal Rate - kbps
VI - Bus Input Voltage - V
3.5
3
RL = 60W
2.5
2
1.5
1
0.5
4
TA = 25oC
VCC = 5 V
VIC = 0.75 V
3.5
3
2.5
2
1.5
1
0.5
0
0
10
20
30
40
50
IO - Differential Output Current - mA
Figure 6-5. Driver Differential Output Voltage versus Driver
Output Current
Copyright © 2022 Texas Instruments Incorporated
0
-200 -180 -160 -140 -120 -100 -80 -60 -40 -20
0
VID - Differential Input Voltage - V
Figure 6-6. Receiver Output Voltage versus Differential Input
Voltage
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6.11 Typical Characteristics (continued)
10
Rise/Fall Time - ns
9
8
VCC = 4.5 V
7
VCC = 5 V
VCC = 5.5 V
6
5
-40
-20
0
20
40
60
80
o
TA - Temperature - C
Figure 6-7. SN65HVD3088E Driver Rise and Fall Time versus Temperature
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7 Parameter Measurement Information
Test load capacitance includes probe and jig capacitance (unless otherwise specified). Signal generator
characteristics: rise and fall time < 6 ns, pulse rate 100 kHz, 50% duty cycle. ZO = 50 Ω (unless otherwise
specified).
II
A
IOA
27 W
VOD
0 V or 3 V
B
50 pF
27 W
IOB
VOC
Figure 7-1. Driver Test Circuit, VOD and VOC Without Common-Mode Loading
375 W
IOA
VOD
0 V or 3 V
60 W
375 W
IOB
VTEST = -7 V to 12 V
VTEST
Figure 7-2. Driver Test Circuit, VOD With Common-Mode Loading
27 W
A
Signal
Generator
50 W
-3.25 V
VA
-1.75 V
VB
27 W
B
50 pF
VOC
VOC(PP)
DVOC(SS)
VOC
Figure 7-3. Driver VOC Test Circuit and Waveforms
3V
1.5 V
Input
1.5 V
0V
RL = 50 W
Signal
Generator
VOD
tPHL
tPLH
CL = 50 pF
50 W
90%
0V
Output
10%
tf
tr
VOD(H)
VOD(L)
Figure 7-4. Driver Switching Test Circuit and Waveforms
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A
D
0 V or 3 V
3 V if Testing A Output
0 V if Testing B Output
Output
3V
B
1.5 V
DE
1.5 V
0V
0.5 V
tPZH
RL = 110 W
CL = 50 pF
DE
Signal
Generator
S1
VOH
2.5 V
Output
50 W
VOff0
tPHZ
Figure 7-5. Driver Enable and Disable Test Circuit and Waveforms, High Output
5V
A
D
0 V or 3 V
0 V if Testing A Output
3 V if Testing B Output
RL = 110 W
S1
3V
Output
B
DE
0V
tPZL
CL = 50 pF
DE
1.5 V
1.5 V
tPLZ
5V
Output
Signal
Generator
2.5 V
VOL
50 W
0.5 V
Figure 7-6. Driver Enable and Disable Test Circuit and Waveforms, Low Output
IOS
IO
VID
VO
VO
Voltage
Source
Figure 7-8. Receiver Switching Test Circuit and
Waveforms
Figure 7-7. Driver Short-Circuit
Signal
Generator
50 W
Input B
VID
1.5 V
A
B
Signal
Generator
50 W
R
CL = 15 pF
IO
VO
50%
Input A
0V
tPHL
tPLH
VOH
90%
Output
10%
tr
tf
VOL
Figure 7-9. Receiver Switching Test Circuit and Waveforms
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VCC D
DE
V
CC
A
54 W
B
1 kW
R
3V
RE
1.5 V
0V
0V
RE
Signal
Generator
CL = 15 pF
tPZH
tPHZ
VOH
VOH -0.5 V
50 W
1.5 V
R
GND
Figure 7-10. Receiver Enable and Disable Test Circuit and Waveforms, Data Output High
0V D
DE
V
CC
A
54 W
B
R
RE
5V
1.5 V
0V
CL = 15 pF
RE
Signal
Generator
3V
1 kW
tPLZ
tPZL
50 W
VCC
R
1.5 V
VOH +0.5 V
VOL
Figure 7-11. Receiver Enable and Disable Test Circuit and Waveforms, Data Output Low
VCC
Switch Down for V(A) = 1.5 V
Switch Up for V(A) = -1.5 V
A
1.5 V or
-1.5 V
R
B
RE
Signal
Generator
50 W
3V
1 kW
RE
1.5 V
CL = 15 pF
0V
tPZH(SHDN)
tPZL(SHDN)
5V
VOH
R
1.5 V
VOL
0V
Figure 7-12. Receiver Enable From Shutdown Test Circuit and Waveforms
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VTEST
100 W
0V
Pulse Generator,
15 ms Duration,
1% Duty Cycle
15 ms
-VTEST
15 ms
Figure 7-13. Test Circuit and Waveforms, Transient Overvoltage Test
DE Input
D and RE Input
VCC
50 kW
500 W
Input
VCC
Input
9V
500 W
50 kW
9V
A Input
B Input
VCC
VCC
36 kW
16 V
36 kW
16 V
180 kW
180 kW
Input
Input
16 V
36 kW
16 V
36 kW
A and B Output
R Output
VCC
VCC
16 V
5W
Output
16 V
Output
9V
Figure 7-14. Equivalent Input and Output Schematic Diagrams
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8 Detailed Description
8.1 Overview
The SNx5HVD308xE family of half-duplex RS-485 transceivers is suitable for data transmission at rates up
to 200 kbps (for SN65HVD3082E and SN75HVD3082E), 1 Mbps (for SN65HVD3085E), or 20 Mbps (for
SN65HVD3088E) over controlled-impedance transmission media (such as twisted-pair cabling). Up to 256 units
of SNx5HVD308xE may share a common RS-485 bus due to the family’s low bus input currents. The devices
also feature a high degree of ESD protection and typical standby current consumption of 1 nA.
8.2 Functional Block Diagram
VCC
R
RE
A
DE
B
D
GND
8.3 Feature Description
The SNx5HVD308xE provides internal biasing of the receiver input thresholds for open-circuit, bus-idle, or
short-circuit fail-safe conditions. It features a typical hysteresis of 30 mV in order to improve noise immunity.
Internal ESD protection circuits protect the transceiver bus terminals against ±15-kV Human Body Model (HBM)
electrostatic discharges.
The devices protect themselves against damage due to overtemperature conditions, through the use of a
thermal shutdown feature. Thermal shutdown is entered at 165°C (nominal) and causes the device to enter a
low-power state with high-impedance outputs.
8.4 Device Functional Modes
When the driver enable pin, DE, is logic high, the differential outputs A and B follow the logic states at data input
D. A logic high at D causes A to turn high and B to turn low. In this case the differential output voltage defined
as VOD = VA – VB is positive. When D is low, the output states reverse, B turns high, A becomes low, and VOD is
negative.
When DE is low, both outputs turn high-impedance. In this condition the logic state at D is irrelevant. The DE
pin has an internal pull-down resistor to ground, thus when left open the driver is disabled (high-impedance) by
default. The D pin has an internal pull-up resistor to VCC, thus, when left open while the driver is enabled, output
A turns high and B turns low.
Table 8-1. Driver Function Table
(1)
INPUT
ENABLE(1)
OUTPUTS(1)
D
DE
A
H
H
H
L
Actively drive bus High
L
H
L
H
Actively drive bus Low
X
L
Z
Z
Driver disabled
X
OPEN
Z
Z
Driver disabled by default
OPEN
H
H
L
Actively drive bus High by default
FUNCTION
B
H = high level, L = low level, Z = high impedance, X = irrelevant
When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage
defined as VID = VA – VB is positive and higher than the positive input threshold, VIT+, the receiver output, R,
turns high. When VID is negative and lower than the negative input threshold, VIT–, the receiver output, R, turns
low. If VID is between VIT+ and VIT– the output is indeterminate.
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When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of VID
are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is
disconnected from the bus (open-circuit), the bus lines are shorted (short-circuit), or the bus is not actively driven
(idle bus).
Table 8-2. Receiver Function Table
DIFFERENTIAL INPUT
ENABLE (1)
OUTPUT(1)
VID = VA – VB
RE
R
VIT+ < VID
L
H
Receive valid bus High
VIT– < VID < VIT+
L
?
Indeterminate bus state
VID < VIT–
L
L
Receive valid bus Low
X
H
Z
Receiver disabled
X
OPEN
Z
Receiver disabled by default
Open-circuit bus
L
H
Fail-safe high output
Short-circuit bus
L
H
Fail-safe high output
Idle (terminated) bus
L
H
Fail-safe high output
(1)
16
FUNCTION
H = high level, L = low level, Z = high impedance, X = irrelevant, ? = indeterminate
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The SNx5HVD308xE devices are half-duplex RS-485 transceivers commonly used for asynchronous data
transmissions. The driver and receiver enable pins allow the configuration of different operating modes.
R
R
R
R
R
R
RE
A
RE
A
RE
A
DE
B
DE
B
DE
B
D
D
D
D
D
D
Figure 9-1. Half-Duplex Transceiver Configurations
Using independent enable lines provides the most flexible control, as it allows the driver and the receiver to be
turned on and off individually. While this configuration requires two control lines, it allows selective listening into
the bus traffic whether the driver is transmitting data or not.
Combining the enable signals simplify the interface to the controller, by forming a single direction-control signal.
In this configuration, the transceiver operates as a driver when the direction-control line is high and as a receiver
when the direction-control line is low.
Additionally, only one line is required when connecting the receiver-enable input to ground and controlling only
the driver-enable input. In this configuration, a node not only receives the data from the bus, but also the data it
sends and can verify that the correct data has been transmitted.
9.2 Typical Application
An RS-485 bus consists of multiple transceivers connecting in parallel to a bus cable. To eliminate line
reflections, each cable end is terminated with a termination resistor, RT, whose value matches the characteristic
impedance, Z0, of the cable. This method, known as parallel termination, allows higher data rates over longer
cable length.
R
R
RE
B
DE
D
R
A
R
A
RT
RT
D
A
R
B
A
D
R RE DE D
R
RE
B
DE
D
B
D
D
R RE DE D
Figure 9-2. Typical Application Circuit
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9.2.1 Design Requirements
RS-485 is a robust electrical standard suitable for long-distance networking that may be used in a wide range of
applications with varying requirements, such as distance, data rate, and number of nodes.
9.2.1.1 Data Rate and Bus Length
The inverse relationship between the data rate and bus length, means the higher the data rate, the shorter the
cable length; and conversely, the lower the data rate, the longer the cable can be without introducing data errors.
While most RS-485 systems use data rates between 10 kbps and 100 kbps, some applications require data
rates up to 250 kbps at distances of 4,000 feet and longer. The longer distances can be achieved by allowing
small signal jitter of up to 5 or 10%.
10000
Cable Length (ft)
5%, 10%, and 20% Jitter
1000
Conservative
Characteristics
100
10
100
1k
10 k
100 k
1M
10 M
100 M
Data Rate (bps)
Figure 9-3. Cable Length vs Data Rate Characteristic
9.2.1.2 Stub Length
The distance between the transceiver inputs and the cable trunk, which is known as the stub, must be short
as possible when connecting a node to the bus. Stubs present a non-terminated piece of bus line which
can introduce reflections as the length of the stub increases. As a general guideline, the electrical length, or
round-trip delay of a stub, must be less than one-tenth of the rise time of the driver, thus giving a maximum
physical stub length as shown in Equation 1.
Lstub ≤ 0.1 × tr × v × c
(1)
where:
•
•
•
tr is the 10/90 rise time of the driver
c is the speed of light (3 × 108 m/s)
v is the signal velocity of the cable or trace as a factor of c
9.2.1.3 Bus Loading
The RS-485 standard specifies that a compliant driver must be able to driver 32 unit loads (UL), where 1 unit
load represents a load impedance of approximately 12 kΩ. The SNx5HVD308xE is a 1/8 UL transceiver, which
means it can connect up to 256 receivers to the bus.
18
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9.2.1.4 Receiver Fail-safe
The differential receiver is fail-safe to invalid bus states caused by:
• Open bus conditions, such as a disconnected connector
• Shorted bus conditions, such as cable damage shorting the twisted-pair together
• Idle bus conditions that occur when no driver on the bus is actively driving
In any of these cases, the differential receiver outputs a fail-safe logic High state, so that the output of the
receiver is not indeterminate.
Receiver fail-safe is accomplished by offsetting the receiver thresholds, so that the input indeterminate range
does not include zero volts differential. To comply with the RS-422 and RS-485 standards, the receiver output
must output a High when the differential input VID is more positive than +200 mV, and must output a Low when
the VID is more negative than –200 mV. The receiver parameters which determine the fail-safe performance are
VIT+ and VIT– and VHYS. As seen in the Electrical Characteristics table, differential signals more negative than
–200 mV will always cause a Low receiver output and differential signals more positive than +200 mV will always
cause a High receiver output.
When the differential input signal is close to zero, it is still above the maximum VIT+ threshold, and the receiver
output is High. Only when the differential input is more negative than VIT– will the receiver output transition to a
Low state. The noise immunity of the receiver inputs during a bus fault condition, includes the receiver hysteresis
value VHYS (the separation between VIT+ and VIT– ) as well as the value of VIT+.
9.2.2 Detailed Design Procedure
In order to protect bus nodes against high-energy transients, the implementation of external transient protection
devices is necessary.
5V
100 nF
100 nF
10 kΩ
VCC
R1
R
RxD
MCU/
UART
DIR
RE
A
DE
B
TVS
D
TxD
R2
GND
10 kΩ
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Figure 9-4. Transient Protection Against ESD, EFT, and Surge Transients
Figure 9-4 suggests a protection circuit against 10-kV ESD (IEC 61000-4-2), 4-kV EFT (IEC 61000-4-4), and
1-kV surge (IEC 61000-4-5) transients. Table 9-1 shows the associated Bill of Materials.
Table 9-1. Bill of Materials
DEVICE
FUNCTION
ORDER NUMBER
MANUFACTURER
XCVR
RS-485 Transceiver
SNx5HVD308xE
R1, R2
10-Ω, Pulse-Proof Thick-Film Resistor
CRCW060310RJNEAHP
Vishay
TVS
Bidirectional 400-W Transient Suppressor
CDSOT23-SM712
Bourns
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9.2.2.1 Power Usage in an RS-485 Transceiver
With power consumption being a concern in many applications, power supply current is delivered to the bus load
as well as to the transceiver circuitry. For a typical RS-485 bus configuration, the load that an active driver must
drive consists of all of the receiving nodes, plus the termination resistors at each end of the bus.
The load presented by the receiving nodes depends on the input impedance of the receiver. The TIA/EIA-485A
standard defines a unit load as allowing up to 1 mA. With up to 32 unit loads allowed on the bus, the total current
supplied to all receivers can be as high as 32 mA. The HVD308xE is rated as a 1/8 unit load device. As shown in
Figure 6-1, the bus input current is less than 0.125 mA, allowing up to 256 nodes on a single bus.
The current in the termination resistors depends on the differential bus voltage. The standard requires active
drivers to produce at least 1.5 V of differential signal. For a bus terminated with one standard 120-Ω resistor at
each end, this sums to 25 mA differential output current whenever the bus is active. Typically, the HVD308xE
can drive more than 25-mA to a 60-Ω load, resulting in a differential output voltage higher than the minimum
required by the standard (see Figure 6-3).
Overall, the total load current can be 60 mA to a loaded RS-485 bus. This is in addition to the current required by
the transceiver itself; the HVD308xE circuitry requires only about 0.4 mA with both driver and receiver enabled,
and only 0.3 mA with either the driver enabled or with the receiver enabled. In low-power shutdown mode,
neither the driver nor receiver is active, and the supply current is low.
Supply current increases with signaling rate primarily due to the totem pole outputs of the driver (see Figure 6-2).
When these outputs change state, there is a moment when both the high-side and low-side output transistors
are conducting and this creates a short spike in the supply current. As the frequency of state changes increases,
more power is used.
9.2.2.2 Low-Power Shutdown Mode
When both the driver and receiver are disabled (DE low and RE high) the device is in shutdown mode. If the
enable inputs are in this state for less than 60 ns, the device does not enter shutdown mode. This guards against
inadvertently entering shutdown mode during driver or receiver enabling. Only when the enable inputs are held
in this state for 300 ns or more, the device is assured to be in shutdown mode. In this low-power shutdown
mode, most internal circuitry is powered down, and the supply current is typically 1 nA. When either the driver or
the receiver is re-enabled, the internal circuitry becomes active.
If only the driver is re-enabled (DE transitions to high) the driver outputs are driven according to the D input after
the enable times given by tPZH(SHDN) and tPZL(SHDN) in the driver switching characteristics. If the D input is open
when the driver is enabled, the driver outputs defaults to A high and B low, in accordance with the driver fail-safe
feature.
If only the receiver is re-enabled (RE transitions to low) the receiver output is driven according to the state of
the bus inputs (A and B) after the enable times given by tPZH(SHDN) and tPZL(SHDN) in the receiver switching
characteristics. If there is no valid state on the bus the receiver responds as described in the fail-safe operation
section.
If both the receiver and driver are re-enabled simultaneously, the receiver output is driven according to the state
of the bus inputs (A and B) and the driver output is driven according to the D input.
Note
The state of the active driver affects the inputs to the receiver. Therefore, the receiver outputs are
valid as soon as the driver outputs are valid.
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10 Power Supply Recommendations
To ensure reliable operation at all data rates and supply voltages, each supply must be decoupled with a 100-nF
ceramic capacitor located as close to the supply pins as possible. This helps to reduce supply voltage ripple
present on the outputs of switched-mode power supplies and also helps to compensate for the resistance and
inductance of the PCB power planes.
11 Layout
11.1 Layout Guidelines
Robust and reliable bus node design often requires the use of external transient protection devices in order to
protect against EFT and surge transients that may occur in industrial environments. Due to the wide frequency
bandwidth (from approximately 3 MHz to 3 GHz) that the transients have, high-frequency layout techniques must
be applied during PCB design.
• Place the protection circuitry close to the bus connector to prevent noise transients from entering the board.
• Use VCC and ground planes to provide low-inductance.
Note
High-frequency currents follow the path of least inductance and not the path of least impedance.
•
•
•
•
•
•
Design the protection components into the direction of the signal path. Do not force the transients currents to
divert from the signal path to reach the protection device.
Apply 100-nF to 220-nF bypass capacitors as close as possible to the VCC pins of transceiver, UART, and
controller ICs on the board.
Use at least two vias for VCC and ground connections of bypass capacitors and protection devices to
minimize effective via-inductance.
Use 1-kΩ to 10-kΩ pullup or pulldown resistors for enable lines to limit noise currents in these lines during
transient events.
Insert series pulse-proof resistors into the A and B bus lines if the TVS clamping voltage is higher than the
specified maximum voltage of the transceiver bus pins. These resistors limit the residual clamping current
into the transceiver and prevent it from latching up.
While pure TVS protection is sufficient for surge transients up to 1 kV, higher transients require metal-oxide
varistors (MOVs) that reduce the transients to a few hundred volts of clamping voltage, and transient blocking
units (TBUs) that limit transient current to 200 mA.
11.2 Layout Example
5
Via to ground
Via to VCC
4
6 R
1
R
MCU
R
7
5
R
6 R
SN65HVD3082E
JMP
C
R
TVS
5
Figure 11-1. Layout Example
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11.3 Thermal Considerations for IC Packages
θJA (Junction-to-Ambient Thermal Resistance) is defined as the difference in junction temperature to ambient
temperature divided by the operating power.
θJA is not a constant and is a strong function of:
•
•
•
the PCB design (50% variation)
altitude (20% variation)
device power (5% variation)
θJA can be used to compare the thermal performance of packages when the specific test conditions are
defined and used. Standardized testing includes specification of PCB construction, test chamber volume, sensor
locations, and the thermal characteristics of holding fixtures. θJA is often misused when it is used to calculate
junction temperatures for other installations.
TI uses two test PCBs as defined by JEDEC specifications. The low-k board gives average in-use condition
thermal performance and consists of a single trace layer 25-mm long and 2-oz thick copper. The high-k board
gives best case in-use condition and consists of two 1-oz buried power planes with a single trace layer 25-mm
long with 2-oz thick copper. A 4% to 50% difference in θJA can be measured between these two test cards.
θJC (Junction-to-Case Thermal Resistance) is defined as the difference in junction temperature to case divided
by the operating power. It is measured by putting the mounted package up against a copper block cold plate, to
force heat to flow from the die through the mold compound and into the copper block.
θJC is a useful thermal characteristic when a heat sink is applied to package. It is NOT a useful characteristic
to predict junction temperature, as it provides pessimistic numbers if the case temperature is measured in a
non-standard system and junction temperatures are backed out. It can be used with θJB in 1-dimensional thermal
simulation of a package system.
θJB (Junction-to-Board Thermal Resistance) is defined to be the difference in the junction temperature and the
PCB temperature at the center of the package (closest to the die) when the PCB is clamped in a cold-plate
structure. θJB is only defined for the high-k test card.
θJB provides an overall thermal resistance between the die and the PCB. It includes a bit of the PCB thermal
resistance (especially for BGAs with thermal balls) and can be used for simple 1-dimensional network analysis of
package system (see Figure 11-2).
Ambient Node
qCA Calculated
Surface Node
qJC Calculated/Measured
Junction
qJB Calculated/Measured
PC Board
Figure 11-2. Thermal Resistance
22
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Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: SN65HVD3082E SN75HVD3082E SN65HVD3085E SN65HVD3088E
SN65HVD3082E, SN75HVD3082E, SN65HVD3085E, SN65HVD3088E
www.ti.com
SLLS562M – AUGUST 2009 – REVISED FEBRUARY 2022
12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 12-1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN65HVD3082E
Click here
Click here
Click here
Click here
Click here
SN75HVD3082E
Click here
Click here
Click here
Click here
Click here
SN65HVD3085E
Click here
Click here
Click here
Click here
Click here
SN65HVD3088E
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
Copyright © 2022 Texas Instruments Incorporated
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23
SN65HVD3082E, SN75HVD3082E, SN65HVD3085E, SN65HVD3088E
www.ti.com
SLLS562M – AUGUST 2009 – REVISED FEBRUARY 2022
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
24
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Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: SN65HVD3082E SN75HVD3082E SN65HVD3085E SN65HVD3088E
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN65HVD3082EDG4
NRND
SOIC
D
8
75
TBD
Call TI
Call TI
-40 to 85
SN65HVD3082EDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAU | SN
| NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
NWN
Samples
SN65HVD3082EDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
VP3082
Samples
SN65HVD3082EDRG4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
VP3082
Samples
SN65HVD3082EP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
65HVD3082
Samples
SN65HVD3082EPE4
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
65HVD3082
Samples
SN65HVD3085ED
NRND
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
VP3085
NIPDAU
SN65HVD3085EDG4
NRND
SOIC
D
8
75
RoHS & Green
Level-1-260C-UNLIM
-40 to 85
VP3085
SN65HVD3085EDGK
NRND
VSSOP
DGK
8
80
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
NWK
SN65HVD3085EDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAU | SN
| NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
NWK
Samples
SN65HVD3085EDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
VP3085
Samples
SN65HVD3088ED
NRND
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
VP3088
NIPDAU
SN65HVD3088EDG4
NRND
SOIC
D
8
75
RoHS & Green
Level-1-260C-UNLIM
-40 to 85
VP3088
SN65HVD3088EDGK
NRND
VSSOP
DGK
8
80
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
NWH
SN65HVD3088EDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAU | SN
| NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
NWH
Samples
SN65HVD3088EDGKRG4
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
NWH
Samples
SN65HVD3088EDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
VP3088
Samples
SN65HVD3088EDRG4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
VP3088
Samples
SN75HVD3082EDG4
NRND
SOIC
D
8
75
TBD
Call TI
Call TI
0 to 70
SN75HVD3082EDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
Call TI | SN | NIPDAU
Level-1-260C-UNLIM
0 to 70
NWM
Samples
SN75HVD3082EDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
VN3082
Samples
SN75HVD3082EDRG4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
VN3082
Samples
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
14-Oct-2022
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
RoHS & Green
NIPDAU
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN75HVD3082EP
ACTIVE
PDIP
P
8
50
N / A for Pkg Type
0 to 70
75HVD3082
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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