SN65HVD485EDGKRG4

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents SN65HVD485E SLLS612E – JUNE 2004 – REVISED DECEMBER 2015 SN65HVD485E Half-Duplex RS-485 Transceiver 1 Features 3 Description • • • • The SN65HVD485E device is a half-duplex transceiver designed for RS-485 data bus networks. Powered by a 5-V supply, it is fully compliant with the TIA/EIA-485A standard. This device is suitable for data transmission up to 10 Mbps over long twistedpair cables and is designed to operate with very low supply current, typically less than 2 mA, exclusive of the load. When the device is in the inactive shutdown mode, the supply current drops below 1 mA. 1 • • • Bus-Pin ESD Protection up to 15 kV 1/2 Unit Load: up to 64 Nodes on a Bus Bus-Open-Failsafe Receiver Glitch-Free Power-Up and Power-Down Bus Inputs and Outputs Available in Small VSSOP-8 Package Meets or Exceeds the Requirements of the TIA/EIA-485A Standard Industry-Standard SN75176 Footprint 2 Applications • • • • • • • Motor Control Power Inverters Industrial Automation Building Automation Networks Industrial Process Control Battery-Powered Applications Telecommunications Equipment The wide common-mode range and high ESD protection levels of this device make it suitable for demanding applications such as: electrical inverters, status/command signals across telecom racks, cabled chassis interconnects, and industrial automation networks where noise tolerance is essential. The SN65HVD485E device matches the industry-standard footprint of the SN75176 device. Power-on reset circuits keep the outputs in a highimpedance state until the supply voltage has stabilized. A thermal-shutdown function protects the device from damage due to system-fault conditions. The SN65HVD485E device is characterized for operation from –40°C to 85°C air temperature. Device Information(1) PART NUMBER PACKAGE SN65HVD485E BODY SIZE (NOM) SOIC (8) 4.91 mm × 3.90 mm VSSOP (8) 3.00 mm × 3.00 mm PDIP (8) 9.81 mm × 6.35 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application Schematic R R RE B DE D R A R A RT RT D A R B A D R RE DE D R RE B DE D B D D R RE DE D 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN65HVD485E SLLS612E – JUNE 2004 – REVISED DECEMBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 4 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 4 4 4 5 5 5 6 6 6 6 7 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions ...................... Thermal Information .................................................. Electrical Characteristics: Driver ............................... Electrical Characteristics: Receiver .......................... Power Dissipation Characteristics ............................ Supply Current .......................................................... Switching Characteristics: Driver .............................. Switching Characteristics: Receiver........................ Dissipation Ratings ................................................. Typical Characteristics ............................................ Parameter Measurement Information .................. 8 9 Detailed Description ............................................ 12 9.1 9.2 9.3 9.4 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 12 12 12 12 10 Application and Implementation........................ 14 10.1 Application Information.......................................... 14 10.2 Typical Application ............................................... 14 11 Power Supply Recommendations ..................... 18 12 Layout................................................................... 18 12.1 Layout Guidelines ................................................. 18 12.2 Layout Example .................................................... 18 13 Device and Documentation Support ................. 19 13.1 13.2 13.3 13.4 13.5 13.6 Device Support...................................................... Documentation Support ........................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 19 20 20 20 20 20 14 Mechanical, Packaging, and Orderable Information ........................................................... 20 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (July 2015) to Revision E • Page Changed 3.3 V To: 5 V at pin VCC in Figure 20 ................................................................................................................... 16 Changes from Revision C (March 2007) to Revision D Page • Added Pin Configuration and Functions section, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ............................................................... 1 • Deleted Ordering Information table ....................................................................................................................................... 1 • Changed Thermal Information table ...................................................................................................................................... 5 • Added Power Dissipation Characteristics table...................................................................................................................... 6 2 Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: SN65HVD485E SN65HVD485E www.ti.com SLLS612E – JUNE 2004 – REVISED DECEMBER 2015 5 Device Comparison Table Improved Replacement for Devices PART NUMBER REPLACE WITH BENEFITS ADM485 SN65HVD485E Better ESD protection (±15 kV versus unspecified) Faster signaling rate (10 Mbps versus 5 Mbps) More nodes on a bus (64 versus 32) Wider power supply tolerance (10% vs 5%) SP485E SN65HVD485E More nodes on a bus (64 versus 32) Wider power supply tolerance (10% versus 5%) LMS485E SN65HVD485E Higher signaling rate (10 Mbps versus 2.5 Mbps) More nodes on a bus (64 versus 32) Wider power supply tolerance (10% versus 5%) DS485 SN65HVD485E Higher signaling rate (10 Mbps versus 2.5 Mbps) Better ESD (±15 kV versus ±2 kV) More nodes on a bus (64 versus 32) Wider power supply tolerance (10% versus 5%) LTC485 SN65HVD485E Better ESD (±15 kV versus ±2 kV) Wider power supply tolerance (10% versus 5%) MAX485E SN65HVD485E Higher signaling rate (10 Mbps versus 2.5 Mbps) More nodes on a bus (64 versus 32) Wider power supply tolerance (10% versus 5%) ST485E SN65HVD485E Higher signaling rate (10 Mbps versus 5 Mbps) Wider power supply tolerance (10% versus 5%) ISL8485E SN65HVD485E More nodes on a bus (64 versus 32) Faster signaling rate (10 Mbps versus 5 Mbps) 6 Pin Configuration and Functions D, DGK, P Packages 8-Pin SOIC, VSSOP, PDIP Top View R RE DE D 1 8 2 7 3 6 4 5 VCC B A GND Pin Functions PIN NAME NO. TYPE DESCRIPTION A 6 Bus input/output Driver output or receiver input (complementary to B) B 7 Bus input/output Driver output or receiver input (complementary to A) D 4 Digital input Driver data input DE 3 Digital input Driver enable, active high GND 5 Reference potential Local device ground R 1 Digital input Receive data output RE 2 Digital input Receiver enable, active low VCC 8 Supply 4.5-V to 5.5-V supply Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: SN65HVD485E 3 SN65HVD485E SLLS612E – JUNE 2004 – REVISED DECEMBER 2015 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) VCC (1) (2) Supply voltage Voltage range at A or B TJ (1) (2) MAX UNIT 7 V V –9 14 Voltage range at any logic pin –0.3 VCC + 0.3 V Receiver output current –24 24 mA Voltage input range, transient pulse, A and B, through 100 Ω (see Figure 15) –50 50 V Junction temperature 170 170 °C Continuous total power dissipation Tstg MIN –0.5 Refer to Dissipation Ratings Storage temperature –65 130 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS001 (1) Bus pins and GND ±15000 All pins ±4000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) UNIT V ±1000 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) MIN NOM MAX UNIT VCC Supply voltage 4.5 5.5 V VI Input voltage at any bus terminal (separately or common mode) –7 12 V VIH High-level input voltage (D, DE, or RE inputs) 2 VCC V VIL Low-level input voltage (D, DE, or RE inputs) VID Differential input voltage Driver IO Output current RL Differential load resistance 1/tUI Signaling rate TA Operating free-air temperature TJ (1) (2) 4 Junction temperature Receiver 0 0.8 V –12 12 V –60 60 –8 8 54 (2) mA Ω 60 0 10 Mbps –40 85 °C –40 130 °C The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this data sheet. See Thermal Information for information on maintenance of this specification for the DGK package. Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: SN65HVD485E SN65HVD485E www.ti.com SLLS612E – JUNE 2004 – REVISED DECEMBER 2015 7.4 Thermal Information SN65HVD485E THERMAL METRIC (1) D (SOIC) DGK (VSSOP) P (PDIP) 8 PINS UNIT 8 PINS 8 PINS RθJA Junction-to-ambient thermal resistance (2) 127 180 153 °C/W RθJC(top) Junction-to-case (top) thermal resistance 51.4 66 40.5 °C/W RθJB Junction-to-board thermal resistance 47.6 108 28.5 °C/W ψJT Junction-to-top characterization parameter 7.9 4.6 17.6 °C/W ψJB Junction-to-board characterization parameter 47 73.1 28.3 °C/W (1) (2) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953). See the Package Thermal Characterization Methodologies application note (SZZA003) for an explanation of this parameter. 7.5 Electrical Characteristics: Driver over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS IO = 0, No load |VOD| Differential output voltage MIN TYP (1) 3 4.3 RL = 54 W (see Figure 3) 1.5 2.3 VTEST = –7 V to 12 V (see Figure 4) 1.5 MAX UNIT V Δ|VOD| Change in magnitude of differential output voltage See Figure 3 and Figure 4 VOC(SS) Steady-state common-mode output voltage See Figure 5 ΔVOC(SS) Change in steady-state common-mode output voltage VOC(PP) Common-mode output voltage See Figure 5 IOZ High-impedance output current See receiver input currents II Input current D, DE –100 100 μA IOS Short-circuit output current –7 V ≤ VO ≤ 12 V (see Figure 9) –250 250 mA MIN TYP (1) MAX UNIT –85 –10 mV (1) –0.2 0 0.2 V 1 2.6 3 V –0.1 0 0.1 V 500 mV μA All typical values are at 25°C and with a 5-V supply. 7.6 Electrical Characteristics: Receiver over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS VIT+ Positive-going input threshold voltage IO = –8 mA VIT– Negative-going input threshold voltage IO = 8 mA Vhys Hysteresis voltage (VIT+ – VIT–) VOH High-level output voltage VID = 200 mV, IOH = –8 mA (see Figure 10) VOL Low-level output voltage VID = –200 mV, IOH = 8 mA (see Figure 10) IOZ High-impedance-state output current VO = 0 to VCC, RE = VCC –200 4 –115 mV 30 mV 4.6 0.15 –1 VIH = 12 V, VCC = 5 V II Bus input current IIH High-level input current (RE) IIL Cdiff (1) V 0.4 V 1 μA 0.5 VIH = 12 V, VCC = 0 0.5 mA VIH = –7 V, VCC = 5 V –0.4 VIH = –7 V, VCC = 0 –0.4 VIH = 2 V –60 –30 μA Low-level input current (RE) VIL = 0.8 V –60 –30 μA Differential input capacitance VI = 0.4 sin (4E6πt) + 0.5 V, DE at 0 V 7 pF All typical values are at 25°C and with a 5-V supply. Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: SN65HVD485E 5 SN65HVD485E SLLS612E – JUNE 2004 – REVISED DECEMBER 2015 www.ti.com 7.7 Power Dissipation Characteristics PARAMETER TEST CONDITIONS P(AVG) Average power dissipation TSD Thermal shut-down junction temperature MIN TYP RL = 54 Ω, Input to D is a 10 Mbps 50% duty cycle square wave VCC at 5.5 V, TJ = 130°C MAX UNIT 219 mW 165 °C 7.8 Supply Current over recommended operating conditions (unless otherwise noted) PARAMETER ICC (1) TEST CONDITIONS MIN TYP (1) MAX UNIT Driver and receiver enabled D at VCC or open or 0 V, DE at VCC, RE at 0 V, No load 2 mA Driver and receiver disabled DE at 0 V, RE at VCC 1 mA D at VCC or open, All typical values are at 25°C and with a 5-V supply. 7.9 Switching Characteristics: Driver over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS tPLH Propagation delay time, low-to-high-level output tPHL Propagation delay time, high-to-low-level output tr Differential output signal rise time tf Differential output signal fall time tsk(p) Pulse skew (|tPHL – tPLH|) tPZH Propagation delay time, high-impedance-to-high-level output MIN TYP MAX RL = 54 Ω, CL = 50 pF (see Figure 6) tPHZ Propagation delay time, high-level-to-high-impedance output tPZL Propagation delay time, high-impedance-to-low-level output UNIT 30 ns 30 ns 25 ns 25 ns 5 ns 150 ns 100 ns 150 ns 100 ns RL = 110 Ω, RE at 0 V (see Figure 7) RL = 110 Ω, RE at 0 V (see Figure 8) tPLZ Propagation delay time, low-level-to-high-impedance output tPZH(SHN) Propagation delay time, shutdown-to-high-level output RL = 110 Ω, RE at VCC (see Figure 7) 2600 ns tPZL(SHDN) Propagation delay time, shutdown-to-low-level output RL = 110 Ω, RE at VCC (see Figure 8) 2600 ns 7.10 Switching Characteristics: Receiver over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH Propagation delay time, low-to-high-level output 200 ns tPHL Propagation delay time, high-to-low-level output 200 ns tsk(p) Pulse skew (|tPHL – tPLH|) tr Output signal rise time 3 ns tf Output signal fall time 3 ns tPZH Output enable time to high level 50 ns tPZL Output enable time to low level 50 ns tPHZ Output enable time from high level 50 ns tPLZ Output enable time from low level 50 ns tPZH(SHDN) Propagation delay time, shutdown-to-high-level output 3500 ns tPZL(SHDN) Propagation delay time, shutdown-to-low-level output 3500 ns 6 VID = -1.5 V to 1.5 V, CL = 15 pF (see Figure 11) CL = 15 pF, DE at 3 V, (see Figure 12 and Figure 13) CL = 15 pF, DE at 0 V, (see Figure 14) Submit Documentation Feedback 6 ns Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: SN65HVD485E SN65HVD485E www.ti.com SLLS612E – JUNE 2004 – REVISED DECEMBER 2015 7.11 Dissipation Ratings PACKAGE (1) JEDEC BOARD MODEL TA < 25°C POWER RATING DERATING FACTOR (2) ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING D (SIOC) Low k (3) 507 mW 4.82 mW/°C 289 mW 217 mW High k (3) 824 mW 7.85 mW/°C 471 mW 353 mW Low k (3) 686 mW 6.53 mW/°C 392 mW 294 mW (3) 394 mW 3.76 mW/°C 255 mW 169 mW (4) 583 mW 5.55 mW/°C 333 mW 250 mW P (PDIP) Low k DGK (VSSOP) (1) (2) (3) (4) High k For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. In accordance with the low-k thermal metric definitions of EIA/JESD51-3. In accordance with the high-k thermal metric definitions of EIA/JESDS1-7. 7.12 Typical Characteristics 80 5 VOD − Differential Output Voltage − V 60 II − Input Bias Current − µA TA = 25°C VCC = 5 V 4.5 40 VCC = 0 V 20 0 VCC = 5 V −20 −40 RL = 120Ω 4 3.5 3 RL = 60Ω 2.5 2 1.5 1 0.5 −60 −8 −6 −4 −2 0 2 4 6 VI − Bus Input Voltage − V 8 10 Figure 1. Bus Input Current vs Bus Input Voltage 12 0 0 10 20 30 40 IO − Differential Output Current − mA 50 Figure 2. Driver Differential Output Voltage vs Differential Output Current Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: SN65HVD485E 7 SN65HVD485E SLLS612E – JUNE 2004 – REVISED DECEMBER 2015 www.ti.com 8 Parameter Measurement Information Test load capacitance includes probe and jig capacitance (unless otherwise specified). Signal generator characteristics: rise time and fall time