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SN65HVD62RGTR

SN65HVD62RGTR

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    QFN16_3X3MM_EP

  • 描述:

    SN65HVD62 AISG 2.0 开关键控同轴调制解调器收发器

  • 数据手册
  • 价格&库存
SN65HVD62RGTR 数据手册
Product Folder Sample & Buy Support & Community Tools & Software Technical Documents SN65HVD62 SLLSE94C – SEPTEMBER 2011 – REVISED MARCH 2015 SN65HVD62 AISG On-Off Keying Coax Modem Transceiver 1 Features 3 Description • • • These transceivers modulate and demodulate signals between the logic (baseband) and a frequency suitable for long coaxial media. 1 • • • • • • • Supply Ranging From 3V to 5.5V Independent Logic Supply of 1.6V to 5.5V Wide Input Dynamic Range of –15dBm to +5dBm for Receiver Power Delivered by the Driver to the Coax can be Adjusted From 0dBm to +6dBm AISG Compliant Output Emission Profile Low-power Standby Mode Direction Control Output for RS-485 Bus Arbitration Supports up to 115 kbps Signaling Integrated Active Bandpass Filter with Center Frequency at 2.176MHz 3mm × 3mm 16-Pin QFN Package The HVD62 receiver integrates an active bandpass filter to enable demodulation of signals even in the presence of spurious frequency components. The filter has a 2.176 MHz center frequency. The transmitter supports adjustable output power levels varying from +0dBm to +6dBm delivered to the 50 Ω coax cable. The HVD62 transmitter is compliant with the spectrum emission requirement provided by the AISG standard. A direction control output is provided which facilitates bus arbitration for an RS-485 interface. These devices integrate an oscillator input for a crystal, and also accept standard clock inputs to the oscillator. 2 Applications • • • The HVD62 is an integrated AISG transceiver designed to be compliant with Antenna Interface Standards Group v2.0 specification. AISG – Interface for Antenna Line Devices Tower Mounted Amplifiers (TMA) General Modem Interfaces Device Information(1) PART NUMBER SN65HVD62 PACKAGE BODY SIZE (NOM) VQFN (16) 3.00 mm x 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 4 Block Diagram Vcc 13 VL 3 1 9 XTAL1 14 XTAL2 15 TXIN DIRSET1 DIRSET2 DIR RXOUT FILTER OOK MOD XTAL Buffer OUTPUT STAGE PREAMP 12 SYNCOUT RES TXOUT 2.176 2 7 6 Control Logic 5 FILTER OOK DEMOD 4 11 Buffer RXIN 2.176 Buffer COMP RECEIVER THRESHOLD 16 GND 8 GND 10 BIAS 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN65HVD62 SLLSE94C – SEPTEMBER 2011 – REVISED MARCH 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Block Diagram........................................................ Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 1 2 3 4 7.1 7.2 7.3 7.4 7.5 7.6 7.7 4 4 4 5 6 7 8 Absolute Maximum Ratings ..................................... ESD Ratings.............................................................. Thermal Information .................................................. Recommended Operating Conditions....................... Electrical Characteristics........................................... Switching Characteristics .......................................... Typical Characteristics .............................................. 8 9 Parameter Measurement Information ................ 11 Detailed Description ............................................ 14 9.1 Overview ................................................................. 14 9.2 Functional Block Diagram ....................................... 14 9.3 Device Functional Modes........................................ 14 10 Application and Implementation........................ 16 10.1 Application Information.......................................... 16 11 Device and Documentation Support ................. 18 11.1 11.2 11.3 11.4 Documentation Support ....................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 18 18 18 18 12 Mechanical, Packaging, and Orderable Information ........................................................... 18 5 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (January 2013) to Revision C Page • Added Device Information table,ESD Ratings table, Device Functional Modes, Application and Implementation section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. .................................................................................................................................................................................. 1 • Moved the Storage temperature From: Thermal Information To: Absolute Maximum Ratings (1) ......................................... 4 • Changed TA in the Recommended Operating Conditions From: MAX = 85°C To: MAX = 105°C ......................................... 5 Changes from Revision A (January 2012) to Revision B Page • Changed Features From: "Power Delivered by the Driver to the Coax can be Adjusted +3dBm to +6dBm" To: "Power Delivered by the Driver to the Coax can be Adjusted 0dBm to +6dBm" ................................................................... 1 • Added Storage temperature to the Thermal Information........................................................................................................ 4 • Change the MIN value of VRES in the ROC table From: 0.84 To: 0.7 V ................................................................................. 5 • Change the TYP value of CC in the ROC table From: 270 To: 220 nF.................................................................................. 5 • Changed the Electrical Characteristics................................................................................................................................... 6 • Changed the Switching Characteristics.................................................................................................................................. 7 • Added the Typical Characteristics section.............................................................................................................................. 8 • Changed the Parameter Measurement Information section................................................................................................. 11 • Changed the Application Information section ....................................................................................................................... 16 Changes from Original (September 2011) to Revision A Page • Changed Pin 4 label (lower right) in the Pin Configuration and Functions diagram from TXIN to RXOUT ........................... 3 • Changed the Pin Functions table by merging the DESCRIPTION cells for pins 5, 6, and 7 and deleted the word DIRSET from the beginning of the second line in that description field. ................................................................................ 3 • Added rows 162 and 163 to the Electrical Characteristics table, under RECEIVER FILTER section ................................... 6 • Added rows 210 and 211 to the Switching Characteristics table ........................................................................................... 7 • Added Table 1 and Table 2 .................................................................................................................................................. 15 • Added Figure 22 State Transition Diagram .......................................................................................................................... 15 2 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: SN65HVD62 SN65HVD62 www.ti.com SLLSE94C – SEPTEMBER 2011 – REVISED MARCH 2015 6 Pin Configuration and Functions RES BIAS RXIN TXOUT RGT (VQFN) Package 16 Pins Top View VCC GND XTAL1 DIRSET1 Exposed text Pad GND DIR VL TXIN RXOUT DIRSET2 SYNCOUT XTAL2 Pin Functions PIN HVD62 PIN DESCRIPTION NAME 1 SYNCOUT Open drain output to synchronize other devices to the 4x-carrier oscillator at XTAL1,2. (8.704 MHz for HVD62) 2 TXIN Digital data bit stream to driver. 3 VL Logic supply voltage for the device. 4 RXOUT Digital data bit stream from receiver. 5 DIR 6 DIRSET2 7 DIRSET1 DIR: Direction control output signal for bus arbitration. DIRSET1 and DIRSET2: Bits to set the duration of DIR DIRSET[2,1]:[L,L]=9.6kbps [L,H]=38.4kbps [H,L]=115kbps [H,H]=Standby Mode 8 GND Ground 9 RES Input voltage to adjust driver output power. Set by external resistors from BIAS pin to GND. 10 BIAS Bias voltage output for setting driver output power by external resistors. 11 RXIN Modulated input signal to the receiver. 12 TXOUT Modulated output signal from the driver. 13 VCC Analog supply voltage for the device. 14 XTAL1 15 XTAL2 Crystal oscillator’s IO pins. Connect a 4 x fC crystal between these pins. Or connect XTAL1 to an 8.704 MHz clock and connect XTAL2 to GND. 16 GND Ground EP Exposed pad. Recommended to be connected to ground plane for best thermal conduction. - Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: SN65HVD62 3 SN65HVD62 SLLSE94C – SEPTEMBER 2011 – REVISED MARCH 2015 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings (1) VALUES UNIT MIN MAX Supply voltage, VCC and VL –0.5 6 V Voltage range at coax pins –0.5 6 V Voltage range at logic pins –0.3 VL + 0.3 V Logic Output Current –20 20 mA TXOUT output current Internally limited SYNCOUT output current Internally limited Junction Temperature, TJ 170 Storage temperature, TSTG –65 Continuous total power dissipation (1) °C 150 See the Thermal Information °C Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7.2 ESD Ratings V(ESD) (1) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) VALUE UNIT ±2000 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. 7.3 Thermal Information SN65HVD62 THERMAL METRIC (1) RGT (VQFN) UNIT (16) PINS RθJA Junction-to-ambient thermal resistance 49.4 RθJCtop Junction-to-case (top) thermal resistance 64.2 RθJB Junction-to-board thermal resistance 22.9 ψJT Junction-to-top characterization parameter 1.7 ψJB Junction-to-board characterization parameter 22.9 RθJCbot Junction-to-case (bottom) thermal resistance 25.0 (1) 4 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: SN65HVD62 SN65HVD62 www.ti.com SLLSE94C – SEPTEMBER 2011 – REVISED MARCH 2015 7.4 Recommended Operating Conditions MIN NOM MAX UNIT VCC Analog supply voltage VL Logic supply voltage VI(pp) Input signal amplitude at RXIN VIH High-level input voltage VIL Low-level input voltage 1/tUI Data signaling rate FOSC Oscillator frequency TA Operating free-air temperature –40 105 °C TJ Junction Temperature –40 125 °C TXIN, DIRSET1, DIRSET2 3 5.5 1.6 5.5 V 1.12 Vpp 70%VL VL 70%VCC VCC TXIN, DIRSET1, DIRSET2 0 30%VL XTAL1, XTAL2 0 30%VCC XTAL1, XTAL2 9.6 HVD62 –30 ppm 8.704 V V V 115 kbps 30 ppm MHz Load impedance between TXOUT to RXIN 50 Load impedance between RXIN and GND at fC (channel) 50 R1 Bias resistor between BIAS and RES 4.1 kΩ R2 Bias resistor between RES and GND 10 kΩ RSYNC Pull-up resistor between SYNCOUT and VCC 1 kΩ VRES Voltage at RES pin CC Coupling capacitance between RXIN and Coax (channel) CBIAS Capacitance between BIAS and GND RLOAD 0.7 Ω 1.5 nF 1 µF Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: SN65HVD62 V 220 5 SN65HVD62 SLLSE94C – SEPTEMBER 2011 – REVISED MARCH 2015 www.ti.com 7.5 Electrical Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 28 33 25 31 27 33 12 17 UNIT POWER SUPPLY 100 TXIN = L (Active) 101 TXIN = H (Quiescent) 102 ICC Supply current (VCC) TXIN = 115 kbps, 50% duty cycle 99 DIRSET1 = L DIRSET2 = H (Standby) DIRSET1 = DIRSET2=H 103 IL Logic supply current TXIN = H, RXIN = DC input 104 ΔVRXIN/ ΔVCC Receiver power supply rejection ratio VTXIN = VL 50 45 60 mA µA dB LOGIC PINS 112 VOH High-level logic output voltage (RXOUT, DIR) IOH = –4 mA for VL > 2.4V, IOH = –2 mA for VL < 2.4V 113 VOL Low-level logic output voltage (RXOUT, DIR) IOL = 4 mA for VL > 2.4V, IOL = 2 mA for VL < 2.4V 114 IIH/IIL Logic input current (DIRSET1/2) IIH/IIL Logic input current (TXIN) 90%VL V 10%VL V -1 10 µA -2 1 µA COAX DRIVER 130 132 130A 132A 134 134A VOPP Peak-to-peak output voltage at device pin TXOUT (See Figure 19) VRES = 1.5 V (Maximum setting) VOPP Peak-to-peak voltage at coax out (See Figure 19) VRES = 1.5 V VOZ Off-state output voltage 136 41 fo Output frequency (HVD62) ∆f Output frequency variation 143 144 145 2.5 1.17 5 VRES = 0.7 V At coax out Coupled to coaxial cable with characteristic impedance 50 Ohms, as shown in Figure 1. With a recommended 470 pF capacitor between RXIN and GND. Measurements above 150 MHz are determined by setup. 1.3 6 -0.6 At TXOUT Output emissions 142 2.24 VRES = 0.7 V (Minimum setting) 0.3 VPP dBm 1 mVpp -60 dBm Conforms to AISG spectrum emissions mask, 3GPP TS 25.461, see Figure 21 2.176 –100 MHz 100 ppm At 100 kHz 0.03 Ω At 10 MHz 3.5 Ω Short-circuit output current TXOUT is also protected by a thermal shutdown circuit during short-circuit faults 300 450 mA VIT Input threshold fIN = 2.176 MHz ZIN Input impedance Zo Output impedance | IOS | COAX RECEIVER 152 152A 154 79 112 158 mVPP –18 –15 –12 dBm f = fO 11 21 Passband VRXIN = 1.12VP_P 1.1 4.17 MHz Receiver rejection range 2.176MHz carrier amplitude of 112.4 mVPP, Frequency band of spurious components with 800 mVPP allowed. 1.1 4.17 MHz Receiver noise filter time (slow bit rate) DIRSET for 9.6kbps 4 Receiver noise filter time (fast bit rate) DIRSET for > 9.6 kbps 2 Input leakage current XTAL1, XTAL2, 0V < VIN < VCC Output low voltage SYNCOUT, with 1 kΩ resistor from SYNCOUT to VCC kΩ RECEIVER FILTER 160 161 162 163 fPB fREJ tnoise filter µs XTAL AND SYNC 171 172 6 II VOL Submit Documentation Feedback –15 15 µA 0.4 V Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: SN65HVD62 SN65HVD62 www.ti.com SLLSE94C – SEPTEMBER 2011 – REVISED MARCH 2015 7.6 Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS tpAQ, tpQA Coax driver propagation delay See Figure 19 202 tr, tf Coax receiver output rise/fall time CL = 15 pF, RL = 1 kΩ, See Figure 19 203 tPHL, tPLH Receiver propagation delay See Figure 20 204 Duty Cycle Coax receiver output duty cycle 201 214 206 207 MIN 5.5 Direction control active duration 208 tDIR 210 tDIS Standby disable delay 211 tEN Standby enable delay Skew µs 20 ns 11 µs 60% VRXIN(ON) = 200 mVpp, VRXIN(OFF) < 5 mVpp, 50% duty cycle 40% 60% 1667 DIRSET2 = GND, DIRSET1 = VL 417 DIRSET2 = VL, DIRSET1 = VL 137 270 300 mVPP at 2.176 MHz on RXIN Product Folder Links: SN65HVD62 µs ns 2 2 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated UNIT 5 40% Direction control skew (DIR to RXOUT) 209 MAX VRXIN(ON) = 630 mVpp, VRXIN(OFF) < 5 mVpp, 50% duty cycle DIRSET2 = DIRSET1 = GND or OPEN tDIR TYP ms 7 SN65HVD62 SLLSE94C – SEPTEMBER 2011 – REVISED MARCH 2015 www.ti.com 7.7 Typical Characteristics 10 ±60 AISG Mask 50% Duty Cycle CF = 470pF ±70 ±10 TRANSMITTER OUTPUT (dBm) TRANSMITTER OUTPUT (dBm) 0 ±20 AISG Mask ±30 ±40 ±50 50% Duty Cycle CF = 470pF ±80 ±90 ±100 ±60 ±110 ±70 ±120 ±80 0 10M 20M FREQUENCY (Hz) 30M 30M 130M 230M FREQUENCY (Hz) 330M C00 C00 Figure 1. Low Frequency Emissions Spectrum with 9.6 kbps Signaling Rate Figure 2. High Frequency Emissions Spectrum with 9.6 kbps Signaling Rate 10 ±60 AISG Mask 50% Duty Cycle cF = 470 pF 0 ±70 TRANSMITTER OUTPUT (dBm) TRANSMITTER OUTPUT (dBm) ±10 ±20 AISG Mask ±30 ±40 50% Duty Cycle CF = 470pF ±80 ±90 ±100 ±50 ±60 ±110 ±70 ±120 ±80 0 10M 20M FREQUENCY (Hz) 30M 30M 130M 230M FREQUENCY (Hz) 330M C00 C00 Figure 3. Low Frequency Emissions Spectrum with 38.4 kbps Signaling Rate Figure 4. High Frequency Emissions Spectrum with 38.4 kbps Signaling Rate 10 ±60 AISG Mask 50% Duty cycle cF = 470 pF ±70 ±10 TRANSMITTER OUTPUT (dBm) TRANSMITTER OUTPUT (dBm) 0 ±20 AISG Mask ±30 ±40 ±50 50% Duty Cycle CF = 470pF ±80 ±90 ±100 ±60 ±110 ±70 ±120 ±80 0 10M 20M FREQUENCY (Hz) 30M 30M Figure 5. Low Frequency Emissions Spectrum with 115.2 kbps Signaling Rate 8 130M 230M 330M FREQUENCY (Hz) C00 C00 Figure 6. High Frequency Emissions Spectrum with 115.2 kbps Signaling Rate Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: SN65HVD62 SN65HVD62 www.ti.com SLLSE94C – SEPTEMBER 2011 – REVISED MARCH 2015 40 6 35 5 30 4 TRANSMITTER OUTPUT (dBm) TRANSMITTER OUTPUT IMPEDANCE (Ÿ) Typical Characteristics (continued) 25 20 15 10 5 3 2 1 0 ±1 0 ±2 0.1M 1M 10M FREQUENCY (Hz) 0.7 0.9 1.1 VRES (V) 1.3 1.5 C00 C00 Figure 7. Transmitter Output Impedance Figure 8. Transmit Power Adjustment 13 27 12.8 QUIESCENT CURRENT (mA) QUIESCENT CURRENT (mA) TXIN = VL 12.9 TXIN = VL 26.5 26 25.5 25 12.7 12.6 12.5 12.4 12.3 12.2 24.5 12.1 24 12 3 3.5 4 4.5 5 3 5.5 3.5 SUPPLY VOLTAGE (V) 4 4.5 5 C00 C00 Figure 9. Supply Current versus Supply Voltage while Transmitting Figure 10. Supply Current versus Supply Voltage in Standby Mode 13.2 7 13.1 6 TRANSMITTER OUTPUT (dBm) QUIESCENT CURRENT (mA) 5.5 SUPPLY VOLTAGE (V) 13 12.9 12.8 12.7 12.6 5 4 3 2 1 12.5 0 12.4 -40 -10 20 50 80 3 110 TEMPERATURE (OC) 3.5 4 4.5 5 5.5 SUPPLY VOLTAGE (V) C00 C00 Figure 11. Supply Current versus Temperature in Standby Mode Figure 12. Transmitter Output Power versus Supply Voltage Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: SN65HVD62 9 SN65HVD62 SLLSE94C – SEPTEMBER 2011 – REVISED MARCH 2015 www.ti.com Typical Characteristics (continued) 30k 7 25k RECEIVER INPUT IMPEDANCE (Ÿ) TRANSMITTER OUTPUT (dBm) 6 5 4 3 2 20k 15k 10k 5k 1 0 0 -40 -10 20 50 80 TEMPERATURE 100 110 1k (OC) 10k 100k 1M 5M FREQUENCY (Hz) C00 Figure 13. Transmitter Output Power versus Temperature C00 Figure 14. Receiver Input Impedance versus Frequency 0.16 360 DIR RECEIVER OUTPUT DELAY (nS) RECEIVER IINPUT THRESHOLD (V) 0.15 0.14 0.13 RTXOUT=STABLE LOW 0.12 0.11 RXOUT=STABLE HIGH 0.1 355 350 345 0.09 0.08 340 -40 -10 20 50 80 110 -40 -10 TEMPERATURE (OC) 20 50 80 110 TEMPERATURE (OC) C00 Figure 15. Receiver Input Threshold versus Temperature C00 Figure 16. DIR Output Delay versus Temperature 60 RECEIVER OUTPUT DUTYCYCLE (%) RECEIVER OUTPUT DUTYCYCLE (%) 60 56 52 48 44 40 50 40 30 20 10 0 -10 -7 -4 -1 2 5 -10 RECEIVER INPUT (dBm) -4 -1 2 5 RECEIVER INPUT (dBm) C00 Figure 17. Receiver Duty Cycle with 9.6 kbps Signaling Rate 10 -7 C00 Figure 18. Receiver Duty Cycle with 115.2 kbps Signaling Rate Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: SN65HVD62 SN65HVD62 www.ti.com SLLSE94C – SEPTEMBER 2011 – REVISED MARCH 2015 8 Parameter Measurement Information Signal generator rate is 115 kbps, 50% duty cycle, rise and fall times less than 6 nsec, nominal output levels 0V and 3V. Coupling capacitor Cc is 220 nF. Driver Amplitude Adjust RAMP XTAL2 2.176 MHz Crystal RES TXOUT TXIN 50 W XTAL2 Signal generator Coax Out 50 W Cc RXIN VL 0.5 VL TXIN tpQA tpAQ Vpk 0.5 Vpk TXOUT Figure 19. Measurement of Modem Driver Output Voltage With 50 Ω Loads Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: SN65HVD62 11 SN65HVD62 SLLSE94C – SEPTEMBER 2011 – REVISED MARCH 2015 www.ti.com Parameter Measurement Information (continued) TXOUT 50 2.176 MHz Signal Coax In Received Data Out Cc RXIN Direction Control Vpk 0.5 VL RXIN VL 0.5 VL RXOUT tPHL tPLH VL 0.5 VL DIR tDIRSKEW Figure 20. Measurement of Modem Receiver Propagation Delays 12 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: SN65HVD62 SN65HVD62 www.ti.com SLLSE94C – SEPTEMBER 2011 – REVISED MARCH 2015 Parameter Measurement Information (continued) Emissions spectrum with 50% duty cycle OOK and VRES=1.5V conforms to TS 25.461 10 2.076, 5 2.276, 5 0 Emissions (dBm) with OOK and VRES=1.5V 1.976, -5 2.376, -5 -10 -20 1.676, -25 2.676, -25 -30 10, -36 1, -36 20, -36 -40 -50 -60 30, -67 -70 0.1 1 10 100 Frequency (MHz) Figure 21. AISG Emissions Template Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: SN65HVD62 13 SN65HVD62 SLLSE94C – SEPTEMBER 2011 – REVISED MARCH 2015 www.ti.com 9 Detailed Description 9.1 Overview If DIRSET1 and DIRSET2 are in a logic High state, the device will be in STANDBY mode. While in STANDBY mode, the Receiver functions normally, detecting carrier frequency activity on the RXIN pin and setting the RXOUT state as discussed below. But the Transmitter circuits are not active in STANDBY, thus the TXOUT pin is idle regardless of the logic state of TXIN. The supply current in STANDBY mode is significantly reduced, allowing power savings when the node is not transmitting. 9.2 Functional Block Diagram Vcc 13 VL 3 1 9 XTAL1 14 XTAL2 15 TXIN DIRSET1 DIRSET2 DIR RXOUT FILTER OOK MOD XTAL Buffer OUTPUT STAGE PREAMP 12 SYNCOUT RES TXOUT 2.176 2 7 6 Control Logic 5 FILTER OOK DEMOD 4 11 Buffer RXIN 2.176 Buffer COMP RECEIVER THRESHOLD 16 GND 8 GND 10 BIAS 9.3 Device Functional Modes When not in STANDBY mode, the default power-on state is IDLE. When in IDLE mode, RXOUT is High, and TXOUT is quiet. The device transitions to RECEIVE mode when a valid modulated signal is detected on the RXIN line the device transitions to TRANSMIT mode when TXIN goes Low. The device stays in either RECEIVE or TRANSMIT mode until DIR Timeout (nominal 16 bit times) after the last activity on RXOUT or TXIN. When in RECEIVE mode: • RXOUT responds to all valid modulated signals on RXIN, whether from the local transmitter, a remote transmitter, or long noise burst. • TXOUT responds to TXIN, generating 2.176 MHz signals on TXOUT when TXIN is Low, and TXOUT is quiet when TXIN is High. (In normal operation, TXIN is expected to remain High when the device is in RECEIVE mode). • The device stays in RECEIVE mode until 16 bit times after the last rising edge on RXOUT, caused by valid modulated signal on the RXIN line. When in TRANSMIT mode: • RXOUT stays High, regardless of the input signal on RXIN. • TXOUT responds to TXIN, generating 2.176 MHz signals on TXOUT when TXIN is Low, and TXOUT is quiet when TXIN is High. • The device stays in TRANSMIT mode until 16 bit times after TXIN goes High. 14 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: SN65HVD62 SN65HVD62 www.ti.com SLLSE94C – SEPTEMBER 2011 – REVISED MARCH 2015 Device Functional Modes (continued) Table 1. Driver Function Table (1) TXIN [DIRSET1, DIRSET2] H [L,L], [L,H] or [H,L] L X (1) TXOUT COMMENT < 1 mVPP at 2.176 MHz Driver not active VOPP at 2.176 MHz [H,H] Driver active < 1 mVPP at 2.176 MHz Standby mode H = High, L = Low, X = Indeterminate Table 2. Receiver and DIR Function Table (1) RXIN RXOUT DIR COMMENT (see Figure 22) H L No outgoing or incoming signal < VIT at 2.176 MHz for less than tDIR Timeout H H Incoming '1' bit, DIR stays HIGH for DIR Timeout > VIT at 2.176 MHz for longer than tnoise filter L H Incoming '0' bit, DIR output is HIGH H L Outgoing message, DIR stays LOW for DIR Timeout IDLE mode (not transmitting or receiving) < VIT at 2.176 MHz for longer than DIR timeout RECEIVE mode (not already transmitting) TRANSMIT mode (not already receiving) X (1) H = High, L = Low Transmit 0 RXIN 9 TXOUT=Active DIR = L Receive 0 RXOUT = L DIR = H TXIN ; IDLE TXIN 9 RXOUT = H TXOUT=Idle DIR = L TXIN ; Transmit 1 RXIN 9 RXIN ; Receive 1 DIR Timeout TXOUT=Idle DIR = L DIR Timeout RXOUT = H DIR = H Figure 22. State Transition Diagram Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: SN65HVD62 15 SN65HVD62 SLLSE94C – SEPTEMBER 2011 – REVISED MARCH 2015 www.ti.com 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.1 Application Information 10.1.1 Driver Amplitude Adjust The SN65HVD62 can provide up to 2.5 V peak-to-peak of output signal at the TXOUT pin to compensate for potential loss within the external filter, cable, connections, and termination. External resistors are used to set the amplitude of the modulated driver output signal. Resistors connected across RES and BIAS set the output amplitude. The maximum peak-to-peak voltage at TXOUT is 2.5 V, corresponding to +6 dBm on the coaxial cable. The TXOUT voltage level can be adjusted by choice of resistors to set the voltage at the RES pin. according to the following equation: VTXOUT (VP-P) = (2.5 VP-P x VRES (V))/1.5 V VRES (V) = 1.5 V x R2/(R1 + R2) VTXOUT (VP-P) = 2.5 VP-P x R2/(R1 + R2). (1) The voltage at the RES pin should be between 0.7 V and 1.5 V. Connect RES directly to the BIAS (R1 = 0 Ω) for maximum output level of 2.5 V peak-to-peak. This gives a minimum voltage level at TXOUT of 1.2 V peak-topeak, corresponding to about 0 dBm at the coaxial cable. A 1 μF capacitor should be connected between the BIAS pin and GND. To obtain a nominal power level of +3 dBm at the feeder cable as the AISG standard requires, use R1 = 4.1k Ω and R2 = 10k Ω that provide 1.78 VP-P at TXOUT. 10.1.2 Direction Control In many applications the mast-top modem which receives data from the base will then distribute the received data through an RS-485 network to several mast-top devices. When the mast-top modem receives the first logic 0 bit (active modulated signal) it will take control of the mast-top RS-485 network by asserting the Direction Control signal. The duration of the Direction Control assertion should be optimized to pass a complete message of length B bits at the known signaling rate (1/tBIT) before relinquishing control of the mast-top RS-485 network. For example, if the messages are 10 bits in length (B=10) and the signaling rate is 9600 bits per second (tBIT = 0.104 msec) then a positive pulse of duration 1.7 msec is sufficient (with margin to allow for network propagation delays) to enable the mast-top RS-485 drivers to distribute each received message. Coax In Data Out Direction 10.1.3 Direction Control Time Constant The time constant for the Direction Control function can be set by the Control Mode pins, DIRSET1/DIRSET2. These pins should be set to correspond to the desired data rate. With no external connections to the Control Mode pins, the internal time constant is set to the maximum value, corresponding to the minimum data rate. 16 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: SN65HVD62 SN65HVD62 www.ti.com SLLSE94C – SEPTEMBER 2011 – REVISED MARCH 2015 Application Information (continued) 10.1.4 Conversion Between dBm and Peak-to-peak Voltage dBm = 20 × LOG10 [Volts-pp / SQRT(0.008 × Zo)] = 20 × LOG10 [Volts-pp / 0.63] for Zo = 50 Ω Volts-pp = SQRT(0.008 × Zo) × 10(dBm/20) = 0.63 × 10(dBm/20) for Zo = 50 Ω (2) (3) The following table shows conversions between dBm and peak-to-peak voltage with 50 Ω load, for various levels of interest including reference levels from the 3GPP TS 25.461 Technical Specification. SIGNAL ON COAX (Iuant Layer 1) dBm Vpp (V) Maximum Driver ON Signal 5 1.12 Nominal Driver ON Signal 3 0.89 Minimum Driver ON Signal 1 0.71 AISG Maximum Receiver Threshold –12 0.16 Nominal Receiver Threshold –15 0.11 Minimum Receiver Threshold –18 0.08 Maximum Driver OFF Signal –40 0.006 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: SN65HVD62 17 SN65HVD62 SLLSE94C – SEPTEMBER 2011 – REVISED MARCH 2015 www.ti.com 11 Device and Documentation Support 11.1 Documentation Support 11.2 Trademarks All trademarks are the property of their respective owners. 11.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 18 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: SN65HVD62 PACKAGE OPTION ADDENDUM www.ti.com 14-Aug-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN65HVD62RGTR ACTIVE VQFN RGT 16 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 HVD62 SN65HVD62RGTT ACTIVE VQFN RGT 16 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 HVD62 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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SN65HVD62RGTR
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