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SN65HVD63
ZHCSE43 – JULY 2015
SN65HVD63 AISG® 开关键控同轴调制解调器收发器
1 特性
•
•
•
1
•
•
•
•
•
•
•
3 说明
3V 至 5.5V 电源范围
1.6V 至 5.5V 独立逻辑电源
–15dBm 至 +5dBm 接收器
宽输入动态范围
可在 0dBm 至 6dBm 范围内调节
驱动器为同轴电缆提供的功率
AISG® 符合 V2.0 的输出辐射配置文件
同时符合即将推行的 AISG V3.0 规范
低功耗待机模式
针对 RS-485 总线仲裁的
方向控制输出
支持最高达 115kbps 的信号传输速率
集成有源带通滤波器的中心频率
为 2.176MHz
16 引脚 3mm × 3mm 超薄型四方扁平无引线
(VQFN) 封装
SN65HVD63 收发器对逻辑（基带）接口和适用于长
同轴介质的频率之间的信号进行调制和解调，以便无线
设备之间进行有线数据传输。
SN65HVD63 器件是一款集成 AISG 收发器，旨在满
足即将推行的“天线接口标准组织 v3.0 规范”的要求。
SN65HVD63 接收器集成了一个有源带通滤波器，这
样即使存在寄生频率组件仍然能够解调信号。 该滤波
器的中心频率为 2.176MHz。
发送器支持在 +0dBm 至 6dBm 的范围内调节为 50Ω
同轴电缆提供的输出功率。 SN65HVD63 发送器符合
AISG 标准针对发射频谱的要求。
该器件提供的方向控制输出使得对 RS-485 接口的总线
仲裁更加便捷。 该器件为晶振集成了一个振荡器输
入，并且接受到振荡器的标准时钟输入。
2 应用
•
•
•
器件信息(1)
AISG - 针对天线线路器件的接口
塔顶放大器 (TMA)
普通调制解调器 (Modem) 接口
器件型号
SN65HVD63
封装
封装尺寸（标称值）
VQFN (16)
3.00mm x 3.00mm
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
框图
VL
VCC
3
13
1
9
XTAL1
14
XTAL2
15
SYNCOUT
RES
FILTER
XTAL
Buffer
OOK
MOD
OUTPUT
STAGE
PREAMP
12
TXOUT
2.176–MHz
TXIN
DIRSET1
DIRSET2
DIR
RXOUT
2
7
6
Control
Logic
FILTER
5
OOK
DEMOD
4
Buffer
11
Buffer
RXIN
2.176–MHz
COMP
RECEIVER
THRESHOLD
16
8
10
GND
GND
BIAS
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLLSEO3
SN65HVD63
ZHCSE43 – JULY 2015
www.ti.com.cn
目录
1
2
3
4
5
6
7
8
9
特性 ..........................................................................
应用 ..........................................................................
说明 ..........................................................................
修订历史记录 ...........................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
4
4
4
4
6
7
8
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
9.2 Functional Block Diagram ....................................... 12
9.3 Feature Description................................................. 12
9.4 Device Functional Modes........................................ 13
10 Application and Implementation........................ 15
10.1 Application Information.......................................... 15
10.2 Typical Application ............................................... 16
11 Power Supply Recommendations ..................... 18
12 Layout................................................................... 18
12.1 Layout Guidelines ................................................. 18
12.2 Layout Example .................................................... 18
13 器件和文档支持 ..................................................... 19
13.1
13.2
13.3
13.4
13.5
Parameter Measurement Information ................ 11
Detailed Description ............................................ 12
相关文档 ...........................................................
社区资源................................................................
商标 .......................................................................
静电放电警告.........................................................
Glossary ................................................................
19
19
19
19
19
14 机械、封装和可订购信息 ....................................... 19
9.1 Overview ................................................................. 12
4 修订历史记录
2
日期
修订版本
注释
2015 年 7 月
*
首次发布。
Copyright © 2015, Texas Instruments Incorporated
SN65HVD63
www.ti.com.cn
ZHCSE43 – JULY 2015
5 Device Comparison Table
PART NUMBER
STANDARD SUPPORTED
SN65HVD62
AISG 2.0
SN65HVD63
SPURIOUS FREQUENCY
RANGE
MAXIMUM LEVEL
≤ 1.1 MHz
2 dBm (793 mVPP)
AISG 3.0
≤ 4.17 MHz
2 dBm (793 mVPP)
≤ 1.35 MHz
–13 dBm (142 mVPP)
≤ 3.5 MHz
–13 dBm (142 mVPP)
6 Pin Configuration and Functions
VCC
13
XTAL1
14
TXOUT
RXIN
BIAS
RES
12
11
10
9
RGT Package
16-Pin VQFN With Exposed Thermal Pad
Top View
8
GND
7
DIRSET1
Exposed
Pad
5
DIR
RXOUT
SYNCOUT
4
16
3
GND
VL
DIRSET2
2
6
TXIN
15
1
XTAL2
Pin Functions
PIN
NAME
DESCRIPTION
NO.
TYPE
BIAS
10
O
Bias voltage output for setting driver output power by external resistors
DIR
5
O
Direction control output signal for bus arbitration
DIRSET1
7
—
DIRSET2
6
—
DIRSET1 and DIRSET2: Bits to set the duration of DIR
DIRSET[2:1]: [L:L] = 9.6 kbps; [L:H] = 38.4 kbps; [H:L] = 115 kbps; [H:H] = standby mode
—
Ground
GND
8
16
RES
9
P
Input voltage to adjust driver output power that is set by external resistors from BIAS pin to GND
RXIN
11
I
Modulated input signal to the receiver
RXOUT
4
O
Digital data bit stream from receiver
SYNCOUT
1
O
Open-drain output to synchronize other devices to the 4x-carrier oscillator at XTAL1 and XTAL2
TXIN
2
I
Digital data bit stream to driver
TXOUT
12
O
Modulated output signal from the driver
VCC
13
P
Analog supply voltage for the device
VL
3
P
Logic supply voltage for the device
XTAL1
14
I/O
XTAL2
15
I/O pins of the crystal oscillator. Connect a 4 × fC crystal between these pins or connect XTAL1 to an 8.704-MHz clock and
connect XTAL2 to GND.
EP
—
—
Exposed pad. Connection to ground plane is recommended for best thermal conduction.
Copyright © 2015, Texas Instruments Incorporated
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ZHCSE43 – JULY 2015
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7 Specifications
7.1 Absolute Maximum Ratings (1)
MIN
MAX
UNIT
Supply voltage, VCC and VL
–0.5
6
V
Voltage at coax pins
–0.5
6
V
Voltage at logic pins
–0.3
VVL + 0.3
V
Logic output current
–20
20
mA
TXOUT output current
Internally limited
SYNCOUT output current
Internally limited
Junction temperature, TJ
170
Continuous total power dissipation
Storage temperature, Tstg (2)
(1)
(2)
°C
See the Thermal Information
–65
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Applicable before the device is installed in the final product.
7.2 ESD Ratings
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
VALUE
UNIT
±2000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
VCC
Analog supply voltage
VL
Logic supply voltage
VI(pp)
Input signal amplitude at RXIN
VIH
High-level input voltage
VIL
Low-level input voltage
1/tUI
Data signaling rate
FOSC
Oscillator frequency
TXIN, DIRSET1, DIRSET2
NOM
MAX
5.5
V
1.6
5.5
V
1.12
Vpp
70%VL
VL
70%VCC
VCC
TXIN, DIRSET1, DIRSET2
0
30%VL
XTAL1, XTAL2
0
30%VCC
XTAL1, XTAL2
UNIT
3
9.6
–30 ppm
8.704
V
V
115
kbps
30 ppm
MHz
Ω
Load impedance between TXOUT to RXIN
50
Load impedance between RXIN and GND at fC (channel)
50
Ω
R1
Bias resistor between BIAS and RES
4.1
kΩ
R2
Bias resistor between RES and GND
10
kΩ
RSYNC
Pullup resistor between SYNCOUT and VCC
VRES
Voltage at RES pin
CC
Coupling capacitance between RXIN and coax (channel)
CBIAS
Capacitance between BIAS and GND
TA
Operating free-air temperature
–40
105
°C
TJ
Junction temperature
–40
125
°C
ZLOAD
1
0.7
kΩ
1.5
220
V
nF
1
µF
7.4 Thermal Information
THERMAL METRIC (1)
RθJA
(1)
4
Junction-to-ambient thermal resistance
VQFN
RGT16 Pins
49.4
UNIT
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
版权 © 2015, Texas Instruments Incorporated
SN65HVD63
www.ti.com.cn
ZHCSE43 – JULY 2015
Thermal Information (接
接下页)
THERMAL METRIC (1)
VQFN
RGT16 Pins
UNIT
RθJCtop
Junction-to-case (top) thermal resistance
64.2
°C/W
RθJB
Junction-to-board thermal resistance
22.9
°C/W
ψJT
Junction-to-top characterization parameter
1.7
°C/W
ψJB
Junction-to-board characterization parameter
22.9
°C/W
RθJCbot
Junction-to-case (bottom) thermal resistance
25
°C/W
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ZHCSE43 – JULY 2015
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7.5 Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
TXIN = L (active)
28
33
TXIN = H (quiescent)
25
31
TXIN = 115 kbps,
50% duty cycle
27
33
12
17
UNIT
POWER SUPPLY
ICC
Supply current
DIRSET1 = L
DIRSET2 = H
DIRSET1 = H, DIRSET2 = H (standby)
IVL
Logic supply current
TXIN = H, RXIN = DC input
PSRR
Receiver power supply rejection ratio
VTXIN = VL
VOH
High-level logic output voltage
(RXOUT, DIR)
IOH = –4 mA for VL > 2.4 V,
IOH = –2 mA for VL < 2.4 V
VOL
Low-level logic output voltage
(RXOUT, DIR)
IOL = 4 mA for VL > 2.4 V,
IOL = 2 mA for VL < 2.4 V
50
45
60
mA
µA
dB
LOGIC PINS
90%VVL
V
10%VV
V
L
COAX DRIVER
VO(PP)
Peak-to-peak output voltage at device pin
TXOUT (see 图 19)
VRES = 1.5 V (Maximum setting)
VO(PP)
Peak-to-peak voltage at coax out
(see 图 19)
VRES = 1.5 V
VO(OFF)
Off-state output voltage
Output emissions
fO
Output frequency
∆f
Output frequency variation
ZO
Output impedance
| IOS |
Short-circuit output current
2.24
VRES = 0.7 V (Minimum setting)
2.5
1.17
5
VRES = 0.7 V
1.3
6
–0.6
At TXOUT
At coax out
0.3
VPP
dBm
1
mVpp
–60
dBm
Coupled to coaxial cable with characteristic
impedance of 50 Ω, as shown in 图 1 (1) (2)
N/A
2.176
–100
MHz
100
ppm
At 100 kHz
0.03
At 10 MHz
3.5
TXOUT is also protected by a thermal shutdown
circuit during short-circuit faults
300
450
mA
79
112
158
mVPP
–12
dBm
Ω
COAX RECEIVER
VIT
Input threshold
fIN = 2.176 MHz
–18
–15
ZIN
Input impedance
f = fO
11
21
Passband
VRXIN = 1.12VP_P
1.1
4.17
MHz
Receiver rejection range
2.176-MHz carrier amplitude of 112.4 mVPP, frequency
band of spurious components with 800 mVPP allowed.
1.1
4.17
MHz
Receiver noise filter time (slow bit rate)
DIRSET for 9.6 kbps
4
µs
Receiver noise filter time (fast bit rate)
DIRSET for > 9.6 kbps
2
µs
kΩ
RECEIVER FILTER
fPB
fREJ
tnoise
filter
XTAL AND SYNC
II
Input leakage current
XTAL1, XTAL2, 0V < VIN < VCC
VOL
Output low voltage
SYNCOUT, with 1-kΩ resistor from SYNCOUT to VCC
(1)
(2)
6
–15
15
µA
0.4
V
Specified by design with a recommended 470-pF capacitor between RXIN and GND. Measurements above 150 MHz are determined by
setup.
Conforms to AISG spectrum emissions mask, 3GPP TS 25.461, see 图 21.
版权 © 2015, Texas Instruments Incorporated
SN65HVD63
www.ti.com.cn
ZHCSE43 – JULY 2015
7.6 Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tpAQ, tpQA
Coax driver propagation delay
See 图 19
tr, tf
Coax receiver output rise/fall time
CL = 15 pF, RL = 1 kΩ; see 图 19
tPHL, tPLH
Receiver propagation delay
See 图 20
Coax receiver output duty cycle
MIN
Direction control active duration
MAX
5
5.5
UNIT
µs
20
ns
11
µs
VRXIN(ON) = 630 mVpp, VRXIN(OFF) < 5 mVpp,
50% duty cycle
40%
60%
VRXIN(ON) = 200 mVpp, VRXIN(OFF) < 5 mVpp,
50% duty cycle
40%
60%
DIRSET2 = GND or OPEN, DIRSET1 = GND
or OPEN
tDIR
TYP
1667
DIRSET2 = GND, DIRSET1 = VL
417
DIRSET2 = VL, DIRSET1 = VL
137
µs
tDIRSKEW
Direction control skew
(DIR to RXOUT)
tdis
Standby disable delay
300 mVPP at 2.176 MHz on RXIN
2
ms
ten
Standby enable delay
300 mVPP at 2.176 MHz on RXIN
2
ms
版权 © 2015, Texas Instruments Incorporated
270
ns
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ZHCSE43 – JULY 2015
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7.7 Typical Characteristics
-50
10
AISG Mask
AISG Mask
-60
Transmitter Output (dBm)
Transmitter Output (dBm)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-70
-120
30M
-80
0
10M
20M
30M
Frequency (Hz)
50% Duty Cycle
130M
D002
50% Duty Cycle
CF = 470 pF
230M
Frequency (Hz)
-50
10
AISG Mask
AISG Mask
-60
Transmitter Output (dBm)
Transmitter Output (dBm)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-70
-120
30M
-80
0
10M
20M
30M
Frequency (Hz)
50% Duty Cycle
130M
D004
50% Duty Cycle
CF = 470 pF
230M
Frequency (Hz)
330M
D005
CF = 470 pF
图 4. High-Frequency Emissions Spectrum
With 38.4-kbps Signaling Rate
图 3. Low-Frequency Emissions Spectrum
With 38.4-kbps Signaling Rate
10
-50
AISG Mask
AISG Mask
0
-60
-10
Transmitter Output (dBm)
Transmitter Output (dBm)
D003
CF = 470 pF
图 2. High-Frequency Emissions Spectrum
With 9.6-kbps Signaling Rate
图 1. Low-Frequency Emissions Spectrum
With 9.6-kbps Signaling Rate
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-70
-80
0
10M
20M
Frequency (Hz)
50% Duty Cycle
CF = 470 pF
图 5. Low-Frequency Emissions Spectrum
With 115.2-kbps Signaling Rate
8
330M
30M
-120
30M
130M
D006
50% Duty Cycle
230M
Frequency (Hz)
330M
D007
CF = 470 pF
图 6. High-Frequency Emissions Spectrum
With 115.2-kbps Signaling Rate
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SN65HVD63
www.ti.com.cn
ZHCSE43 – JULY 2015
40
6
35
5
Transmitter Output (dBm)
Transmitter Output Impedance (:)
Typical Characteristics (接
接下页)
30
25
20
15
10
4
3
2
1
0
-1
5
0
0.1M
1M
10M
-2
0.7
100M
Frequency (Hz)
0.9
D008
图 7. Transmitter Output Impedance
1.1
VRES Voltage (V)
1.3
1.5
D009
图 8. Transmit Power Adjustment
27
13
12.9
Quiescent Current (mA)
Quiescent Current (mA)
26.5
26
25.5
25
12.8
12.7
12.6
12.5
12.4
12.3
12.2
24.5
12.1
24
12
3
3.5
4
4.5
Supply Voltage (V)
5
5.5
3
TXIN = VL
5
5.5
D011
图 10. Supply Current vs Supply Voltage
in Standby Mode
13.2
7
13.1
6
Transmitter Output (dBm)
Ouiescent Current (mA)
4
4.5
Supply Voltage (V)
TXIN = VL
图 9. Supply Current vs Supply Voltage
While Transmitting
13
12.9
12.8
12.7
12.6
5
4
3
2
1
12.5
12.4
-40
3.5
D011
0
-25
-10
5
20 35 50 65
Temperature (qC)
80
95
110 125
图 11. Supply Current vs Temperature
in Standby Mode
版权 © 2015, Texas Instruments Incorporated
D012
3
3.5
4
4.5
Supply Voltage (V)
5
5.5
D013
图 12. Transmitter Output Power
vs Supply Voltage
9
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ZHCSE43 – JULY 2015
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7
30000
6
25000
Receiver Input Impedance (:)
Transmitter Output (dBm)
Typical Characteristics (接
接下页)
5
4
3
2
1
0
-40
-25
-10
5
20 35 50 65
Temperature (qC)
80
95
20000
15000
10000
5000
0
100
110 125
图 13. Transmitter Output Power vs Temperature
10k
100k
Frequency (Hz)
1M
5M
D015
图 14. Receiver Input Impedance vs Frequency
360
0.18
DIR Receiver Output Delay (nS)
RTXOUT = Stable Low
RTXOUT = Stable High
0.17
Receiver Input Threshold (V)
1k
D014
0.16
0.15
0.14
0.13
0.12
0.11
0.1
355
350
345
0.09
0.08
-40
-25
-10
5
20 35 50 65
Temperature (qC)
80
95
340
-40
110 125
图 15. Receiver Input Threshold vs Temperature
5
20 35 50 65
Temperature (qC)
80
95
110 125
D017
图 16. DIR Output Delay vs Temperature
Receiver Output Dutycycle (%)
Receiver Output Dutycycle (%)
56
52
48
44
-7
-4
-1
Receiver Input (dBm)
2
图 17. Receiver Duty Cycle
With 9.6 kbps Signaling Rate
10
-10
60
60
40
-10
-25
D016
5
D018
50
40
30
20
10
0
-10
-7
-4
-1
Receiver Input (dBm)
2
5
D019
图 18. Receiver Duty Cycle
With 115.2 kbps Signaling Rate
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SN65HVD63
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ZHCSE43 – JULY 2015
8 Parameter Measurement Information
Signal generator rate is 115 kbps, 50% duty cycle. Rise and fall times are less than 6 ns, and nominal output
levels are 0 V and 3 V. Coupling capacitor, CC, is 220 nF.
Driver Amplitude Adjust
RAMP
TXOUT
RES
50 Ω
XTAL2
TXOUT
2.176–MH_
z
Crystal
2.176–MH_
z
Generator
XTAL2
Coax In
TXIN
Received
Data Out
Cc
50 Ω
RXIN
Signal
Generator
Coax Out
Direction
Control
Cc
50 Ω
RXIN
VPP
0.5 V L
VL
RXIN
0.5 V L
TXIN
t pQA
t pAQ
VL
0.5 V L
RXOUT
t PHL
t PLH
VPP
VL
0.5 VPP
TXOUT
0.5 V L
DIR
t DIRSKEW
图 19. Measurement of Modem Driver
Output Voltage With 50-Ω Loads
图 20. Measurement of Modem Receiver
Propagation Delays
图 21. AISG Emissions Template
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9 Detailed Description
9.1 Overview
The SN65HVD63 transceiver modulates and demodulates signals between the logic (baseband) and a frequency
suitable for long coaxial media. The SN65HVD63 device is an integrated AISG transceiver designed to meet the
requirements of the upcoming Antenna Interface Standards Group v3.0 specification. The SN65HVD63 receiver
integrates an active bandpass filter to enable demodulation of signals even in the presence of spurious frequency
components. The filter has a 2.176-MHz center frequency. The transmitter supports adjustable output power
levels from 0 dBm to 6 dBm delivered to the 50-Ω coax cable. The SN65HVD63 transmitter is compliant with the
spectrum emission requirement provided by the AISG standard. A direction control output facilitates bus
arbitration for an RS-485 interface. This device integrates an oscillator input for a crystal, and also accepts
standard clock inputs to the oscillator.
9.2 Functional Block Diagram
VL
VCC
3
13
1
9
XTAL1
14
XTAL2
15
SYNCOUT
RES
FILTER
XTAL
Buffer
OOK
MOD
OUTPUT
STAGE
PREAMP
12
TXOUT
2.176–MHz
TXIN
DIRSET1
DIRSET2
DIR
RXOUT
2
7
6
Control
Logic
FILTER
5
OOK
DEMOD
4
Buffer
11
Buffer
RXIN
2.176–MHz
COMP
RECEIVER
THRESHOLD
16
8
10
GND
GND
BIAS
9.3 Feature Description
9.3.1 Coaxial Interface
The SN65HVD63 transceiver enables the transfer of data between radio equipment by modulating baseband
data to a carrier frequency of 2.176 MHz (per the AISG standard). The transmitter output amplitude can be
configured from 0 dBm to 6 dBm in order to communicate over a variety of different links, and the output
emissions spectrum is designed to be compliant to AISG limits. The receiver features an active bandpass filter
circuit that helps to separate the carrier frequency data from other spurious frequency components.
9.3.2 Reference Input
The 2.176-MHz modulation frequency is derived from an input reference that is nominally 8.704 MHz. The input
reference can come either from a crystal or from an oscillator circuit with a tolerance of up to 30 ppm.
9.3.3 RS-485 Direction Control
To facilitate bus arbitration of an RS-485 interface, the SN65HVD63 provides a direction control output that can
be used to control the enable/disable controls of an RS-485 transceiver. The direction control output
automatically toggles based on activity present on the coaxial input interface, and has an adjustable time
constant (controlled by the DIRSET1 and DIRSET2 pins) in order to accommodate various signaling rates.
12
版权 © 2015, Texas Instruments Incorporated
SN65HVD63
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ZHCSE43 – JULY 2015
9.4 Device Functional Modes
If DIRSET1 and DIRSET2 are in a logic high state, the device will be in standby mode. While in standby mode,
the receiver functions normally, detecting carrier frequency activity on the RXIN pin and setting the RXOUT state.
The transmitter circuits are not active in standby mode, thus the TXOUT pin is idle regardless of the logic state of
TXIN. The supply current in standby mode is significantly reduced, allowing power savings when the node is not
transmitting.
When not in standby mode, the default power-on state is idle. When in idle mode, RXOUT is high, and TXOUT is
quiet. The device transitions to receive mode when a valid modulated signal is detected on the RXIN line or the
device transitions to transmit mode when TXIN goes low. The device stays in either receive or transmit mode
until DIR time-out (nominal 16 bit times) after the last activity on RXOUT or TXIN.
When in receive mode:
• RXOUT responds to all valid modulated signals on RXIN, whether from the local transmitter, a remote
transmitter, or long noise burst.
• TXOUT responds to TXIN, generating 2.176-MHz signals on TXOUT when TXIN is low, and TXOUT is quiet
when TXIN is high. (In normal operation, TXIN is expected to remain high when the device is in receive
mode.)
• The device stays in receive mode until 16 bit times after the last rising edge on RXOUT, caused by valid
modulated signal on the RXIN line.
When in transmit mode:
• RXOUT stays high, regardless of the input signal on RXIN.
• TXOUT responds to TXIN, generating 2.176-MHz signals on TXOUT when TXIN is low, and TXOUT is quiet
when TXIN is high.
• The device stays in transmit mode until 16 bit times after TXIN goes high.
表 1 shows the driver functions. 表 2 shows the receiver functions. 图 22 shows the transitions between each
state.
表 1. Driver Function Table
TXIN (1)
[DIRSET1, DIRSET2]
H
[L,L], [L,H] or [H,L]
L
X
(1)
TXOUT
< 1 mVPP at 2.176 MHz
VOPP at 2.176 MHz
[H,H]
< 1 mVPP at 2.176 MHz
COMMENT
Driver not active
Driver active
Standby mode
H = High, L = Low, X = Indeterminate
表 2. Receiver and DIR Function Table
RXIN
(1)
COMMENT (see 图 22)
RXOUT
DIR
H
L
No outgoing or incoming signal
< VIT at 2.176 MHz for less than tDIR time-out
H
H
Incoming 1 bit, DIR stays HIGH for DIR time-out
> VIT at 2.176 MHz for longer than tnoise filter
L
H
Incoming 0 bit, DIR output is HIGH
H
L
Outgoing message, DIR stays LOW for DIR time-out
IDLE mode (not transmitting or receiving)
< VIT at 2.176 MHz for longer than DIR time-out
RECEIVE mode (not already transmitting)
TRANSMIT mode (not already receiving)
X
(1)
H = High, L = Low, X = Indeterminate
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13
SN65HVD63
ZHCSE43 – JULY 2015
www.ti.com.cn
Transmit 0
TXOUT=Active
DIR = L
RXIN 9
Receive 0
RXOUT = L
DIR = H
TXIN ;
IDLE
TXIN 9
TXIN ;
RXOUT = H
TXOUT=Idle
DIR = L
Transmit 1
TXOUT=Idle
DIR = L
RXIN 9
RXIN ;
Receive 1
DIR Timeout
DIR Timeout
RXOUT = H
DIR = H
图 22. State Transition Diagram
14
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SN65HVD63
www.ti.com.cn
ZHCSE43 – JULY 2015
10 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
10.1.1 Driver Amplitude Adjust
The SN65HVD63 device can provide up to 2.5 V of peak-to-peak output signal at the TXOUT pin to compensate
for potential loss within the external filter, cable, connections, and termination. External resistors are used to set
the amplitude of the modulated driver output signal. Resistors connected across RES and BIAS set the output
amplitude. The maximum peak-to-peak voltage at TXOUT is 2.5 V, corresponding to 6 dBm on the coaxial cable.
The TXOUT voltage level can be adjusted by choice of resistors to set the voltage at the RES pin. according to
the following equation:
VTXOUT (VPP) = (2.5 VPP × VRES (V)) / 1.5 V VRES (V) = 1.5 V × R2 / (R1 + R2) VTXOUT (VPP) = 2.5 VPP × R2 / (R1 + R2)
(1)
The voltage at the RES pin should be from 0.7 V to 1.5 V. Connect RES directly to the BIAS (R1 = 0 Ω) for
maximum output level of 2.5 VPP. This gives a minimum voltage level at TXOUT of 1.2 VPP, corresponding to
about 0 dBm at the coaxial cable. A 1-μF capacitor should be connected between the BIAS pin and GND. To
obtain a nominal power level of 3 dBm at the feeder cable as the AISG standard requires, use R1 = 4.1 kΩ and
R2 = 10 kΩ that provide 1.78 VPP at TXOUT.
10.1.2 Direction Control
In many applications the mast-top modem that receives data from the base distributes the received data through
an RS-485 network to several mast-top devices. When the mast-top modem receives the first logic 0 bit (active
modulated signal) it takes control of the mast-top RS-485 network by asserting the direction control signal. The
duration of the direction control assertion should be optimized to pass a complete message of length B bits at the
known signaling rate (1/tBIT) before relinquishing control of the mast-top RS-485 network. For example, if the
messages are 10 bits in length (B=10) and the signaling rate is 9600 bits per second (tBIT = 0.104 ms) then a
positive pulse of duration 1.7 ms is sufficient (with margin to allow for network propagation delays) to enable the
mast-top RS-485 drivers to distribute each received message. 图 23 shows the assertion of direction control.
Coax In
Data Out
Direction
图 23. Assertion of Direction Control
10.1.3 Direction Control Time Constant
The time constant for the direction control function can be set by the control mode pins, DIRSET1 and DIRSET2.
These pins should be set to correspond to the desired data rate. With no external connections to the control
mode pins, the internal time constant is set to the maximum value, corresponding to the minimum data rate.
版权 © 2015, Texas Instruments Incorporated
15
SN65HVD63
ZHCSE43 – JULY 2015
www.ti.com.cn
Application Information (接
接下页)
10.1.4 Conversion Between dBm and Peak-to-Peak Voltage
dBm = 20 × LOG10 [Volts-pp / SQRT(0.008 × Zo)] = 20 × LOG10 [VPP / 0.63] for Zo = 50 Ω
VPP = SQRT(0.008 × Zo) × 10(dBm/20) = 0.63 × 10(dBm/20) for Zo = 50 Ω
(2)
(3)
表 3 shows conversions between dBm and peak-to-peak voltage with a 50-Ω load, for various levels of interest
including reference levels from the 3GPP TS 25.461 Technical Specification.
表 3. Conversions Between dBM and Peak-to-Peak Voltage
SIGNAL ON COAX
dBm
VPP
Maximum Driver ON Signal
5
1.12
Nominal Driver ON Signal
3
0.89
Minimum Driver ON Signal
1
0.71
AISG Maximum Receiver Threshold
–12
0.16
Nominal Receiver Threshold
–15
0.11
Minimum Receiver Threshold
–18
0.08
Maximum Driver OFF Signal
–40
0.006
10.2 Typical Application
The AISG On-Off Keying (OOK) interface allows for command, control, and diagnostic information to be
communicated between a base station and the corresponding tower-mounted antennae. 图 24 shows a typical
application.
RF+
Modulated Signals +
Power (On Coax)
RF
Signals
RS-485
Signals
(Twisted Pair)
Power
Diagnostics
and Control
图 24. Typical AISG Application
10.2.1 Design Requirements
An AISG transceiver is used to convert between digital logic-level signals and RF signals. The AISG standard
requires an RF carrier frequency of 2.176 MHz with 100-ppm accuracy. The output signal of the driver, when
active, should be from 1 dBm to 5 dBm. The receiver must be designed such that the input threshold is from –18
dBm to –12 dBm.
10.2.2 Detailed Design Procedure
To ensure accuracy of the carrier frequency, an input reference frequency equal to four times the carrier (that is,
8.704 MHz) should be connected to the XTAL1 or XTAL2 inputs. This signal can come from a crystal (connected
between XTAL1 and XTAL2) or from a PLL/clock generator circuit (connected to XTAL1 with XTAL2 grounded).
The frequency accuracy must be within 100 ppm.
16
版权 © 2015, Texas Instruments Incorporated
SN65HVD63
www.ti.com.cn
ZHCSE43 – JULY 2015
Typical Application (接
接下页)
The driver output power level of the SN65HVD63 device can be adjusted through use of the RES pin. To align
with AISG requirements, a nominal power level of 3 dBm should be configured by connecting a 4.1-kΩ resistor
between RES and BIAS and a 10-kΩ resistor between RES and GND. 图 25 shows an example schematic.
39 pF 8.704 MHz 39 pF
VCC
SYNCOUT
VCC
49.9
BIAS
470 pF
RES
GND
DIRSET1
VL
DIRSET2
RXIN
DIR
220 nF
TXOUT
TXIN
RXOUT
0.1 F
XTAL1
GND
VL
XTAL2
0.1 F
4.1 N
10 N
图 25. SN65HVD63 Schematic
10.2.3 Application Curve
图 26 shows the application curve for the SN65HVD63 device.
图 26. SN65HVD63 Application Curve
版权 © 2015, Texas Instruments Incorporated
17
SN65HVD63
ZHCSE43 – JULY 2015
www.ti.com.cn
11 Power Supply Recommendations
The SN65HVD63 device has two power supply pins: VCC, which provides power to the analog circuitry, and VL,
which is a logic supply. VCC should be operated from 3 V to 5.5 V, while VL can range from 1.6 V to 5.5 V to
interface to different logic levels. Power supply decoupling capacitances of at least 0.1 µF should be placed as
close as possible to each power supply pin.
12 Layout
12.1 Layout Guidelines
Best practices for high-speed PCB design should be observed because the coax interface to the SN65HVD63
device operates at RF. The RF signaling traces should have a controlled characteristic impedance that is wellmatched to the coaxial line. A continuous reference plane should be used to avoid impedance discontinuities.
Power and ground distribution should be done through planes rather than traces to decrease series resistance
and increase the effective decoupling capacitance on the power rails.
12.2 Layout Example
图 27. SN65HVD63 Layout
18
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SN65HVD63
www.ti.com.cn
ZHCSE43 – JULY 2015
13 器件和文档支持
13.1 相关文档
《天线线路器件的控制接口》，天线接口标准标准组织，标准编号 AISG v2.0
13.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.3 商标
E2E is a trademark of Texas Instruments.
AISG is a registered trademark of Antenna Interface Standards Group, Ltd.
All other trademarks are the property of their respective owners.
13.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
13.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不
对本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2015, Texas Instruments Incorporated
19
PACKAGE OPTION ADDENDUM
www.ti.com
4-Dec-2025
PACKAGING INFORMATION
Orderable part number
(1)
Status
Material type
(1)
(2)
Package | Pins
Package qty | Carrier
RoHS
(3)
Lead finish/
Ball material
MSL rating/
Peak reflow
(4)
(5)
Op temp (°C)
Part marking
(6)
SN65HVD63RGTR
Active
Production
VQFN (RGT) | 16
3000 | LARGE T&R
Yes
FULL NIPDAU
Level-2-260C-1 YEAR
-40 to 105
HVD63
SN65HVD63RGTR.A
Active
Production
VQFN (RGT) | 16
3000 | LARGE T&R
Yes
FULL NIPDAU
Level-2-260C-1 YEAR
-40 to 105
HVD63
SN65HVD63RGTRG4
Active
Production
VQFN (RGT) | 16
3000 | LARGE T&R
Yes
FULL NIPDAU
Level-2-260C-1 YEAR
-40 to 105
HVD63
SN65HVD63RGTRG4.A
Active
Production
VQFN (RGT) | 16
3000 | LARGE T&R
Yes
FULL NIPDAU
Level-2-260C-1 YEAR
-40 to 105
HVD63
SN65HVD63RGTT
Active
Production
VQFN (RGT) | 16
250 | SMALL T&R
Yes
FULL NIPDAU
Level-2-260C-1 YEAR
-40 to 105
HVD63
SN65HVD63RGTT.A
Active
Production
VQFN (RGT) | 16
250 | SMALL T&R
Yes
FULL NIPDAU
Level-2-260C-1 YEAR
-40 to 105
HVD63
Status: For more details on status, see our product life cycle.
(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance,
reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional
waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.
(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.
(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum
column width.
(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown.
Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.
(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.
Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two
combined represent the entire part marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and
makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers
and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-Dec-2025
Addendum-Page 2
PACKAGE OUTLINE
RGT0016A
VQFN - 1 mm max height
SCALE 3.600
PLASTIC QUAD FLATPACK - NO LEAD
3.1
2.9
A
B
PIN 1 INDEX AREA
3.1
2.9
C
1 MAX
SEATING PLANE
0.05
0.00
0.08
1.45 0.1
(0.2) TYP
5
12X 0.5
8
EXPOSED
THERMAL PAD
4
9
4X
1.5
SYMM
17
1
12
16X
PIN 1 ID
(OPTIONAL)
13
16
0.1
0.05
SYMM
16X
0.30
0.18
C A B
0.5
0.3
4219032/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
4. Reference JEDEC registration MO-220
www.ti.com
EXAMPLE BOARD LAYOUT
RGT0016A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 1.45)
SYMM
16
13
16X (0.6)
1
12
16X (0.24)
SYMM
17
(0.475)
TYP
(2.8)
12X (0.5)
9
4
( 0.2) TYP
VIA
5
(R0.05)
ALL PAD CORNERS
8
(0.475) TYP
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4219032/A 02/2017
NOTES: (continued)
5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
6. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGT0016A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 1.34)
13
16
16X (0.6)
1
12
16X (0.24)
17
SYMM
(2.8)
12X (0.5)
9
4
METAL
ALL AROUND
5
SYMM
8
(R0.05) TYP
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17:
86% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4219032/A 02/2017
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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