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SN65HVD888
SLLSEH3C – JULY 2013 – REVISED JANUARY 2018
SN65HVD888 Bus-Polarity Correcting RS-485 Transceiver With IEC-ESD Protection
1 Features
3 Description
•
•
•
•
The SN65HVD888 is a low-power RS-485 transceiver
with automatic bus-polarity correction and transient
protection. Upon hot plug-in, the device detects and
corrects the bus polarity within the first 76 ms of bus
idling. On-chip transient protection protects the device
against IEC61000 ESD and EFT transients. This
device has robust drivers and receivers for
demanding industrial applications. The bus pins are
robust to electrostatic discharge (ESD) events, with
high levels of protection to Human-Body Model
(HBM), Air-Gap Discharge, and Contact Discharge
specifications.
1
•
•
•
Exceeds Requirements of EIA-485 Standard
Bus-Polarity Correction Within 76 ms (tFS)
Data Rate: 300 bps to 250 kbps
Works With Two Configurations:
– Failsafe Resistors Only
– Failsafe and Differential Termination Resistors
Up to 256 Nodes on a Bus (1/8 Unit Load)
SOIC-8 Package for Backward Compatibility
Bus-Pin Protection:
– ±16 kV HBM protection
– ±12 kV IEC61000-4-2 Contact Discharge
– +4 kV IEC61000-4-4 Fast Transient Burst
2 Applications
•
•
•
•
•
•
•
•
E-Metering Networks
Industrial Automation
HVAC Systems
DMX512-Networks
Process Control
Battery-Powered Applications
Motion Control
Telecom Equipment
The device combines a differential driver and a
differential receiver, which operate together from a
single 5-V power supply. The driver differential
outputs and the receiver differential inputs are
connected internally to form a bus port suitable for
half-duplex (two-wire bus) communication. The
device features a wide common-mode voltage range
making the device suitable for multi-point applications
over long cable runs. The SN65HVD888 is available
in an SOIC-8 package, and is characterized from
–40°C to 125°C.
Device Information(1)
PART NUMBER
SN65HVD888
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Typical Network Application With Polarity Correction (POLCOR)
Cross-wire
fault 0
5V
R
R
DE
D
D
A
B
B
1k
A
B
A
POLCOR
RE
R
R
1k
A
D
B
Master
SN65HVD82
RE
DE
D
Slave
SN65HVD888
R
R
D
D
POLCOR
R
RE DE
POLCOR
D
Slave
SN65HVD888
R
RE DE
D
Slave
SN65HVD888
Copyright © 2018, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN65HVD888
SLLSEH3C – JULY 2013 – REVISED JANUARY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
3
3
4
4
4
5
6
6
7
Absolute Maximum Ratings ......................................
ESD Ratings: JEDEC Specifications ........................
ESD Ratings: IEC Specifications ..............................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Power Dissipation Characteristics ...........................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Parameter Measurement information .................. 8
7.1 Driver......................................................................... 8
7.2 Receiver .................................................................... 9
8
Detailed Description ............................................ 10
8.1
8.2
8.3
8.4
9
Overview ................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
10
10
10
12
Application and Implementation ........................ 14
9.1 Application Information............................................ 14
9.2 Typical Application ................................................. 20
10 Power Supply Recommendations ..................... 21
11 Layout................................................................... 22
11.1 Layout Guidelines ................................................. 22
11.2 Layout Example ................................................... 22
12 Device and Documentation Support ................. 23
12.1
12.2
12.3
12.4
12.5
12.6
Device Support......................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
23
23
23
23
23
23
13 Mechanical, Packaging, and Orderable
Information ........................................................... 23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (June 2017) to Revision C
•
Page
Changed 3.3 VISO To: 5 VISO in Figure 24 ........................................................................................................................... 20
Changes from Revision A (September 2015) to Revision B
Page
•
Changed text From: "characterized from –40°C to 85°C" To: "characterized from –40°C to 125°C" in the Description ....... 1
•
Changed the TA MAX value From: 85°C To: 125°C in the Recommended Operating Conditions table ............................... 4
•
Changed ICC to show values for the temperature ranges of –40°C to 85°C and –40°C to 125°C in the Electrical
Characteristics table ............................................................................................................................................................... 5
Changes from Original (July 2013) to Revision A
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
•
Changed JEDEC Standard 22, Test Method A114 (HBM) from ±4 to ±8 kV......................................................................... 3
•
Changed JEDEC Standard 22, Test Method A115 (Machine Model) from ±100 to ±200 V. ................................................. 3
•
Changed the "D and RE Inputs" circuit and the "DE Input" circuit of Figure 15................................................................... 13
2
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SLLSEH3C – JULY 2013 – REVISED JANUARY 2018
5 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
R
RE
DE
D
1
2
3
4
8
7
6
5
Vcc
B
A
GND
Pin Functions
PIN
NAME
I/O
NO.
DESCRIPTION
A
6
Bus
input/output
Driver output or receiver input (complementary to B)
B
7
Bus
input/output
Driver output or receiver input (complementary to A)
D
4
Digital input
Driver data input
DE
3
Digital input
Driver enable, active high
GND
5
Reference
potential
R
1
RE
2
Digital input
VCC
8
Supply
Local device ground
Digital output Receive data output
Receiver enable, active low
4.5-V to 5.5-V supply
6 Specifications
6.1 Absolute Maximum Ratings
(1)
(see
)
MIN
VCC
UNIT
Supply voltage
–0.5
7
V
Input voltage at any logic pin
–0.3
5.7
V
Voltage input, transient pulse, A and B, through 100 Ω
–100
100
V
Voltage at A or B inputs
–18
18
V
Receiver output current
–24
24
mA
Continuous total-power dissipation
TJ
Junction temperature
TSTG
Storage temperature
(1)
MAX
See (Thermal Information)
table
–65
170
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings: JEDEC Specifications
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±8000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1500
Machine model (MM)
±100
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 ESD Ratings: IEC Specifications
VALUE
IEC 61000-4-2 ESD (Contact Discharge), bus terminals and GND
V(ESD)
Electrostatic discharge
UNIT
±12000
IEC 61000-4-4 EFT (Fast transient or burst) bus terminals and GND
±4000
IEC 60749-26 ESD (HBM), bus terminals and GND
±16000
V
6.4 Recommended Operating Conditions
MIN
NOM
MAX
5
UNIT
VCC
Supply voltage
4.5
5.5
V
VID
Differential input voltage
–12
12
V
VI
Input voltage at any bus terminal (separate or common mode) (1)
–7
12
V
VIH
High-level input voltage (driver, driver-enable, and receiver-enable inputs)
2
VCC
V
VIL
Low-level input voltage (driver, driver-enable, and receiver-enable inputs)
0
0.8
V
–60
60
–8
8
Driver
IO
Output current
CL
Differential load capacitance
50
RL
Differential load resistance
60
1/tUI
Signaling rate
0.3
250
kbps
TJ
Junction temperature
–40
150
°C
TA (2)
Operating free-air temperature (see Thermal Information for additional information)
–40
125
°C
(1)
(2)
Receiver
mA
pF
Ω
The algebraic convention in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
Operation is specified for internal (junction) temperatures up to 150°C. Self-heating due to internal power dissipation should be
considered for each application. Maximum junction temperature is internally limited by the thermal shut-down (TSD) circuit which
disables the driver outputs when the junction temperature reaches 170°C.
6.5 Thermal Information
SN65HVD888
THERMAL METRIC (1)
D (SOIC)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
116.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
60.8
°C/W
RθJB
Junction-to-board thermal resistance
57.1
°C/W
ψJT
Junction-to-top characterization parameter
13.9
°C/W
ψJB
Junction-to-board characterization parameter
56.5
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.6 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
│VOD│
Driver differential-output voltage
magnitude
TEST CONDITIONS
RL = 60 Ω, 375 Ω on each output
from –7 to +12 V
RL = 54 Ω (RS-485)
RL = 100 Ω (RS-422)
See Figure 4
See Figure 5
MIN
TYP
1.5
2.5
1.5
2.5
2
3
MAX
UNIT
V
Δ│VOD│
Change in magnitude of driver
differential-output voltage
RL = 54 Ω, CL = 50 pF
See Figure 5
–0.2
0
0.2
V
VOC(SS)
Steady-state common-mode
output voltage
Center of two 27-Ω load resistors
See Figure 5
1
VCC / 2
3
V
ΔVOC
Change in differential driver
common-mode output voltage
Center of two 27-Ω load resistors
See Figure 5
–0.2
0
0.2
VOC(PP)
Peak-to-peak driver commonmode output voltage
Center of two 27-Ω load resistors
See Figure 5
COD
Differential output capacitance
VIT+
Positive-going receiver
differential-input voltage threshold
VIT–
Negative-going receiver
differential-input voltage threshold
VHYS (1)
Receiver differential-input voltage
threshold hysteresis (VIT+ – VIT– )
VOH
Receiver high-level output voltage
IOH = –8 mA
VOL
Receiver low-level output voltage
IOL = 8 mA
II
Driver input, driver enable, and
receiver enable input current
IOZ
Receiver high-impedance output
current
VO = 0 V or VCC, RE at VCC
│IOS│
Driver short-circuit output current
│IOS│ with VA or VB from –7 to +12 V
II
ICC
ICC
Bus input current (driver disabled)
Supply current (quiescent)
–40°C to 85°C
Supply current (quiescent)
–40°C to 125°C
Supply current (dynamic)
(1)
mV
850
mV
8
pF
35
–100
–35
40
60
2.4
VCC – 0.3
0.2
100
mV
mV
mV
V
0.4
V
–2
2
µA
–10
10
µA
150
mA
VCC = 4.5 to 5.5 V or
VI = 12 V
75
VCC = 0 V, DE at 0 V
VI = –7 V
Driver and receiver enabled
DE = VCC,
RE = GND,
No load
Driver enabled, receiver disabled
DE = VCC,
RE = VCC,
No load
650
Driver disabled, receiver enabled
DE = GND,
RE = GND,
No load
750
Driver and receiver disabled
DE = GND,
D = GND
RE = VCC,
No load
0.4
5
Driver and receiver enabled
DE = VCC,
RE = GND,
No load
750
990
Driver enabled, receiver disabled
DE = VCC,
RE = VCC,
No load
715
Driver disabled, receiver enabled
DE = GND,
RE = GND,
No load
825
–100
125
–40
750
µA
900
µA
µA
See Figure 3
Under any specific conditions, VIT+ is specified to be at least VHYS higher than VIT–.
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6.7 Power Dissipation Characteristics
PARAMETER
Power Dissipation
driver and receiver enabled,
VCC = 5.5 V, TJ = 150°C
50% duty cycle square-wave
signal at 250 kbps signaling
rate:
PD
TEST CONDITIONS
VALUE
Unterminated
RL = 300 Ω,
CL = 50 pF (driver)
164
RS-422 load
RL = 100 Ω,
CL = 50 pF (driver)
247
RS-485 load
RL = 54 Ω,
CL = 50 pF (driver)
316
UNIT
mW
6.8 Switching Characteristics
3.3 ms > bit time > 4 μs (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DRIVER
tr, tf
Driver differential-output rise and fall times RL = 54 Ω, CL = 50 pF
See Figure 6
400
700
1200
ns
tPHL, tPLH
Driver propagation delay
RL = 54 Ω, CL = 50 pF
See Figure 6
90
700
1000
ns
tSK(P)
Driver pulse skew, |tPHL – tPLH|
RL = 54 Ω, CL = 50 pF
See Figure 6
25
200
ns
See Figure 7 and
Figure 8
50
500
ns
Receiver enabled
See Figure 7 and
Figure 8
500
1000
ns
Receiver disabled
See Figure 7 and
Figure 8
3
9
µs
tPHZ, tPLZ
Driver disable time
tPHZ, tPLZ
Driver enable time
RECEIVER
tr, tf
Receiver output rise and fall times
CL = 15 pF
See Figure 9
18
30
ns
tPHL, tPLH
Receiver propagation delay time
CL = 15 pF
See Figure 9
85
195
ns
tSK(P)
Receiver pulse skew, |tPHL – tPLH|
CL = 15 pF
See Figure 9
1
15
ns
tPHZ, tPLZ
Receiver disable time
50
500
tPZL(1),
tPZH(1)
tPZL(2),
tPZH(2)
Receiver enable time
tFS
Bus failsafe time
6
Driver enabled
See Figure 10
20
130
ns
Driver disabled
See Figure 11
2
8
µs
Driver disabled
See Figure 12
58
76
ms
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6.9 Typical Characteristics
10
10
Driver Output Voltage (V)
6
Driver Differential Output Voltage (V)
VCC = 5 V
D = DE = 5 V
8
VOH
4
VOL
2
0
±2
±4
±6
±8
VCC = 5 V
D = DE = 5 V
9
8
7
6
5
4
3
2
1
0
±10
0
10
20
30
40
50
60
70
80
90
Driver Output Current (mA)
0
100
10
20
30
40
50
60
70
80
90
Driver Output Current (mA)
C001
Figure 1. Driver Output Voltage vs Driver Output Current
100
C002
Figure 2. Driver Differential Output Voltage vs Driver Output
Current
25
VCC = 5 V
D = DE = /RE = 5 V
Supply Current (mA)
20
15
10
5
0
0
50
100
150
200
Signal Rate (kbps)
250
C003
Figure 3. Supply Current vs Signaling Rate
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7 Parameter Measurement information
7.1 Driver
375 Ÿ
Vcc
DE
A
D
0V or 5 V
VOD
-7V < Vtest < 12 V
60 Ÿ
B
375 Ÿ
Figure 4. Measurement of Driver Differential-Output Voltage With Common-Mode Load
A
0V or 5 V
RL/2
A
D
VA
B
VB
VOD
RL/2
B
VOC(PP)
CL VOC
ûVOC(SS)
VOC
Figure 5. Measurement of Driver Differential and Common-Mode Output With RS-485 Load
5V
Vcc
DE
A
D
Input
Generator
VI
54 Ÿ
VOD
50Ÿ
50%
VI
B
CL=
50 pF
0V
tPLH
tPHL
90%
50%
10%
VOD
tr
§ 2V
§ -2V
tf
Figure 6. Measurement of Driver Differential-Output Rise and Fall Times and Propagation Delays
A
D
VI
50%
VI
B
DE
Input
Generator
5V
VO
S1
RL=
110 Ÿ
CL=
50 pF
50Ÿ
0V
tPZH
90%
VO
VOH
50%
§ 0V
tPHZ
Figure 7. Measurement of Driver Enable and Disable Times With Active-High Output and Pull-Down Load
5V
5V
D
DE
Input
Generator
VI
A
RL= 110 Ÿ
S1
B
50Ÿ
CL=
50 pF
VO
50%
VI
0V
tPZL
VO
tPLZ
§ 5V
50%
10%
VOL
Figure 8. Measurement of Driver Enable and Disable Times With Active-Low Output and Pull-up Load
8
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7.2 Receiver
5V
A
Input
Generator
VI
50Ÿ 1.5V
0V
50%
VI
R VO
0V
tPLH
B
tPHL
90%
50%
10%
CL= 15 pF
RE
VOD
tr
VOH
VOL
tf
Figure 9. Measurement of Receiver Output Rise and Fall Times and Propagation Delays
Vcc
Vcc
DE
0V or 5 V
B
Input
Generator
50%
0V
A
D
5V
VI
R VO
S1
VO
CL= 15 pF
RE
tPHZ
tPZH(1)
1 kŸ
§ 0V
tPZL(1)
50Ÿ
VI
D at 5V
S1 to GND
VOH
90%
50%
tPLZ
VO
50%
D at 0V
S1 to VCC
VCC
10%
VOL
Figure 10. Measurement of Receiver Enable and Disable Times With Driver Enabled
5V
Vcc
1.5 V or 0 V
Input
Generator
B
50%
0V
A
0V or 1.5 V
VI
R VO
RE
tPZH(2)
1 kŸ
VOH
S1
VO
CL= 15 pF
A at 1.5V
B at 0V
S1 to GND
50%
§ 0V
tPZL(2)
VCC
50Ÿ
VI
VO
A at 0V
B at 1.5V
S1 to VCC
50%
VOL
Figure 11. Measurement of Receiver Enable Times With Driver Disabled
VI
A
Input
Generator
VI
50Ÿ 1.5V
B
RE
0V
(DE = Low)
R
50%
0V
VO
tPHL
tFS
10 kŸ
VCC
VO
50%
Figure 12. Measurement of Receiver Polarity-Correction Time With Driver Disabled
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8 Detailed Description
8.1 Overview
The SN65HVD888 device is a half-duplex RS-485 transceiver suitable for data transmission at rates up to 250
kbps over controlled-impedance transmission media (such as twisted-pair cabling). The device features a high
level of internal transient protection, making it able to withstand up ESD strikes up to 12 kV (per IEC 61000-4-2)
and EFT transients up to 4 kV (per IEC 61000-4-4) without incurring damage. Up to 256 units of SN65HVD82
may share a common RS-485 bus due to the device’s low bus input currents. The device features automatic
polarity correction, which detects bus mis-wirings at start-up and then swaps the A and B halves of the bus if
needed.
8.2 Functional Block Diagram
R
DE
D
POLCOR
RE
Vcc
B
A
GND
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8.3 Feature Description
8.3.1 Low-Power Standby Mode
When the driver and the receiver are both disabled (DE = Low and RE = High) the device enters standby mode.
If the enable inputs are in the disabled state for only a brief time (for example: less than 100 ns), the device does
not enter standby mode, preventing the SN65HVD888 from entering standby mode during driver or receiver
enabling. Only when the enable inputs are held in the disabled state for a duration of 300 ns or more does the
device enter low-power standby mode. In this mode most internal circuitry is powered down, and the steady-state
supply current is typically less than 400 nA. When either the driver or the receiver is re-enabled, the internal
circuitry becomes active. During VCC power-up, when the device is set for both driver and receiver disabled
mode, the device may consume more than 5-µA of ICC disabled current because of capacitance charging effects.
This condition occurs only during VCC power up.
8.3.2 Bus Polarity Correction
The SN65HVD888 automatically corrects a wrong bus-signal polarity caused by a cross-wire fault. In order to
detect the bus polarity, all three of the following conditions must be met:
• A failsafe-biasing network (commonly at the master node) must define the signal polarity of the bus
• A slave node must enable the receiver and disable the driver (RE = DE = Low)
• The bus must idle for the failsafe time, tFS-max
After the failsafe time has passed, the polarity correction is complete and is applied to both the receive and
transmit channels. The status of the bus polarity is latched within the transceiver and is maintained for
subsequent data transmissions.
NOTE
Data string durations of consecutive 0s or 1s exceeding tFS-min can accidently trigger a
wrong polarity correction and must be avoided.
Figure 13 shows a simple point-to-point data link between a master node and a slave node. Because the master
node with the failsafe biasing network determines the signal polarity on the bus, an RS-485 transceiver without
polarity correction, such as SN65HVD82, suffices. All other bus nodes, typically performing as slaves, require the
SN65HVD888 transceiver with polarity correction.
10
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Feature Description (continued)
VS-Master
Master
node
Vdd
VS-Master
VS-Slave
VSM
Vcc
RxD
DIR
TxD
RFS
DE
A
B
D
RT
RT
(opt.)
(opt.)
B
RxD
MCU
RE
DE
D
RFS
GND
DGND
Vdd
R
A
RE
VS-Slave
Vcc
POLCOR
MCU
R
Slave
node
GND
DIR
TxD
DGND
Figure 13. Point-To-Point Data Link With Cross-Wire Fault
Prior to initiating data transmission the master transceiver must idle for a time span that exceeds the maximum
failsafe time, tFS-max, of a slave transceiver. This idle time is accomplished by driving the direction control line,
DIR, low. After a time, t > tFS-max, the master begins transmitting data.
Because of the indicated cross-wire fault between master and slave, the slave node receives bus signals with
reversed polarity. Assuming the slave node has just been connected to the bus, the direction-control pin is
pulled-down during power-up and then is actively driven low by the slave MCU. The polarity correction begins as
soon as the slave supply is established and ends after approximately 44 to 76 ms.
DIRm
Master
signals
Low due to pull-down
or actively driven
high Z
Dm
VAm
VFS
0V
-Vod
+Vod
+Vid
-Vid
VBm
VBs
VFS
0V
VAs
VSs
Slave
signals
Low due to pull-down and then actively driven
DIRs
Rs
tFS
Uncorrected R output:
R is in phase with
wrong VID polarity
Corrected R output:
R is reversed to
wrong VID polarity
Figure 14. Polarity Correction Timing Prior to a Data Transmission
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Feature Description (continued)
Initially the slave receiver assumes that the correct bus polarity is applied to the inputs and performs no polarity
reversal. Because of the reversed polarity of the bus-failsafe voltage, the output of the slave receiver, RS, turns
low. After tFS has passed and the receiver has detected the wrong bus polarity, the internal POLCOR logic
reverses the input signal and RS turns high.
At this point all incoming bus data with reversed polarity are polarity corrected within the transceiver. Because
polarity correction is also applied to the transmit path, the data sent by the slave MCU are reversed by the
POLCOR logic and then fed into the driver.
The reversed data from the slave MCU are reversed again by the cross-wire fault in the bus, and the correct bus
polarity is reestablished at the master end.
This process repeats each time the device powers up and detects an incorrect bus polarity.
8.4 Device Functional Modes
Table 1. Driver Pin Functions
INPUT
ENABLE
D
DE
A
OUTPUTS
H
H
H
L
Actively drives bus High
L
H
L
H
Actively drives bus Low
X
L
Z
Z
Driver disabled
X
OPEN
Z
Z
Driver disabled by default
OPEN
H
H
L
Actively drives bus High
DESCRIPTION
B
NORMAL MODE
POLARITY-CORRECTING MODE (1)
(1)
H
H
L
H
Actively drives bus Low
L
H
H
L
Actively drives bus High
X
L
Z
Z
Driver disabled
X
OPEN
Z
Z
Driver disabled by default
OPEN
H
L
H
Actively drives bus Low
The polarity-correcting mode is entered when VID < VIT– and t > tFS and DE = low. This state is latched when RE turns from Low to High.
Table 2. Receiver Pin Functions
DIFFERENTIAL INPUT
ENABLE
OUTPUT
VID = VA – VB
RE
R
DESCRIPTION
NORMAL MODE
VIT+ < VID
L
H
Receive valid bus High
VIT– < VID < VIT+
L
?
Indeterminate bus state
VID < VIT–
L
L
Receive valid bus Low
X
H
Z
Receiver disabled
X
OPEN
Z
Receiver disabled
Open, short, idle Bus
L
?
Indeterminate bus state
POLARITY-CORRECTING MODE (1)
(1)
12
VIT+ < VID
L
L
Receive valid bus Low
VIT– < VID < VIT+
L
?
Indeterminate bus state
VID < VIT–
L
H
Receive polarity corrected bus High
X
H
Z
Receiver disabled
X
OPEN
Z
Receiver disabled
Open, short, idle Bus
L
?
Indeterminate bus state
The polarity-correcting mode is entered when VID < VIT– and t > tFS and DE = low. This state is latched when RE turns from Low to High.
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D and RE Inputs
DE Input
Vcc
Vcc
Vcc
R Output
100k
1k
1k
D,RE
1k
DE
9V
R
9V
100k
9V
Vcc
Receiver Inputs
Driver Outputs
Vcc
16V
16V
R2
R2
R1
A
A
R
R1
B
B
16V
R3
R3
16V
Figure 15. Equivalent Input and Output Schematic Diagrams
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Device Configuration
The SN65HVD888 is a half-duplex RS-485 transceiver operating from a single 5-V ±10% supply. The driver and
receiver enable pins allow for the configuration of different operating modes.
D
D
Vcc
R
B
RE
A
DE
GND
a) Independent driver and
receiver enable signals
D
R
D
R
Vcc
B
RE
A
DE
D
GND
R
POLCOR
DE
POLCOR
RE
R
POLCOR
R
Vcc
B
A
D
GND
c) Receiver always on
b) Combined enable signals for
use as directional control pin
Copyright © 2018, Texas Instruments Incorporated
Figure 16. Transceiver Configurations
Using independent enable lines provides the most flexible control as the lines allow for the driver and the
receiver to be turned on and turned off individually. While this configuration requires two control lines, it allows for
selective listening to the bus traffic, whether the driver is transmitting data or not. Only this configuration allows
the SN65HVD888 to enter low-power standby mode because it allows both the driver and receiver to be disabled
simultaneously.
Combining the enable signals simplifies the interface to the controller by forming a single direction-control signal.
Thus, when the direction-control line is high, the transceiver is configured as a driver, while for a low the device
operates as a receiver.
Tying the receiver enable to ground and controlling only the driver-enable input also uses only one control line. In
this configuration a node not only receives the data on the bus sent by other nodes but also receives the data
sent on the bus, enabling the node to verify the correct data has been transmitted.
9.1.2 Bus Design
An RS-485 bus consists of multiple transceivers connected in parallel to a bus cable. To eliminate line
reflections, each cable end is terminated with a termination resistor, RT, whose value matches the characteristic
impedance, Z0, of the cable. This method, known as parallel termination, allows for relatively high data rates over
long cable length.
Common cables used are unshielded twisted pair (UTP), such as low-cost CAT-5 cable with Z0 = 100 Ω, and
RS-485 cable with Z0 = 120 Ω. Typical cable sizes are AWG 22 and AWG 24.
The maximum bus length is typically given as 4000 ft or 1200 m, and represents the length of an AWG 24 cable
whose cable resistance approaches the value of the termination resistance, thus reducing the bus signal by half
or 6 dB. Actual maximum usable cable length depends on the signaling rate, cable characteristics, and
environmental conditions.
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Application Information (continued)
Table 3. VID with a Failsafe Network and Bus Termination
RL DIFFERENTIAL
TERMINATION
VCC
5V
RFS PULLUP
RFS PULLDOWN
VID
560 Ω
560 Ω
230 mV
54 Ω
1 KΩ
1 KΩ
131 mV
4.7 KΩ
4.7 KΩ
29 mV
10 KΩ
10 KΩ
13 mV
An external failsafe-resistor network must be used to ensure failsafe operation during an idle bus state. When the
bus is not actively driven, the differential receiver inputs could float allowing the receiver output to assume a
random output. A proper failsafe network forces the receiver inputs to exceed the VIT threshold, thus forcing the
SN65HVD888 receiver output into the failsafe (high) state. Table 3 shows the differential input voltage (VID) for
various failsafe networks with a 54-Ω differential bus termination.
9.1.3 Cable Length Versus Data Rate
There is an inverse relationship between data rate and cable length, which means the higher the data rate, the
shorter the cable length; and conversely, the lower the data rate the longer the cable length. While most RS-485
systems use data rates between 10 kbps and 100 kbps, applications such as e-metering often operate at rates of
up to 250 kbps even at distances of 4000 ft and longer. Longer distances are possible by allowing for small
signal jitter of up to 5 or 10%.
10000
CABLE LENGTH - ft
5,10,20 % Jitter
1000
Conservative
Characteristics
100
10
100
1k
10k
100k
1M
10M
100M
DATA RATE - bps
Figure 17. Cable Length vs Data Rate Characteristic
9.1.4 Stub Length
When connecting a node to the bus, the distance between the transceiver inputs and the cable trunk, known as
the stub, should be as short as possible. The reason for the short distance is because a stub presents a nonterminated piece of bus line which can introduce reflections if the distance is too long. As a general guideline, the
electrical length or round-trip delay of a stub should be less than one-tenth of the rise time of the driver, thus
leading to a maximum physical stub length of as shown in Equation 1.
LStub ≤ 0.1 × tr × v × c
where
•
•
•
tr is the 10/90 rise time of the driver
c is the speed of light (3 × 108 m/s or 9.8 × 108 ft/s)
v is the signal velocity of the cable (v = 78%) or trace (v = 45%) as a factor of c
(1)
Based on Equation 1, with a minimum rise time of 400 ns, Equation 2 shows the maximum cable-stub length of
the SN65HVD888.
LStub ≤ 0.1 × 400 × 10-9 × 3 108 × 0.78 = 9.4 m (or 30.6 ft)
(2)
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LS
A
B
R
D
R RE DE D
Figure 18. Stub Length
9.1.5 3- to 5-V Interface
Interfacing the SN65HVD888 to a 3-V controller is easy. Because the 5-V logic inputs of the transceiver accept
3-V input signals they can be directly connected to the controller I/O. The 5-V receiver output, R, however must
be level-shifted by a Schottky diode and a 10-k resistor to connect to the controller input (see Figure 19). When
R is high, the diode is reverse biased and the controller supply potential lies at the controller RxD input. When R
is low, the diode is forward biased and conducts. In this case only the diode forward voltage of 0.2 V lies at the
controller RxD input.
3.3V
10k
5V
BAS70
MCU
RxD
1
R
RCV
2
RE
DRV
3
DE
TxD
4
D
Vcc
8
A
7
B
6
GND
5
HVD8X
0.1µF
Figure 19. 3-V to 5-V Interface
9.1.6 Noise Immunity
The input sensitivity of a standard RS-485 transceiver is ±200 mV. When the differential input voltage, VID, is
greater than +200 mV, the receiver output turns high, for VID < –200 mV the receiver outputs low.
The SN65HVD888 transceiver implements high receiver noise-immunity by providing a typical positive-going
input threshold of 35 mV and a minimum hysteresis of 40 mV. In the case of a noisy input condition therefore, a
differential noise voltage of up to 40 mVPP can be present without causing the receiver output to change states
from high to low.
9.1.7 Transient Protection
The bus terminals of the SN65HVD888 transceiver family possess on-chip ESD protection against ±16 kV HBM
and ±12 kV IEC61000-4-2 contact discharge. The International Electrotechnical Commision (IEC) ESD test is far
more severe than the HBM ESD test. The 50% higher charge capacitance, CS, and 78% lower discharge
resistance, RD of the IEC model produce significantly higher discharge currents than the HBM model.
As stated in the IEC 61000-4-2 standard, contact discharge is the preferred transient protection test method.
Although IEC air-gap testing is less repeatable than contact testing, air discharge protection levels are inferred
from the contact discharge test results.
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RD
50M
(1M)
High-Voltage
Pulse
Generator
330
(1.5k)
CS
150pF
(100pF)
Device
Under
Test
Current - A
RC
40
35
30
25
20
15
10
5
0
10kV IEC
10kV HBM
0
50
100
150
200
250
300
Time - ns
Copyright © 2016, Texas Instruments Incorporated
Figure 20. HBM and IEC-ESD Models and Currents in Comparison (HBM Values in Parenthesis)
The on-chip implementation of IEC ESD protection significantly increases the robustness of equipment. Common
discharge events occur because of human contact with connectors and cables. Designers may choose to
implement protection against longer duration transients, typically referred to as surge transients. Figure 12
suggests two circuit designs providing protection against short and long duration surge transients, in addition to
ESD and Electrical Fast Transients (EFT) transients. Table 4 lists the bill of materials for the external protection
devices.
EFTs are generally caused by relay-contact bounce or the interruption of inductive loads. Surge transients often
result from lightning strikes (direct strike or an indirect strike which induce voltages and currents), or the
switching of power systems, including load changes and short circuits switching. These transients are often
encountered in industrial environments, such as factory automation and power-grid systems.
Figure 21 compares the pulse-power of the EFT and surge transients with the power caused by an IEC ESD
transient. In the diagram on the left of Figure 21, the tiny blue blip in the bottom left corner represents the power
of a 10-kV ESD transient, which already dwarfs against the significantly higher EFT power spike, and certainly
dwarfs against the 500-V surge transient. This type of transient power is well representative of factory
environments in industrial and process automation. The diagram on the fright of Figure 21 compares the
enormous power of a 6-kV surge transient, most likely occurring in e-metering applications of power generating
and power grid systems, with the aforementioned 500-V surge transient.
NOTE
The unit of the pulse-power changes from kW to MW, thus making the power of the 500-V
surge transient almost dropping off the scale.
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22
20
18
16
14
12
10
8
6
4
2
0
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Pulse Power - MW
Pulse Power - kW
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0.5kV Surge
4kV EFT
10kV ESD
0
5
10
15
20
25
30
35
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
6kV Surge
0.5kV Surge
0
40
5
10
15
20
25
30
35
40
Time - μs
Time - μs
Figure 21. Power Comparison of ESD, EFT, and Surge Transients
In the case of surge transients, hgih-energy content is signified by long pulse duration and slow decaying pulse
power
The electrical energy of a transient that is dumped into the internal protection cells of the transceiver is converted
into thermal energy. This thermal energy heats the protection cells and literally destroys them, thus destroying
the transceiver. Figure 22 shows the large differences in transient energies for single ESD, EFT, and surge
transients as well as for an EFT pulse train, commonly applied during compliance testing.
1000
100
Surge
Pulse Energy - Joule
10
1
EFT Pulse Train
0.1
0.01
EFT
10-3
10-4
ESD
10-5
10-6
0.5
1
2
4
6
8 10
15
Peak Pulse Voltage - kV
Figure 22. Comparison of Transient Energies
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Table 4. Bill of Materials
DEVICE
FUNCTION
ORDER NUMBER
MANUFACTURER
XCVR
5-V, 250-kbps RS-485 Transceiver
SN65HVD888
R1, R2
10-Ω, Pulse-Proof Thick-Film Resistor
CRCW0603010RJNEAHP
Vishay
TVS
Bidirectional 400-W Transient Suppressor
CDSOT23-SM712
Bourns
TBU1, TBU2
Bidirectional.
TBU-CA-065-200-WH
Bourns
MOV1, MOV2
200mA Transient Blocking Unit 200-V, MetalOxide Varistor
MOV-10D201K
Bourns
Vcc
Vcc
Vcc
10k
1
R
2
RE
DIR
3
DE
TxD
4
RxD
MCU
TI
Vcc
8
B
7
A
6
GND
5
XCVR
D
0.1 F
Vcc
10k
R1
1
R
2
RE
DIR
3
DE
TxD
4
D
RxD
TVS
MCU
8
B
7
A
6
GND
5
XCVR
R2
10k
Vcc
0.1 F
R1
TBU1
MOV1
TVS
MOV2
R2
10k
TBU2
Copyright © 2016, Texas Instruments Incorporated
Figure 23. Transient Protections Against ESD, EFT, and Surge Transients
The left circuit shown in Figure 23 provides surge protection of ≥ 500-V transients, while the right protection
circuits can withstand surge transients of 5 kV.
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9.2 Typical Application
Many RS-485 networks use isolated bus nodes to prevent the creation of unintended ground loops and their
disruptive impact on signal integrity. An isolated bus node typically includes a micro controller that connects to
the bus transceiver through a multi-channel, digital isolator (Figure 24).
0.1μF
2
Vcc D2 3
1:1.33 MBR0520L
SN6501
GND D1
N
3
1
10μF
IN
OUT
1
TLV70733
10μF 0.1μF
4,5
L1
4
EN
GND
5VISO
2
10μF
7
R1
6
R2
MBR0520L
ISO-BARRIER
3.3V
0.1μF
PSU
0.1μF
PE
0.1μF
4.7k
PE
2
DVcc
5
6
XOUT
XIN
UCA0RXD
P3.0
MSP430
F2132
DVss
P3.1
UCA0TXD
4
16
11
12
15
1
16
Vcc1
Vcc2
7
10
EN1 ISO7241 EN2
6
11
OUTD
IND
3
14
INA
OUTA
4
13
INB
OUTB
5
12
INC
OUTC
GND1
GND2
2,8
0.1μF
4.7k
1
2
3
4
R
RE
DE
8
Vcc
B
HVD888
A
D GND2
5
TVS
9,15
R HV
Short thick Earth wire or Chassis
Protective Earth Ground,
Equipment Safety Ground
Floating RS-485 Common
C HV
PE
island
R1,R2, TVS: see A. below
RHV = 1MΩ, 2kV high-voltage resistor, TT electronics, HVC 2010 1M0 G T3
CHV = 4.7nF, 2kV high-voltage capacitor, NOVACAP, 1812 B 472 K 202 N T
Copyright © 2017, Texas Instruments Incorporated
A.
See Table 4.
Figure 24. Isolated Bus Node With Transient Protection
9.2.1 Design Requirements
Example Application: Isolated Bus Node with Transient Protection
• RS-485-compliant bus interface (needs differential signal amplitude of at least 1.5 V under fully-loaded
conditions – essentially, maximum number of nodes connected and with dual 120-Ω termination).
• Galvanic isolation of both signal and power supply lines.
• Able to withstand ESD transients up to 12 kV (per IEC 61000-4-2) and EFTs up to 4 kV (per IEC 61000-4-4).
• • Full control of data flow on bus in order to prevent contention (for half-duplex communication).
9.2.2 Detailed Design Procedure
Power isolation is accomplished using the push-pull transformer driver SN6501 and a low-cost LDO, TLV70733.
Signal isolation uses the quadruple digital isolator ISO7241. Notice that both enable inputs, EN1 and EN2, are
pulled-up via 4.7-kΩ resistors to limit input currents during transient events.
While the transient protection is similar to the one in Figure 23 (left circuit), an additional high-voltage capacitor
diverts transient energy from the floating RS-485 common further towards Protective Earth (PE) ground. This
diversion is necessary as noise transients on the bus are usually referred to Earth potential.
RVH refers to a high-voltage resistor, and in some applications even a varistor. This resistance is applied to
prevent charging of the floating ground to dangerous potentials during normal operation.
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Typical Application (continued)
Occasionally varistors are used instead of resistors in order to rapidly discharge CHV, if expected that fast
transients might charge CHV to high-potentials.
Note that the PE island represents a copper island on the PCB for the provision of a short, thick Earth wire
connecting this island to PE ground at the entrance of the power supply unit (PSU).
In equipment designs using a chassis, the PE connection is usually provided through the chassis itself. Typically
the PE conductor is tied to the chassis at one end while the high-voltage components, CHV and RHV, are
connecting to the chassis at the other end.
9.2.3 Application Curve
Figure 25. SN65HVD888 D Input (Top), Differential Output (Middle), and R Output (Bottom), 250 kbps
Operation, PRBS Data Pattern
10 Power Supply Recommendations
To ensure reliable operation at all data rates and supply voltages, each supply should be decoupled with a 100nF ceramic capacitor located as close to the supply pins as possible. This helps to reduce supply voltage ripple
present on the outputs of switched-mode power supplies and also helps to compensate for the resistance and
inductance of the PCB power planes.
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11 Layout
11.1 Layout Guidelines
11.1.1 Design and Layout Considerations For Transient Protection
Because ESD and EFT transients have a wide frequency bandwidth from approximately 3 MHz to 3 GHz, highfrequency layout techniques must be applied during PCB design.
In order for PCB design to be successful, begin with the design of the protection circuit in mind.
1. Place the protection circuitry close to the bus connector to prevent noise transients from penetrating your
board.
2. Use Vcc and ground planes to provide low-inductance. Note that high-frequency currents follow the path of
least inductance and not the path of least impedance.
3. Design the protection components into the direction of the signal path. Do not force the transients currents to
divert from the signal path to reach the protection device.
4. Apply 100- to 220-nF bypass capacitors as close as possible to the VCC-pins of transceiver, UART, controller
ICs on the board.
5. Use at least two vias for VCC and ground connections of bypass capacitors and protection devices to
minimize effective via-inductance.
6. Use 1- to 10-k pullup or pulldown resistors for enable lines to limit noise currents in theses lines during
transient events.
7. Insert pulse-proof resistors into the A and B bus lines if the TVS clamping voltage is higher than the specified
maximum voltage of the transceiver bus terminals. These resistors limit the residual clamping current into the
transceiver and prevent it from latching up.
– While pure TVS protection is sufficient for surge transients up to 1 kV, higher transients require metaloxide varistors (MOVs) which reduce the transients to a few-hundred volts of clamping voltage, and
transient blocking units (TBUs) that limit transient current to some 200 mA.
11.2 Layout Example
5
Via to ground
Via to VCC
4
6 R
1
R
MCU
JMP
C
R
R
7
5
R
6 R
TVS
5
SN65HVD888
Figure 26. SN65HVD888 Layout Example
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: SN65HVD888
23
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN65HVD888D
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HVD888
SN65HVD888DR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HVD888
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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