SN65HVDA195-Q1
SLLS961C – JULY 2009 – REVISED JUNE 2022
SN65HVDA195-Q1 Automotive LIN and Most ECL Physical Interface
1 Features
3 Description
•
The SN65HVDA195 device is the Local Interconnect
Network (LIN) physical interface and MOST ECL
interface, which integrates the serial transceiver with
wake-up and protection features. The bus is a singlewire bidirectional bus typically used for low-speed invehicle networks using data rates to 20 kbps. The
device can transmit with an effective data rate of
0 kbps because it does not have dominant state
time-out. The protocol output data stream on TXD
is converted by the SN65HVDA195 into the bus
signal through a current-limited wave-shaping driver
as outlined by the LIN physical layer specification
revision 2.0. The receiver converts the data stream
from the bus and outputs the data stream through
RXD. The bus has two states: dominant state (voltage
near ground) and the recessive state (voltage near
battery). In the recessive state, the bus is pulled
high by the SN65HVDA195 internal pullup resistor
and series diode, so no external pullup components
are required for responder applications. Commander
applications require an external pullup resistor (1 kΩ)
plus a series diode per the LIN specification.
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LIN Physical layer specification revision
2.0 compliant and conforms to SAEJ2602
recommended practice for LIN
LIN Bus speed up to 20-kbps LIN specified
maximum and MOST ECL speeds down to 0 Baud
Supports ISO9141 (k-line)
Qualified for automotive applications
Sleep mode: ultra low current consumption, allows
wake-up events from LIN bus, wake-up Input
(external switch), or host microcontroller
High-speed receive capable
ESD protection to ±12 kV (human body model) on
LIN pin
LIN pin handles voltage from –40 V to 40 V
Survives transient damage in automotive
environment (ISO 7637)
Extended operation with supply from 7 V to 27 V
DC (LIN specification 7 V to 18 V)
Interfaces to microcontroller with 5-V or 3.3-V I/O
pins
Wake-up request on RXD pin
Control of external voltage regulator (INH pin)
Integrated pullup resistor and series diode for LIN
responder applications
Low electromagnetic emission (EME), high
electromagnetic immunity (EMI)
Bus terminal short circuit protected for short-tobattery or short-to-ground
Thermally protected
Ground disconnection fail-safe at system level
Ground shift operation at system level
Unpowered node does not disturb the network
Device Information
PACKAGE(1)
PART NUMBER
SN65HVDA195-Q1
(1)
SOIC (8)
4.90 mm × 3.91 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
VSUP
INH
RXD
VSUP
VSUP/2
2 Applications
•
•
•
BODY SIZE (NOM)
Receiver
Automotive
Industrial sensing
White goods distributed control
EN
Filter
Wake up
State
INH Control
NWAKE
TXD
Filter
Fault Detection
and Protection
Dominant State
Timeout
Driver with
Slope Control
Simplified Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
30lQ
LIN
SN65HVDA195-Q1
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SLLS961C – JULY 2009 – REVISED JUNE 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Description (continued).................................................. 3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information....................................................4
7.5 Electrical Characteristics.............................................5
7.6 Typical Characteristics................................................ 8
8 Parameter Measurement Information............................ 9
9 Detailed Description......................................................10
9.1 Overview................................................................... 10
9.2 Functional Block Diagram......................................... 10
9.3 Feature Description...................................................10
9.4 Device Functional Modes..........................................12
10 Application and Implementation................................ 15
10.1 Application Information........................................... 15
11 Device and Documentation Support..........................18
11.1 Receiving Notification of Documentation Updates.. 18
11.2 Support Resources................................................. 18
11.3 Trademarks............................................................. 18
11.4 Electrostatic Discharge Caution.............................. 18
11.5 Glossary.................................................................. 18
12 Mechanical, Packaging, and Orderable
Information.................................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (March 2015) to Revision C (June 2022)
Page
• Changed all instances of legacy terminology to commander and responder where mentioned.........................1
Changes from Revision A (October 2009) to Revision B (March 2015)
Page
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ............................................................................................................................................................... 1
• Removed Ordering Information table .................................................................................................................3
• Deleted Device Comparison table ................................................................................................................. 0
2
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5 Description (continued)
In sleep mode, the SN65HVDA195 requires low quiescent current while the wake-up circuits remain active. This
allows remote wake up through the LIN bus or local wake up through the NWake or EN pins.
The SN65HVDA195 has been designed for operation in the harsh automotive environment. The device can
handle LIN bus voltage swings from 40 V down to ground and survive –40 V. The device also prevents
back-feed current through LIN to the supply input, in case of a ground shift or supply voltage disconnection. It
also features undervoltage, overtemperature, and loss-of-ground protection. In the event of a fault condition, the
output is immediately switched off and remains off until the fault condition is removed.
6 Pin Configuration and Functions
RXD
1
8
INH
EN
2
7
V
NWake
3
6
LIN
TXD
4
5
GND
SUP
Not to scale
Figure 6-1. D (SOIC) Package 8-Pin
(Top View)
Table 6-1. Pin Functions
PIN
NO.
1
NAME
TYPE(1)
DESCRIPTION
RXD
O
RXD output (open drain) interface reporting state of LIN bus voltage
2
EN
I
Enable input
3
NWake
I
High voltage input for device wake up
TXD input interface to control state of LIN output
4
TXD
I
5
GND
GND
6
LIN
I/O
7
VSUP
Supply
8
INH
O
(1)
Ground
LIN bus single-wire transmitter and receiver
Device supply voltage (connected to battery in series with external reverse blocking diode)
Inhibit controls external voltage regulator with inhibit input
I = Input, O = Output, I/O = Input or Output, G = Ground.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER
VSUP
(2)
Supply line supply
voltage(3)
MIN
MAX
0
40
–0.3
40
UNIT
V
VNWake
NWake DC and transient input voltage (through serial resistor)
INWake
NWake current if due to ground shifts VNWake ≤ VGND – 0.3 V, thus the current into NWake
must be limited through a serial resistance.
VINH
INH voltage
VLogic_Input
Logic pin input voltage
VLIN
LIN DC-input voltage
–40
40
TA
Operational free-air temperature
–40
125
°C
TJ
Junction temperature
–40
150
°C
TSD
Thermal shutdown
200
°C
TSD_HYS
Thermal shutdown hysteresis
25
°C
Tstg
Storage temperature
165
°C
(1)
(2)
(3)
(4)
RXD, TXD, EN
–3.6
–0.3
VSUP + 0.3
–0.3
5.5
–40
mA
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
All voltage values are with respect to GND.
The device is specified for operation in the range of VSUP from 7 V to 27 V. Operating the device more than 27 V may significantly raise
the junction temperature of the device and system level thermal design must be considered.
The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin.
7.2 ESD Ratings
VALUE
V(ESD)
Electrostatic
discharge
Human body model (HBM), per AEC
Q100-002(1)
Charged-device model (CDM), per AEC
Q100-011
(1)
All pins except LIN and NWake
±4000
Pin LIN
±12000
Pin NWake
±11000
All pins
±1500
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VSUP
7
27
V
TAMB
–40
125
°C
7.4 Thermal Information
THERMAL METRIC(1)
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
112.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
66.3
°C/W
RθJB
Junction-to-board thermal resistance
52.9
°C/W
ψJT
Junction-to-top characterization parameter
19.3
°C/W
ψJB
Junction-to-board characterization parameter
52.4
°C/W
(1)
4
D (SOIC)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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7.5 Electrical Characteristics
VSUP = 7 V to 27 V, TA = –40°C to 125°C (unless otherwise noted)
MIN
TYP(1)
MAX
Device is operational beyond the LIN 2.0 defined
nominal supply line voltage range of 7 V ≤ VSUP ≤
18 V
7
14
27
Normal and standby modes
7
14
18
Sleep mode
7
PARAMETER
TEST CONDITIONS
UNIT
SUPPLY
Operational supply voltage(2)
Nominal supply line voltage
VSUP undervoltage threshold
Normal mode, EN = High, Bus dominant (total
bus load where RLIN ≥ 500 Ω and CLIN ≤ 10 nF
(see Figure 8-1)(3), INH = VSUP, NWake = VSUP
Supply current
Delta supply current in sleep
mode
6
1.2
7.5
1
2.1
Normal mode, EN = High, Bus recessive, LIN =
VSUP, INH = VSUP, NWake = VSUP
450
775
Standby mode, EN = Low, Bus recessive, LIN =
VSUP, INH = VSUP, NWake = VSUP
450
775
13
26
Sleep mode, EN = 0, TA = –40°C to 95°C,
7 V < VSUP ≤ 12 V, LIN = VSUP,
NWake = VSUP
ΔISUP
18
mA
Standby mode, EN = low, Bus dominant (total bus
load where RLIN ≥ 500 Ω and CLIN ≤ 10 nF (see
Figure 8-1)(3), INH = VSUP, NWake = VSUP
ISUP
12
4.8
V
μA
Sleep mode, EN = 0, TA = –40°C to 95°C,
12 V < VSUP < 18 V, LIN = VSUP,
NWake = VSUP
35
Sleep mode, EN = 0, TA = –40°C to 95°C, Supply
line voltage range of
7 V ≤ VSUP ≤ 18 V, LIN bus voltage: VSUP – 1.85
V ≤ LIN ≤ VSUP
20
RXD OUTPUT PIN
VO
Output voltage
IOL
Low-level output current, open
LIN = 0 V, RXD = 0.4 V
drain
–0.3
3.5
IIKG
Leakage current, high-level
–5
LIN = VSUP, RXD = 5 V
5.5
V
mA
0
5
μA
TXD INPUT PIN
VIL
Low-level input voltage
–0.3
0.8
VIH
High-level input voltage
2
5.5
VIT
Input threshold hysteresis
voltage
30
500
mV
Pulldown resistor
IIL
Low-level input current
TXD = Low
V
125
350
800
kΩ
–5
0
5
μA
LIN PIN (REFERENCED TO VSUP)
VOH
High-level output voltage
LIN recessive, TXD = High,
IO = 0 mA, VSUP = 14 V
VOL
Low-level output voltage
LIN dominant, TXD = Low,
IO = 40 mA, VSUP = 14 V
0
Pullup resistor to VSUP
Normal and standby modes
20
Pullup current source to VSUP
Sleep mode, VSUP = 14 V, LIN = GND
–2
TXD = 0 V
45
Rrespon
der
IL
Limiting current
TXD = 0 V, TA = –10°C to 125°C
VSUP – 1
V
0.2 × VSUP
30
160
60
kΩ
–20
μA
220
200
mA
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7.5 Electrical Characteristics (continued)
VSUP = 7 V to 27 V, TA = –40°C to 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
–5
0
5
ILKG
Leakage current
LIN = VSUP
ILKG
Leakage current, loss of
supply
7 V < LIN ≤ 12 V, VSUP = GND
5
12 V < LIN < 18 V, VSUP = GND
10
VIL
Low-level input voltage
LIN dominant
VIH
High-level input voltage
LIN recessive
VIT
Input threshold voltage
Vhys
Hysteresis voltage
VIL
Low-level input voltage for
wakeup
UNIT
μA
0.4 × VSUP
0.6 × VSUP
0.4 × VSUP
0.5 × VSUP 0.6 × VSUP
0.05 × VSUP
0.175 ×
VSUP
V
0.4 × VSUP
EN PIN
VIL
Low-level input voltage
–0.3
0.8
VIH
High-level input voltage
2
5.5
Vhys
Hysteresis voltage
30
500
mV
Pulldown resistor
125
350
800
kΩ
–5
0
5
μA
VSUP + 0.3
V
35
85
Ω
0
5
μA
IIL
Low-level input current
EN = Low
V
INH PIN
Vo
DC output voltage
–0.3
Ron
On state resistance
Between VSUP and INH, INH = 2-mA drive,
Normal or standby mode
IIKG
Leakage current
Low-power mode, 0 < INH < VSUP
–5
NWAKE PIN
VIL
Low-level input voltage
–0.3
VSUP – 3.3
VIH
High-level input voltage
VSUP – 1
VSUP + 0.3
IIKG
Pullup current
NWake = 0 V
Leakage current
VSUP = NWake
–45
–10
–2
–5
0
5
V
μA
THERMAL SHUTDOWN
Shutdown junction thermal
temperature
190
°C
AC CHARACTERISTICS
D1
D2
D3
6
Duty cycle 1(4)
THREC(max) = 0.744 × VSUP, THDOM(max) = 0.581 ×
VSUP,
VSUP = 7 V to 18 V,
tBIT = 50 μs (20 kbps),
D1 = tBus_rec(min)/ (2 × tBIT).
See Figure 7-1
Duty cycle 2(4)
THREC(min) = 0.422 × VSUP, THDOM(min) = 0.284 ×
VSUP,
VSUP = 7.6 V to 18 V,
tBIT = 50 μs (20 kbps),
D2 = tBus_rec(max)/ (2 × tBIT).
See Figure 7-1
Duty cycle 3(4)
THREC(max) = 0.778 × VSUP, THDOM(max) = 0.616 ×
VSUP,
VSUP = 7 V to 18 V,
tBIT = 96 μs (10.4 kbps),
D3 = tBus_rec(min)/ (2 × tBIT).
See Figure 7-1
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7.5 Electrical Characteristics (continued)
VSUP = 7 V to 27 V, TA = –40°C to 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
D4
Duty cycle 4(4)
THREC(min) = 0.389 × VSUP, THDOM(min) = 0.251 ×
VSUP,
VSUP = 7.6 V to 18 V,
tBIT = 96 μs (10.4 kbps),
D4 = tBus_rec(max)/ (2 × tBIT).
See Figure 7-1
trx_pdr
Receiver rising propagation
delay time
RRXD = 2.4 kΩ, CRXD = 20 pF
See Figure 7-2
See Figure 8-1
6
trx_pdf
Receiver falling propagation
delay time
RRXD = 2.4 kΩ, CRXD = 20 pF
See Figure 7-2
See Figure 8-1
6
trx_sym
Symmetry of receiver
propagation delay time
rising edge with respect to falling edge (trx_sym =
trx_pdf – trx_pdr)
RRXD = 2.4 kΩ, CRXD = 20 pF
See Figure 7-2
See Figure 8-1
–2
tNWake
NWake filter time for local
wakeup
See Figure 9-4
25
50
150
LIN wake-up filter time
tLINBUS (dominant time for wakeup
through LIN bus)
See Figure 9-3
25
50
150
tgo_to_operate
See Figure 9-2 to Figure 9-3
0.5
1
(1)
(2)
(3)
(4)
UNIT
0.59
2
μs
Typical values are given for VSUP = 14 V at 25°C, except for low power mode where typical values are given for VSUP = 12 V at 25°C.
All voltages are defined with respect to ground; positive currents flow into the SN65HVDA195 device.
In the dominant state, the supply current increases as the supply voltage increases due to the integrated LIN responder termination
resistance. At higher voltages the majority of supply current is through the termination resistance. The minimum resistance of the LIN
responder termination is 20 kΩ, so the maximum supply current attributed to the termination is:
ISUP (dom) max termination ≉ (VSUP – (VLIN_Dominant + 0.7 V) / 20 kΩ
Duty cycles: LIN driver bus load conditions (CLINBUS, RLINBUS): Load1 = 1 nF, 1 kΩ; Load2 = 10 nF, 500 Ω. Duty cycles 3 and 4 are
defined for 10.4-kbps operation. The SN65HVDA195 also meets these lower data rate requirements, while it is capable of the higher
speed 20-kbps operation as specified by Duty cycles 1 and 2. SAEJ2602 derives propagation delay equations from the LIN 2.0 duty
cycle definitions, for details see the SAEJ2602 specification.
tBit
tBit
RECESSIVE
D = 0.5
TXD (Input)
DOMINANT
THRec(max)
LIN Bus
Signal
Thresholds
:
Worst case 1
THDom(max)
Vsup
THRec(min)
Thresholds
:
Worst case 2
THDom(min)
tBus_dom(max)
tBus_rec(max)
D = tBus_rec(min)/(2 x tBit)
RXD
D1 (20 kbps) and
D3 (10 kbps) case
tBus_dom(min)
tBus_rec(min)
D = tBus_rec(max)/(2 x tBit)
RXD
D2 (20 kbps) and
D4 (10 kbps) case
Figure 7-1. Definition of Bus Timing Parameters
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LIN Bus
0.6 V SUP
VSUP
0.4 V SUP
trx_pdf
trx_pdr
RXD
50%
50%
Figure 7-2. Propagation Delay
7.6 Typical Characteristics
1000
30
900
25
800
20
VOL (mV)
700
15
)
V
m
(
VOH
H
O
V
L
O
600
500
V
10
VOHLIN -40°C
5
400
VOLLIN (mV) -40°C
VOHLIN 25°C
VOLLIN (mV) 25° C
300
VOLLIN (mV) 125°C
VOHLIN 125°C
200
0
5
10
15
20
25
30
5
10
20
25
30
VSUP
VSUP
Figure 7-4. VSUP vs VOL
Figure 7-3. VSUP vs VOH
8
15
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8 Parameter Measurement Information
VCC
RRXD
INH
RXD
CRXD
VSUP
100 nF
EN
RLIN
NWake
LIN
CLIN
TXD
GND
Figure 8-1. Test Circuit for AC Characteristics
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9 Detailed Description
9.1 Overview
The SN65HVDA195-Q1 LIN transceiver is a LIN (Local Interconnect Network) physical layer transceiver which
integrates a serial transceiver with wake up and protection features. The LIN bus is a single wire, bi-directional
bus that typically is used in low speed in vehicle networks with data rates that range from 2.4 kbps to 20 kbps
9.2 Functional Block Diagram
VSUP
RXD 1
8
INH
7
VSUP
6
LIN
5
GND
VSUP/2
Receiver
EN 2
Filter
Wake up
State
INH Control
NWAKE 3
Filter
TXD 4
30lQ
Fault Detection
and Protection
Dominant State
Timeout
Driver with
Slope Control
9.3 Feature Description
9.3.1 Local Interconnect Network (LIN) Bus
This I/O pin is the single-wire LIN bus transmitter and receiver.
9.3.1.1 Transmitter Characteristics
The driver is a low-side transistor with internal current limitation and thermal shutdown. There is an internal
30-kΩ pullup resistor with a serial diode structure to VSUP, so no external pullup components are required for LIN
responder mode applications. An external pullup resistor of 1 kΩ, plus a series diode to VSUP must be added
when the device is used for commander node applications.
Voltage on LIN can go from –40-V to 40-V DC without any currents other than through the pullup resistance.
There are no reverse currents from the LIN bus to supply (VSUP), even in the event of a ground shift or loss of
supply (VSUP).
The LIN thresholds and AC parameters are LIN Protocol Specification Revision 2.0 compliant.
During a thermal shut down condition, the driver is disabled.
9.3.1.2 Receiver Characteristics
The receiver’s characteristic thresholds are ratio-metric with the device supply pin. Typical thresholds are 50%,
with a hysteresis from 5% to 17.5% of supply.
The receiver is capable of receiving higher data rates (>100 kbps) than supported by LIN or SAEJ2602
specifications. This allows the SN65HVDA195 to be used for high-speed downloads at end-of-line production
or other applications. The actual data rates achievable depend on system time constants (bus capacitance and
pullup resistance) and driver characteristics used in the system.
10
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9.3.2 Transmit Input (TXD)
TXD is the interface to the MCU’s LIN protocol controller or SCI/UART used to control the state of the LIN
output. When TXD is low, the LIN output is dominant (near ground). When TXD is high, the LIN output is
recessive (near battery). The TXD input structure is compatible with microcontrollers with 3.3-V and 5-V I/O. TXD
has an internal pulldown resistor. This device does not have a TXD dominant time-out protection circuit so that
low data rates may be used.
9.3.3 Receive Output (RXD)
RXD is the interface to the MCU’s LIN protocol controller or SCI/UART, which reports the state of the LIN bus
voltage. LIN recessive (near battery) is represented by a high level on RXD and LIN dominant (near ground) is
represented by a low level on RXD. The RXD output structure is an open-drain output stage. This allows the
SN65HVDA195 to be used with 3.3-V and 5-V I/O microcontrollers. If the microcontroller’s RXD pin does not
have an integrated pullup, an external pullup resistor to the microcontroller I/O supply voltage is required.
9.3.3.1 RXD Wake-Up Request
When the SN65HVDA195 has been in low-power mode and encounters a wake-up event from the LIN bus or
NWake pin, RXD goes low, while the device enters and remains in standby mode (until EN is reasserted high
and the device enters normal mode).
9.3.4 Supply Voltage (VSUP)
VSUP is the SN65HVDA195 device power supply pin. VSUP is connected to the battery through an external
reverse battery blocking diode. The characterized operating voltage range for the SN65HVDA195 is from 7 V to
27 V. VSUP is protected for harsh automotive conditions up to 40 V.
The device contains a reset circuit to avoid false bus messages during undervoltage conditions when VSUP is
less than VSUP_UNDER.
9.3.5 Ground (GND)
GND is the SN65HVDA195 device ground connection. The SN65HVDA195 can operate with a ground shift as
long as the ground shift does not reduce VSUP below the minimum operating voltage. If there is a loss of ground
at the ECU level, the SN65HVDA195 does not have a significant current consumption on LIN bus.
9.3.6 Enable Input (EN)
EN controls the operation mode of the SN65HVDA195 (normal or sleep mode). When EN is high, the
SN65HVDA195 is in normal mode allowing a transmission path from TXD to LIN and from LIN to RXD. When
EN is low, the device is put into sleep mode and there are no transmission paths available. The device can enter
normal mode only after being woken up. EN has an internal pulldown resistor to make sure the device remains in
low-power mode even if EN floats.
9.3.7 NWake Input (NWake)
NWake is a high-voltage input used to wake up the SN65HVDA195 from low-power mode. NWake is usually
connected to an external switch in the application. A low on NWake that is asserted longer than the filter time
(tNWAKE) results in a local wakeup. NWake provides an internal pullup source to VSUP.
9.3.8 Inhibit Output (INH)
INH is used to control an external voltage regulator that has an inhibit input. When the SN65HVDA195 is in
normal operating mode, the inhibit high-side switch is enabled and the external voltage regulator is activated.
When SN65HVDA195 is in low-power mode, the inhibit switch is turned off, which disables the voltage regulator.
A wake-up event on for the SN65HVDA195 returns INH to VSUP level. INH can also drive an external transistor
connected to an MCU interrupt input.
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9.4 Device Functional Modes
9.4.1 Operating Modes
Unpowered System
Vsup £ Vsup_under
Vsup £ Vsup_under
Vsup > Vsup_under
EN = high
Vsup £ Vsup_under
Vsup £ Vsup_under
Vsup > Vsup_under
EN = low
Standby Mode
Driver : Off
RXD: Low
INH: High (On)
Termination: 30 kW
Sleep Mode
Normal Mode
Driver : On
RXD: LIN bus data
INH: High (On)
Termination: 30 kW
LIN Bus Wake-Up
or
Nwake Pin Wake-Up
EN = high
EN = low
Driver : Off
RXD: Floating
INH: High impedance (Off)
Termination: Weak pullup
EN = high
Figure 9-1. Operating States Diagram
Table 9-1. Operating Modes
EN
RXD
LIN BUS
TERMINATION
Sleep
Low
Floating
Weak current pullup
High impedance
Off
Standby
Low
Low
30 kΩ (typ)
High
Off
Wake-up event detected, waiting
on MCU to set EN
Normal
High
LIN bus data
30 kΩ (typ)
High
On
LIN transmission up to 20 kbps
MODE
INH
TRANSMITTER
COMMENTS
9.4.2 Normal Mode
This is the normal operational mode, in which the receiver and driver are active, and LIN transmission up to
the LIN specified maximum of 20 kbps is supported. The receiver detects the data stream on the LIN bus and
outputs it on RXD for the LIN controller, where recessive on the LIN bus is a digital high, and dominate on the
LIN bus is digital low. The driver transmits input data on TXD to the LIN bus. Normal mode is entered as EN
transitions high while the SN65HVDA195 is in sleep or standby mode.
9.4.3 Sleep Mode
Sleep mode is the power saving mode for the SN65HVDA195 and the default state after power up (assuming
EN is low during power up). Even with the extremely low current consumption in this mode, the SN65HVDA195
can still wake up from LIN bus through a wake-up signal, a low on NWake, or if EN is set high. The LIN bus and
NWake are filtered to prevent false wake-up events. The wake-up events must be active for their respective time
periods (tLINBUS, tNWake).
The sleep mode is entered by setting EN low.
12
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While the device is in sleep mode, the following conditions exist:
•
•
•
•
The LIN bus driver is disabled and the internal LIN bus termination is switched off (to minimize power loss if
LIN is short-circuited to ground). However, the weak current pullup is active to prevent false wake-up events
in case an external connection to the LIN bus is lost.
The normal receiver is disabled.
INH is high impedance.
EN input, NWake input, and the LIN wake-up receiver are active.
9.4.4 Wake-Up Events
There are three ways to wake up the SN65HVDA195 from sleep mode:
•
•
•
Remote wakeup through recessive (high) to dominant (low) state transition on LIN bus. The dominant state
must be held for tLINBUS filter time and then the bus must return to the recessive state (to eliminate false
wake-ups from disturbances on the LIN bus or if the bus is shorted to ground).
Local wakeup through a low on NWake, which is asserted low longer than the filter time tNWake (to eliminate
false wake-ups from disturbances on NWake)
Local wakeup through EN being set high
9.4.5 Standby Mode
This mode is entered whenever a wake-up event occurs through LIN bus or NWake while the SN65HVDA195 is
in sleep mode. The LIN bus responder termination circuit and INH are turned on when standby mode is entered.
The application system powers up once INH is turned on, assuming the system is using a voltage regulator
connected through INH. Standby mode is signaled through a low level on RXD.
When EN is set high while the SN65HVDA195 is in standby mode the device returns to normal mode and the
normal transmission paths from TXD to LIN bus and LIN bus to RXD are enabled.
EN
INH
Vsup
High Impedance
TXD
t > tgo_to_operate
Vsup
LIN
RXD
MODE
Floating
Sleep
Normal
Figure 9-2. Wakeup Through EN
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LIN
0.6 × VSUP
0.6 × VSUP
0.4 × VSUP
Vsup
0.4 × VSUP
t < tLINBUS
tLINBUS
Vsup
High Impedance
INH
TXD
t > tgo_to_operate
EN
Floating
RXD
Standby
Sleep
MODE
Normal
Figure 9-3. Wakeup Through LIN
NWake VIL
NWake VIH
NWake VIL
NWake
Vsup
t < tNWake
INH
tNWake
Vsup
High Impedance
TXD
t > tgo_to_operate
EN
RXD
Floating
Vsup
LIN
MODE
Sleep
Standby
Normal
Figure 9-4. Wakeup Through NWake
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10 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
10.1 Application Information
The SN65HVDA195-Q1 can be used as both a responder device and a commander device in a LIN network. It
comes with the ability to support both remote wake-up requests and local wake-up requests.
10.1.1 Typical Application
The device comes with an integrated 30-kΩ pullup resistor and series diode for responder applications, and for
commander applications an external 1-kΩ pullup with series blocking diode can be used. Figure 10-1 shows the
device being used in both types of applications.
VBAT
VSUP
COMMANDER
NODE
TPSxxxx
VSUP
VDD
NWake
VSUP
INH
VDD
VDD
EN
I/O
2
8
3
Commander
Node
Pullup(3)
7
MCU w/o
pullup (2)
1k
VDD I/O
MCU
SN65HVDA195
LIN
Controller
or
SCI/UART(1)
RXD
TXD
GND
LIN
1
6
4
5
220 pF
LIN Bus
TMS470
VSUP
RESPONDER
NODE
TPSxxxx
VSUP
VDD
NWake
INH
VSUP
VDD
EN
I/O
2
8
3
7
MCU w/o
pullup(2)
VDD I/O
MCU
SN65HVDA195
TMS470
LIN
Controller
or
SCI/UART(1)
GND
RXD
TXD
LIN
1
4
6
5
220 pF
A.
B.
RXD on MCU or LIN responder has internal pullup, no external pullup resistor is needed.
RXD on MCU or LIN responder without internal pullup, requires external pullup resistor.
C.
Commander node applications require an external 1-kΩ pullup resistor and serial diode.
Figure 10-1. SN65HVDA195-Q1 Application Diagram
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10.1.1.1 Design Requirements
For this design, use these requirements:
•
•
•
RXD on MCU or LIN responder has internal pullup, no external pullup resistor is needed.
RXD on MCU or LIN responder without internal pullup, requires external pullup resistor.
Commander node applications require an external 1-kΩ pullup resistor and serial diode
10.1.1.2 Detailed Design Procedure
The RXD output structure is an open-drain output stage. This allows the SN65HVDA195-Q1 to be used with
3.3-V and 5-V I/O microcontrollers. If the RXD pin of the microcontroller does not have an integrated pullup, an
external pullup resistor to the microcontroller I/O supply voltage is required.
The VSUP pin of the device should be decoupled with a 100-nF capacitor as close to the supply pin of the device
as possible.
The NWAKE pin is a high voltage wake-up input to the device. If this pin is not being used it should be tied to
VSUP.
10.1.1.3 Application Curves
Figure 10-2 and Figure 10-3 show the propagation delay from the TXD pin to the LIN pin for both the recessive
to dominant and dominant to recessive states under lightly loaded conditions.
Figure 10-2. SN65HVDA195-Q1 Dominant to
Recessive Prop Delay
Figure 10-3. SN65HVDA195-Q1 Recessive to
Dominant Prop Delay
Power Supply Recommendations
The SN65HVDSA195-Q1 was designed to operate directly off a car battery, or any other DC supply ranging from
7 V to 27 V. A100-nF decoupling capacitor should be placed as close to the VSUP pin of the device as possible.
16
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10.1.2 Layout
10.1.2.1 Layout Guidelines
Pin 1 is the RXD output of the SN65HVDA195-Q1. It is an open-drain output and requires an external pullup
resistor in the range of 1-kΩ to 10 kΩ to function properly. If the micro-processor paired with the transceiver does
not have an integrated pullup and external resistor should be placed between RXD and the regulated voltage
supply for the micro-processor.
Pin 2 is the EN input pin for the device that is used to place the device in low power sleep mode. If this feature
is not used on the device, the pin should be pulled high to the regulated voltage supply of the microprocessor
through a series 1-kΩ to 10-kΩ series resistor. Additionally, a series resistor may be placed on the pin to limit the
current on the digital lines in the case of an overvoltage fault.
Pin 3 is a high-voltage local wake up input pin. The device is typically externally controlled by a normally open
switch tied between NWAKE and ground. When the momentary switch is pressed the NWAKE pin is pulled to
ground signaling a local wake-up event. A series resistor between VBATT and the switch, and NWAKE and the
switch should be placed to limit current. If the NWAKE local wake-up feature is not used, the pin can be tied to
VSUP through a 1-kΩ to 10-kΩ pullup resistor.
Pin 4 is the transmit input signal to the device. A series resistor can be placed to limit the input current to the
device in the case of an overvoltage on this pin. Also a capacitor to ground can be placed close to the input pin
of the device to filter noise.
Pin 5 is the ground connection of the device. This pin should be tied to a ground plane through a short trace with
the use of two vias to limit total return inductance.
Pin 6 is the LIN bus connection of the device. For responder applications a 220-pF bus capacitor is
implemented. For commander applications an additional series resistor and blocking diode should be placed
between the LIN pin and the VSUP pin.
Pin 7 is the supply pin for the device. A 100-nF decoupling capacitor should be placed as close to the device as
possible.
Pin 8 is a high-voltage output pin that may be used to control the local power supplies. If this feature is not used
the pin may be left floating.
Note
All ground and power connections should be made as short as possible and use at least two vias to
minimize the total loop inductance.
10.1.2.2 Layout Example
V
C
R1
8
1
RXD
R7
INH
VSUP
2
7
R4
VC
6
4
5
GND
GND
GND
GND
GND
C1
R6
D3
3
D1
Only needed for
the commander node
C3
R5
TXD
C2
U1
SN65HVDA195-Q1
D2 R7
R3
R2
VSUP EN
Figure 10-4. Layout Example
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN65HVDA195QDRQ1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
A195Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
