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SN65HVS883
SLASEE6 – SEPTEMBER 2016
SN65HVS883 24 V, Eight-Channel Digital-Input Serializer
•
•
•
•
•
Eight Sensor Inputs
– High Input Voltage up to 34 V
– Selectable Debounce Filters
From 0 ms to 3 ms
– Adjustable Current Limits
From 0.2 mA to 5.2 mA
– Field Inputs and Supply Lines Protected
to 15-kV HBM
Output Drivers for External Status LEDs
Cascadable for More Inputs in Multiples of Eight
SPI-Compatible Interface
Regulated 5-V Output for External Digital Isolator
Low-Supply Voltage Indicator
2 Applications
•
•
•
Sensor Inputs for Industrial Automation and
Process Control
– IEC61131-2 Type 1, 2, or 3 Switches
– EN60947-5-2 Proximity Switches
High Channel Count Digital Input Modules for PC
and PLC Systems
Decentralized I/O Modules
3 Description
The SN65HVS883 is a 24-V, eight-channel, digitalinput serializer for high-channel density digital input
modules of PC and PLC-based systems in industrial
automation. In combination with galvanic isolators,
the device completes the interface between the 24-V
sensor outputs of the field-side and the low-voltage
controller inputs at the control-side. Input signals
provided by EN60947-5-2 compliant 2-wire and
3-wire proximity switches are current-limited and then
validated by internal debounce filters. The input
switching characteristic is in accordance with
IEC61131-2 for Type 1, 2, and 3 sensor switches.
Cascading of multiple SN65HVS883 is possible by
connecting the serial output of the leading device with
the serial input of the following device, enabling the
design of high-channel count input modules. Input
status is indicated via 3-mA constant current LED
outputs. An external precision resistor is required to
set the internal reference current. The integrated
voltage regulator provides a 5-V output to supply lowpower isolators. An internal supply voltage monitor
provides a chip-okay (CHOK) indication.
The SN65HVS883 comes in a 28-pin PWP
PowerPAD™ package allowing for efficient heat
dissipation. The device is specified for operation at
temperatures from –40°C to 85°C.
Device Information(1)
PART NUMBER
PACKAGE
SN65HVS883
BODY SIZE (NOM)
HTSSOP (28)
9.70 mm x 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified I/O Structure
Voltage
Regulator
24 V In
Debounce Select
DB0:DB1
Field Inputs
IP0:IP7
LED Outputs
RE0:RE7
IREF Adj: RLIM
Field Ground
5 V Out
2
Serial Input
5V
8
8
3
8
SERIALIZER
•
1
Upon the application of load and clock signals, input
data is latched in parallel into the shift register and
afterwards clocked out serially via a subsequent
isolator into a serial PLC input.
Signal
Conditioning
1 Features
Control Inputs
LD, CE, CLK
Serial Output
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN65HVS883
SLASEE6 – SEPTEMBER 2016
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
4
4
4
4
5
6
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions......................
Thermal Information ..................................................
Electrical Characteristics..........................................
Timing Requirements ................................................
Switching Characteristics ..........................................
Typical Input Characteristics.....................................
Typical Voltage Regulator Performance
Characteristics ...........................................................
8.1
8.2
8.3
8.4
9
10
10
11
14
Application and Implementation ........................ 15
9.1 Application Information............................................ 15
9.2 Typical Application ................................................. 18
10 Power Supply Recommendations ..................... 21
11 Layout................................................................... 21
11.1 Layout Guidelines ................................................. 21
11.2 Layout Example .................................................... 21
12 Device and Documentation Support ................. 22
12.1
12.2
12.3
12.4
12.5
12.6
8
Parameter Measurement Information .................. 9
7.1 Waveforms ................................................................ 9
7.2 Signal Conventions ................................................... 9
8
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Third-Party Products Disclaimer ...........................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
22
22
22
22
22
22
13 Mechanical, Packaging, and Orderable
Information ........................................................... 22
Detailed Description ............................................ 10
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
September 2016
*
Initial release.
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5 Pin Configuration and Functions
PWP Package
28 Pin (HTSSOP) With Exposed Thermal Pad
Top View
DB0
1
28
FGND
DB1
2
27
SIP
IP0
3
26
LD
RE0
4
25
CLK
IP1
5
24
CE
RE1
6
23
SOP
IP2
7
22
IP7
RE2
8
21
RE7
IP3
9
20
IP6
RE3
10
19
RE6
IP4
11
18
IP5
RE4
12
17
RE5
RLIM
13
16
CHOK
V24
14
15
5VOP
Thermal
Pad
Not to scale
Pin Functions
PIN
PIN NO.
NAME
DESCRIPTION
1, 2
DB0, DB1
3, 5, 7, 9,
11, 18, 20, 22
Debounce select inputs
IPx
Input channel x
4, 6, 8, 10,
12, 17, 19, 21
REx
Return path x (LED drive)
13
RLIM
Current limiting resistor
14
V24
15
5VOP
24 VDC field supply
5 V output to supply low-power isolators
16
CHOK
Chip okay indicator output
23
SOP
Serial data output
24
CE
Clock enable input
25
CLK
Serial clock input
26
LD
Load pulse input
27
SIP
Serial data input
28
FGND
Field ground
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
V24
Field power input
V24
–0.3
36
UNIT
V
VIPx
Field digital inputs
IPx
–0.3
36
V
VID
Voltage at any logic input
DB0, DB1, CLK, SIP, CE, LD
–0.5
6
V
IO
Output current
CHOK, SOP
±8
mA
PTOT
Continuous total power dissipation
TJ
Junction temperature
See Thermal Information table
170
°C
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS001 (1)
V(ESD)
(1)
(2)
(3)
Electrostatic discharge
All pins
±4000
IPx,V24
±15000
Charged-device model (CDM), per JEDEC specification
JESD22-C101 (2)
All pins
±1000
Machine Mode (3)
All pins
±100
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
JEDEC Standard 22, Method A115-A.
6.3
Recommended Operating Conditions
V24
Field supply voltage
(1)
VIPL
Field input low-state input voltage
VIPH
Field input high-state input voltage (1)
VIL
Logic low-state input voltage
VIH
Logic high-state input voltage
RLIM
Current limiter resistor
fIP
Input data rate (2)
MIN
TYP
MAX
10
24
34
V
0
4
V
34
V
0
0.8
V
2
17
25
5.5
V
500
kΩ
0
TA
UNIT
10
1
TJ
(1)
(2)
UNIT
–40
Mbps
150
°C
85
°C
Field input voltages correspond to an input resistor of RIN = 1.2 kΩ
Maximum data rate corresponds to 0 ms debounce time, (DB0 = open, DB1 = FGND), and RIN = 0 Ω
6.4 Thermal Information
SN65HVS883
THERMAL METRIC (1)
PWP (HTSSOP)
UNIT
28 PINS
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
RθJB
Junction-to-board thermal resistance
PD
(1)
4
Device power dissipation
ILOAD = 50 mA, RIN = 0, IPO–IP7 = V24 = 30 V,
RE7 = FGND, fCLK = 100 MHz,
IIP-LIM and ICC = worst case with RLIM = 25 kΩ
35
°C/W
4.27
°C/W
15
°C/W
2591
mW
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5
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Electrical Characteristics
all voltages measured against FGND unless otherwise stated, see Figure 12
SYMBOL
PARAMETER
VTH–(IP)
Low-level device input threshold voltage
VTH+(IP)
High-level device input threshold voltage
VHYS(IP)
Device input hysteresis
VTH–(IN)
Low-level field input threshold voltage
PIN
IP0–IP7
measured at
field side of RIN
VTH+(IN)
High-level field input threshold voltage
VHYS(IN)
Field input hysteresis
VTH–(V24)
Low-level V24-monitor threshold voltage
VTH+(V24)
High-level V24-monitor threshold voltage
VHYS(V24)
V24-monitor hysteresis
RIP
VOL
Logic low-level output voltage
VOH
Logic high-level output voltage
18 V < V24 < 34 V,
RIN = 1.2 kΩ ± 5%,
RLIM = 25 kΩ
V
V
10
V
16.05
V
18
V
2.3
kΩ
10 V < VIPx < 34 V,
RLIM = 25 kΩ
3.15
3.6
4
mA
IOL = 20 μA
0.4
IOH = –20 μA
4
V24
IP0 to IP7 = V24,
5VOP = open,
REX = FGND,
All logic inputs open
5VOP
2.8
3.15
50
μA
3.5
mA
8.7
mA
18 V < V24 < 34 V,
no load
4.5
5
5.5
18 V < V24 < 34 V,
IL = 50 mA
4.5
5
5.5
V
115
5VOP, V24
Debounce times of input channels
IP0–IP7
Voltage monitor debounce time after V24 < 15
V (CHOK turns low)
tDB-LH
Voltage monitor debounce time after V24 > 18
V (CHOK turns high)
TSHDN
Shutdown temperature
V
V
–50
Linear regulator output current limit
ΔV5/ΔV24 Line regulation
V
1.83
RLIM = 25 kΩ,
REX = FGND
Linear regulator output voltage
V
1
1.4
RE0–RE7
Supply current
V
3 V < VIPx < 6 V,
RIN = 1.2 kΩ ± 5%,
RLIM = 25 kΩ
RE on-state current
tDB-HL
V
5.5
0.75
SOP, CHOK
UNIT
8.4
16.8
IRE-on
tDB
MAX
0.9
9.4
Logic input leakage current
ILIM(5V)
4.3
6
IIL
VO(5V)
4
5.2
DB0, DB1, SIP,
LD, CE, CLK
ICC(V24)
TYP
V24
IP0–IP7
Input current limit
18 V< V24 < 34 V,
RIN = 0 Ω ,
RLIM = 25 kΩ
MIN
15
Input resistance
IIP-LIM
TEST CONDITIONS
18 V < V24 < 34 V,
IL = 5 mA
mA
2
DB0 = open,
DB1 = FGND
0
DB0 = FGND,
DB1 = open
1
DB0 = DB1 = open
3
mV/V
ms
1
ms
6
ms
170
°C
V24, CHOK
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6.6 Timing Requirements
over operating free-air temperature range (unless otherwise noted)
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
tW1
CLK pulse width
See Figure 9
4
ns
tW2
LD pulse width
See Figure 7
6
ns
tSU1
SIP to CLK setup time
See Figure 10
4
ns
tH1
SIP to CLK hold time
See Figure 10
2
ns
tSU2
Falling edge to rising edge (CE to CLK) setup time
See Figure 11
4
ns
tREC
LD to CLK recovery time
See Figure 8
2
fCLK
Clock pulse frequency (50% duty cycle)
See Figure 9
DC
ns
100
MHz
6.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPLH1, tPHL1
CLK to SOP
CL = 15 pF, see Figure 9
10
ns
tPLH2, tPHL2
LD to SOP
CL = 15 pF, see Figure 7
14
ns
tr, tf
Rise and fall times
CL = 15 pF, see Figure 9
5
ns
6
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6.8 Typical Input Characteristics
30
25
a)
b)
c)
VIN (V)
20
15
10
Off
On
5
Field Input Thresholds
0
0
.
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
IIN (mA)
RIN = 1.2 kΩ
a) IIP-LIM = 2.5 mA (RLIM = 36.1 kΩ)
b) IIP-LIM = 3.0 mA (RLIM = 30.1 kΩ)
c) IIP-LIM = 3.6 mA (RLIM = 24.9 kΩ)
102.0
9.6
101.5
9.4
101.0
9.2
100.5
9.0
VIN (V)
IIP-LIM/IIP-LIM–25ºC(%)
Figure 1. Typical Input Characteristics
100.0
8.8
99.5
8.6
99.0
8.4
98.5
8.2
98.0
–45 –35 –25 –15 –5
5
15
25
35
45
55
65
75
85
95
VTH+(IN)
VTH–(IN)
8.0
–45 –35 –25 –15 –5
TA (ºC)
V24 = 24 V
RLIM = 24.9 kΩ
VIN = 24 V
RIN = 1.2 kΩ
Figure 2. Typical Current Limiter Variation vs Ambient
Temperature
5
15
25
35
45
55
65
75
85
95
TA (ºC)
V24 = 24 V
RIN = 1.2 kΩ
RLIM = 24.9 kΩ
Figure 3. Typical Limiter Threshold Voltage Variation vs
Ambient Temperature
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6
5.000
4
4.995
2
4.990
0
4.985
VOUT (V)
ΔVOUT (mV)
6.9 Typical Voltage Regulator Performance Characteristics
–2
–4
4.980
4.975
–6
4.970
–8
4.965
–10
0
5
10
15
20
25
30
35
4.960
–45 –35 –25 –15 –5
15
25 35 45 55 65 75 85 95
TA (°C)
VIN (V)
ILOAD = 5 mA
5
ILOAD = 0 mA
TA = 27°C
Figure 5. Output Voltage vs Ambient Temperature
Figure 4. Line Regulation
5.5
5.0
4.5
VOUT (V)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
5
10
15
20
VIN (V)
25
30
35
RLOAD = 100 Ω
Figure 6. Output Voltage vs Input Voltage
8
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7 Parameter Measurement Information
7.1 Waveforms
For the complete serial interface timing, refer to Figure 21.
tw2
LD
LD
t REC
t PLH2
tPHL2
CLK
SOP
Figure 7. Parallel – Load Mode
Figure 8. Serial – Shift Mode
valid
1/fCLK
t w1
SIP
CLK
tSU 1
t PHL1
tH1
t PLH1
CLK
SOP
tr
Figure 9. Serial – Shift Mode
Figure 10. Serial – Shift Mode
CLK
t SU2
CE
CLK inhibited
Figure 11. Serial – Shift Clock Inhibit Mode
7.2 Signal Conventions
RIN
IPx
IIN
VTH(IN)
VTH(IP)
SN65HVS883
FGND
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Figure 12. On/Off Threshold Voltage Measurements
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8 Detailed Description
8.1 Overview
The SN65HVS883 is an 8 channel, digital input serializer which operates from a 24 V supply and accepts digital
inputs of up to 34 V on the 8 channels (IP0-IP7). The device provides a serially shifted digital output with reduced
voltage ranges of 0-5 V for applications in industrial and building automation systems. The SN65HVS883 meets
JEDEC standards for ESD protection (refer to ESD Ratings), and is SPI compatible for interfacing with standard
microcontrollers. The serializer operates in 2 fundamental modes: Load Mode and Shift mode. In Load mode,
information from the field inputs is allowed to latch into the shift register. In Shift mode, the information stored in
the parallel shift register can be serially shifted to the serial output (SOP). A detailed description of the functional
modes is available in the Device Functional Modes section.
8.2 Functional Block Diagram
Voltage
Regulator
V24
5VOP
5V
Supply
Monitor
CHOK
FGND
RE0
IP0
SIP
Voltage
Sense
IP7
DB1
Current
Sense
&
RE7
DB0
Debounce
Select
Adj. Current
Thresholds
Debounce
Filter
LD
CE
SERIALZER
RLIM
Channel 0
CLK
Channel 7
SOP
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8.3 Feature Description
8.3.1 Digital Inputs
Each digital input operates as a controlled current sink limiting the input current to a maximum value of ILIM. The
current limit is derived from the reference current via ILIM = n × IREF, and IREF is determined by IREF = VREF/RLIM.
Thus, changing the current limit requires the change of RLIM to a different value via: RLIM = n × VREF/ILIM.
Inserting the actual values for n and VREF gives: RLIM = 90 V / ILIM.
While the device is specified for a current limit of 3.6 mA, (via RLIM = 25 kΩ), it is easy to lower the current limit
to further reduce the power consumption. For example, for a current limit of 2.5 mA simply calculate:
90 V
90 V
RLIM =
=
= 36 kΩ
ILIM
2.5 mA
(1)
1.25 VREF
5V
ILIM Mirror
n = 72
IIN
IPx
ILIM
Limiter
IINmax = ILIM
IREF
RLIM
Figure 13. Digital Input Stage
8.3.2 Debounce Filter
The HVS883 applies a simple analog/digital filtering technique to remove unintended signal transitions due to
contact bounce or other mechanical effects. Any new input (either low or high) must be present for the duration
of the selected debounce time to be latched into the shift register as a valid state.
The logic signal levels at the control inputs, DB0 and DB1 of the internal Debounce-Select logic determine the
different debounce times listed in the following truth table.
Table 1. Debounce Times
DB1
DB0
FUNCTION
Open
Open
3 ms delay
Open
FGND
1 ms delay
FGND
Open
0 ms delay
(Filter bypassed)
FGND
FGND
Reserved
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5V
IPx
REF
REx
RLIM
FGND
Figure 14. Equivalent Input Diagram
8.3.3 Shift Register
The conversion from parallel input to serial output data is performed by an eight-channel, parallel-in serial-out
shift register. Parallel-in access is provided by the internal inputs, PIP0–PIP7, that are enabled by a low level at
the load input (LD). When clocked, the latched input data shift towards the serial output (SOP). The shift register
also provides a clock-enable function.
Clocking is accomplished by a low-to-high transition of the clock (CLK) input while LD is held high and the clock
enable (CE) input is held low for all registers in the shift register except the last register which is latched by a
high-to-low transition. Parallel loading is inhibited when LD is held high. The parallel inputs to the register are
enabled while LD is low independently of the levels of the CLK, CE, or serial (SIP) inputs.
SIP
D
CLK
CE
Logic
Q
D
S
R
CP
R
Q
D
S
R
CP
Q
D
S
R
CP
Q
D
S
R
CP
Q
D
S
R
CP
Q
D
S
R
CP
Q
CP
D
CP
S
Q
D
Q
SOP
CP
R
S
LD
PIP 0
PIP 1
PIP 2
PIP 3
PIP 4
PIP 5
PIP 6
PIP 7
Figure 15. Shift Register Logic Structure
12
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Table 2. Function Table
INPUTS
(1)
(2)
LD
CLK
FUNCTION
CE
L
X
X
Parallel load
H
X
H
No change
H
↑
L
Shift (1)
H
↓
L
Shift (2)
Shift = content of each internal register, except the last register, shifts towards serial output.
Shift = content of the last register shifts towards serial output.
8.3.4 Voltage Regulator
The on-chip linear voltage regulator provides a 5 V supply to the internal- and external circuitry, such as digital
isolators, with an output drive capability of 50 mA and a typical current limit of 115 mA. The regulator accepts
input voltages from 34 V down to 10 V. Because the regulator output is intended to supply external digital isolator
circuits proper output voltage decoupling is required. For best results connect a 1 μF and a 0.1 μF ceramic
capacitor as close as possible to the 5VOP-output. For longer traces between the SN65HVS883 and isolators of
the ISO72xx family use additional 0.1 μF and 10 pF capacitors next to the isolator supply pins. Make sure,
however, that the total load capacitance does not exceed 4.7 μF.
For good stability the voltage regulator requires a minimum load current, IL-MIN. Ensure that under any operating
condition the ratio of the minimum load current in mA to the total load capacitance in μF is larger than 1:
IL-MIN 1 mA
>
1 µF
CL
(2)
8.3.5 Supply Voltage Monitor
The integrated supply voltage monitor senses the supply voltage of the SN65HVS883 at the V24-pin. If this
voltage drops below 15 V but stays within the regulator’s operating range, i.e., 15 V > V24 > 10 V, the output
CHOK goes low 1 ms later. When the supply voltage returns to 24 V, the CHOK output turns logic high after
6 ms. Should the supply voltage drop below 10 V, the device ceases operation. Upon the supply returning to
above 18 V, the CHOK output turns high again after 6 ms.
18 V
18 V
15 V
15 V
V24
15 V > V24 > 10 V
1 ms
debounce
time starts
10 V
1 ms
debounce
time starts
tDB-HL
tDB-LH
V24 < 10 V
Circuit ceases
operation
tDB-LH
CHOK
Figure 16. CHOK Output Timing as a Function of Supply Voltage Drop at V24
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8.4 Device Functional Modes
The 2 functional modes of operation are Load mode and Shift mode.
Load mode enables information from the field inputs to latch into the shift register. To enter load mode, the LD
pin must be held low, and the device remains in load mode regardless of the CLK, CE, or serial (SIP) input
levels. A high level at the LD pin switches the device into Shift mode.
When the device is in Shift mode, a low level at the CE pin causes the data stored in all registers of the parallel
shift register except for the last register, to be serially shifted toward the serial output (SOP) on the rising edge of
CLK. The final register in the shift register will be shifted toward the serial output (SOP) on the falling edge of
CLK. A high level at the CE pin inhibits the serial shifting, which is demonstrated in Figure 21. After 8
consecutive CLK cycles, the serial output (SOP) remains at the level of the serial input (SIP) which is internally
pulled to logic high. A logic high at the CE pin is required to signify the end of the serial data output. For of a
daisy chained configuration, the serial output (SOP) of the SN65HVS883 can be connected to the serial input
(SIP) of a following device, and additional clock cycles are required to shift the additional data out of the chain.
The number of consecutive clock cycles will equal 8 times the number of devices in the chain. See Figure 22 for
an example of a cascaded chain of 4x SN65HVS883.
14
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 System-Level EMC
The SN65HVS883 must operate reliably in harsh industrial environments. At a system level, the device is tested
according to several international electromagnetic compatibility (EMC) standards.
In addition to the device internal ESD structures, external protection circuitry, such as the one in Figure 17, can
be used to absorb as much energy from burst- and surge-transients as possible.
CC
RS
VSUP = 24 V
DRP
V 24
D TS
CHV
DZ
CC
CB
CC
SN65HVS883
RIN
INx
IP0 – IP7
CIN
0V
FGND
CHV
FE
Copyright © 2016, Texas Instruments Incorporated
Figure 17. Typical EMC Protection Circuitry for Supply and Signal Inputs
Table 3. Components
DESIGNATOR
DESCRIPTION
DTS
39 V Transient Voltage Suppressor: SM15T39CA
DRP
Super Rectifier: BYM10-1000,
or General Purpose rectifier: 1N4007
DZ
33 V – 36 V fast Zener Diode, Z2SMB36
RS
56 Ω, 1/3 W MELF Resistor
RIN
1.2 kΩ, 1/4 W MELF Resistor
CIN
22 nF, 60 V Ceramic Capacitor
CHV
4.7 nF, 2 kV Ceramic Capacitor
CC
n x 220 nF, 60 V Ceramic Capacitors
CB
1 µF - 10 µF, 60 V Ceramic Capacitor
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9.1.2 Input Channel Switching Characteristics
The input stage of the SN65HVS883 is so designed, that for an input resistor RIN = 1.2 kΩ the trip point for
signalling an ON-condition is at 9.4 V at 3.6 mA. This trip point satisfies the switching requirements of IEC611312 Type 1 and Type 3 switches.
Type 2
Type 1
30
30
25
VIN (V)
ON
20
30
15
10
5
25
ON
20
VIN (V)
25
VIN (V)
Type 3
15
10
5
OFF
0
–30
5
10
IIN (mA)
10
5
OFF
0
–3
15
ON
20
15
0
5
10
15
OFF
0
–3
20
25
30
0
IIN (mA)
5
10
IIN (mA)
15
Figure 18. Switching Characteristics for IEC61131-2 Type 1, 2, and 3 Proximity Switches
For a Type 2 switch application, two inputs are connected in parallel. The current limiters then add to a total
maximum current of 7.2 mA. While the return-path (RE-pin), of one input might be used to drive an indicator
LED, the RE-pin of the other input channel should be connected to ground (FGND).
Paralleling input channels reduces the number of available input channels from an octal Type 1 or Type 3 input
to a quad Type 2 input device. Note, that in this configuration output data of an input channel is represented by
two shift register bits.
RIN
RIN
IN0
IP0
CIN
IN0
IP0
CIN
RE0
RE0
RIN
RIN
IN1
IP1
IP1
CIN
RE1
CIN
RE1
Figure 19. Paralleling Two Type 1 or Type 3 Inputs Into One Type 2 Input
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9.1.3 Digital Interface Timing
The digital interface of the SN65HVS883 is SPI compatible and interfaces, isolated or non-isolated, to a wide
variety of standard micro controllers.
SN65HVS883
SIP
IP7
SERIALIZER
IP0
HOST
CONTROLLER
ISO7241
LD
OUTA
INA
CE
OUTB
INB
CLK
OUTC
INC
SOP
IND
LOAD
STE
SCLK
OUTD
SOMI
Figure 20. Simple Isolation of the Shift Register Interface
Upon a low-level at the load input, LD, the information of the field inputs, IP0 to IP7 is latched into the shift
register. Taking LD high again blocks the parallel inputs of the shift register from the field inputs. A low-level at
the clock-enable input, CE, enables the clock signal, CLK, to serially shift the data to the serial output, SOP. Data
is clocked into the shift register at the rising edge of CLK and out of the shift register on the falling edge of CLK.
Thus after eight consecutive clock cycles all field input data have been clocked out of the shift register and the
information of the serial input, SIP, appears at the serial output, SOP.
The CE signal should only be transitioned low while the CLK signal is low which ensures that a rising edge of
CLK occurs before a falling edge of CLK. This shifts the data into and through the shift register up until the final
register before the first bit that was loaded into the final register is shifted out the serial output, SOP. If a falling
edge of CLK is seen first following the transition of CE to low, the final register outputs the first bit, IP0, on the
serial output, SOP, before shifting the rest of the bits through the shift register. The previous value of the second
to last register prior to the LD event will then be shifted into the final register on the next rising CLK edge and
output on the serial output, SOP, before the next valid bit, IP1, is output on the serial output, SOP. This appears
as an erroneous bit in the serial data. Also, depending on how many falling CLK edges were seen before the CE
signal is transitioned back high, the final bit, IP7, may not get shifted out of the shift register.
CLK
CE
SIP
high
LD
PIP0-PIP6
PIP7
SOP
don’t care
IP7
Inhibit
IP6
IP5
IP4
IP3
IP2
IP1
IP0
SIP
Serial shift
Figure 21. Interface Timing for Parallel-Load and Serial-Shift Operation of the Shift Register
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9.1.4 Cascading for High Channel Count Input Modules
Designing high-channel count modules require cascading multiple SN65HVS883 devices. Simply connect the
serial output (SOP) of a leading device with the serial input (SIP) of a following device without changing the
processor interface.
HOST
CONTROLLER
ISO7241
4 X SN65HVS883
OUTA
INA
LOAD
OUTB
INB
STE
OUTC
INC
CLK
SCLK
SOMI
SOP
OUTD
IP7
IP0
SERIALIZER
IP7
IP0
CE
LD
SIP
SOP
CE
CLK
LD
SIP
CLK
SOP
SERIALIZER
IP7
IP0
SERIALIZER
IP7
IP0
SERIALIZER
CE
LD
SIP
CLK
SOP
LD
CE
SIP
IND
Figure 22. Cascading Four SN65HVS883 for a 32-Channel Input Module
NOTE
When daisy-chaining multiple devices, the maximum operating rate (CLK pulse width) may
need to be restricted in order to maintain minimum set-up/hold timing relationships
between the serial data (SIP/SOP) and the CLK line.
9.2 Typical Application
SM15T39CA
5V
24 V
5 V-ISO
(Logic) 24 V1
SM15T39A
(Sensors) 24 V2
Isolated
DC / DC
220 nF
100 V
220 nF
100 V
4.7 nF
2 kV
Power
Supply 0 V
4.7 nF
2 kV
GND1
GND2
0 V-ISO
4.7 nF
2 kV
56 Ω
MELF
FE
220 nF
100 V
Srew Terminals
BYM10-1000
Z2SMB36
2.2 mF
60 V
1.2 kW
MELF
220 nF
60 V
22 nF
100 V
S0
5VOP
IP0
CE
VCC2
RE0
SIP
EN2
EN1
VCC
LD
OUTA
INA
LOAD
CLK
OUTB
INB
SCLK
ISO7242
VCC1
HOST
CONTROLLER
CHOK
INC
OUTC
INT
RE7
SOP
IND
OUTD
MISO
RLIM
DB0
GND2
GND1
DGND
FGND
DB1
IP7
22 nF
100 V
0.1 mF
V24
1.2 kW
MELF
S7
1 mF
SN65HVS883
24.9 kW
Copyright © 2016, Texas Instruments Incorporated
Figure 23. Typical Digital Input Module Application
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Typical Application (continued)
9.2.1 Design Requirements
The simplified schematic in Figure 23 demonstrates a typical application of the SN65HVS883 for sensing the
state of digital switches with 24-V high logic levels. In this application, a 5-V host controller must receive the state
of 8 switches as a serial input, while remaining isolated from the high voltage power supply.
9.2.2 Detailed Design Procedure
9.2.2.1 Input Stage
Selection of the current limiting resistor RLIM sets the input current limit ILIM for the device. Digital Inputs includes
necessary equations for choosing the limiting resistor.
The On/Off voltage thresholds at the device pin VTH(IP+) and VTH(IP-) are fixed to 5.2 V and 4.3 V respectively,
however the On/Off voltage thresholds of the field input VTH(IN+) and VTH(IN-) are determined by the value of the
series resistor RIN placed between the field input and the device. The threshold voltage VTH(IN+) is determined
with the following equation:
VTH(IN + ) = I IN ´ R IN + VTH(IP + )
(3)
Substituting Equation 1 and solving for RIN produces an equation for RIN given a desired on-threshold.
R IN =
(VTH(IN + ) - 5.2V) ´ R LIM
90V
(4)
The following equation can be used to calculate the off-threshold voltage given a value for RIN
VTH(IN - ) =
90V ´ R IN
+ VTH(IP - )
R LIM
(5)
Figure 24 contains an example input characteristic:
30
25
VIN (V)
20
15
10
ON = 8. 2 V
OFF = 7.3V
5
0
0
0.5
1
1.5
2
2.5
3
I IN (mA)
Figure 24. SN65HVS883 Example Input Characteristic
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Typical Application (continued)
9.2.2.2 Setting Debounce Time
The logic signals at the DB0 and DB1 pins determine the denounce times for the device according to the table in
section 6.5. The DB0 and DB1 pins are internally pulled high. Connecting the pins to GND in different
configurations allows for selection of 0, 1, or 3 ms debounce times. In noisy environments, it is recommended
that unused DB pins should be connected externally to a 5 V supply.
9.2.2.3 Example: High-Voltage Sensing Application
For the high-voltage sensing application in Figure 23, inputs from each switch (S0-S7) are connected to the 8
parallel inputs (IP0-IP7) of the SN65HVS883 through 1.2 kΩ MELF resistors. Small capacitors (22 nF) are tied to
ground at each input to provide noise protection for the signals. A resistor is added between the RLIM pin and
GND to provide a device current limit according to the equation ILIM = 90 V / RLIM. In this example, with a 24.9 kΩ
resistor, the current limit for the device is set to 3.6 mA. LEDs are placed between pins RE0-RE7 to allow for
external status observation of the parallel inputs. Finally the SN65HVS883 is connected through a digital isolation
device to the host controller to provide galvanic isolation to the external interfaces and to allow for
communication between the 5 V SN65HVS883 logic and the 5-V host controller. The host controller manages
mode switching and clocking of the SN65HVS883 through the digital isolation device.
9.2.3 Application Curve
5 V/div
The application traces acquired in Figure 25 demonstrates the typical behavior of the SN65HVD883 when in shift
mode (Load Pulse Input pulled high and Clock Enable Input pulled low). Channel 1 shows the SIP input, Channel
2 shows the CLK input, and Channel 3 shows the SOP output.
500 ns/div
Figure 25. SN65HVS883 Serial Input and Output Timing
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10 Power Supply Recommendations
The SN65HVS883 operates within a recommended supply voltage range from 4.5 V to 5.5 V. A 0.1 µF or larger
capacitor should be placed between VCC and ground to improve power supply noise immunity. A current limiting
resistor can be used to reduce overall power consumption as described in Digital Inputs. The high voltage
parallel field inputs can accept voltages ranging from 0 V to 34 V, however all other inputs must remain between
0 V to 5 V. Refer to the Recommended Operating Conditions table for more detailed voltage suggestions. High
voltage field inputs should be buffered as shown in Figure 23 to improve input noise immunity.
11 Layout
11.1 Layout Guidelines
1. Place series MELF resistors between the field inputs and the device input pins.
2. Place small ~22 nF capacitors close to the field input pins to reduce noise.
3. Place a supply buffering 0.1-µF capacitor around as close to the VCC pin as possible.
11.2 Layout Example
High
Voltage
Parallel
Inputs
1
2
R
C
R
C
R
C
R
C
R
C
R
C
R
C
R
SN65HVD883
Isolator
MCU
R
C
C
3
C
Isolated
DC-DC
Via to ground
Via to VCC 5V
Via to VCC 24V
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12 Device and Documentation Support
12.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN65HVS883PWP
ACTIVE
HTSSOP
PWP
28
50
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
HVS883
SN65HVS883PWPR
ACTIVE
HTSSOP
PWP
28
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
HVS883
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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