Product
Folder
Order
Now
Support &
Community
Tools &
Software
Technical
Documents
SN65LBC174A-EP
SLLS732A – OCTOBER 2006 – REVISED NOVEMBER 2019
SN65LBC174A-EP Quadruple RS-485 Differential Line Driver
1 Features
2 Applications
•
•
•
•
•
•
•
1
•
•
•
•
•
•
•
•
(1)
VID V62/07611
Designed for TIA/EIA-485, TIA/EIA-422, and ISO
8482 applications
Signaling rates up to 30 Mbps (1)
Propagation delay times < 11 ns
Low standby power consumption 1.5-mA max
Driver positive- and negative-current limiting
Power-up and power-down glitch free for lineinsertion applications
Thermal shutdown protection
Industry standard pinout, compatible with
SN75174, MC3487, DS96174, LTC487, and
MAX3042
Supports defense, aerospace, and medical
applications
– Controlled baseline
– One assembly and test site
– One fabrication site
– Available in military (–55°C to 125°C)
temperature range
– Extended product life cycle
– Extended product-change notification
– Product traceability
The signaling rate of a line is the number of voltage
transitions that are made per second, expressed in the unit
bits per second (bps).
Transmission at signaling rates up to 30 Mbps
Avionics, radar
GPS navigation for missiles
Industrial transportation
High-speed multipoint data transmission
applications in noisy environments
3 Description
The SN65LBC174A-EP is a quadruple differential line
driver with tri-state outputs, designed for TIA/EIA-485
(RS-485), TIA/EIA-422 (RS-422), and ISO 8482
applications.
This device is optimized for balanced multipoint bus
transmission at signaling rates up to 30-million bits
per second (Mbps). The transmission media may be
printed-circuit-board traces, backplanes, or cables.
The ultimate rate and distance of data transfer is
dependent upon the attenuation characteristics of the
media and the noise coupling to the environment.
Device Information(1)
PART NUMBER
SN65LBC174A-EP
PACKAGE
BODY SIZE (NOM)
SOIC (20)
7.50 × 12.80
SOIC (16)
7.50 × 10.30
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
1A
1Y
1Z
1,2EN
2A
2Y
2Z
3A
3Y
3Z
3,4EN
4A
4Y
4Z
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN65LBC174A-EP
SLLS732A – OCTOBER 2006 – REVISED NOVEMBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
5
7.1
7.2
7.3
7.4
7.5
7.6
7.7
5
5
5
5
6
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 9
Detailed Description ............................................ 14
9.1 Overview ................................................................. 14
9.2 Functional Block Diagram ....................................... 14
9.3 Feature Description................................................. 14
9.4 Device Functional Modes........................................ 14
10 Application and Implementation........................ 15
10.1 Application Information.......................................... 15
10.2 Typical Application ................................................ 15
11 Power Supply Recommendations ..................... 17
12 Layout................................................................... 18
12.1 Layout Guidelines ................................................. 18
12.2 Layout Example .................................................... 18
13 Device and Documentation Support ................. 19
13.1
13.2
13.3
13.4
13.5
Receiving Notification of Documentation Updates
Support Resources ...............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
19
19
19
19
14 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (December 2006) to Revision A
Page
•
Updated data sheet to superior standards ............................................................................................................................. 1
•
Added pinout drawing for 16-pin DW ..................................................................................................................................... 3
•
Added 16-pin DW and updated the Pin Functions table ........................................................................................................ 4
•
Added ESD value for 16-pin DW package ............................................................................................................................. 5
•
Added updated thermal metrics.............................................................................................................................................. 5
2
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: SN65LBC174A-EP
SN65LBC174A-EP
www.ti.com
SLLS732A – OCTOBER 2006 – REVISED NOVEMBER 2019
5 Description (continued)
Each driver features current limiting and thermal-shutdown circuitry, making it suitable for high-speed multipoint
applications in noisy environments. The device is designed using LinBiCMOS™ technology, facilitating low power
consumption and robustness.
The two enable (EN) inputs provide pair-wise driver enabling, or can be externally tied together to provide enable
control of all four drivers with one signal. When disabled or powered off, the driver outputs present a high
impedance to the bus for reduced system loading.
The SN65LBC174A-EP is characterized for operation over the temperature range of –55°C to 125°C.
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: SN65LBC174A-EP
3
SN65LBC174A-EP
SLLS732A – OCTOBER 2006 – REVISED NOVEMBER 2019
www.ti.com
6 Pin Configuration and Functions
DW
16-Pin SOIC
Top View
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
1A
1Y
1Z
1,2EN
2Z
2Y
2A
GND
DW
20-Pin SOIC
Top View
VCC
4A
4Y
4Z
3,4EN
3Z
3Y
3A
1
2
3
4
5
6
7
8
9
10
1A
1Y
NC
1Z
1,2EN
2Z
NC
2Y
2A
GND
20
19
18
17
16
15
14
13
12
11
VCC
4A
4Y
NC
4Z
3,4EN
3Z
NC
3Y
3A
Pin Functions
PIN
NAME
I/O
DESCRIPTION
16 PINS
20 PINS
1
1
1Y
2
2
Bus output
NC
—
3
No Connect Physically not connected in package
1Z
3
4
Bus output
1,2EN
4
5
Digital input Bus output port 1 and 2 driver enable
2Z
5
6
Bus output
NC
—
7
No Connect Physically not connected in package
2Y
6
8
Bus output
2A
7
9
Digital input Port 2 A data input
GND
8
10
3A
9
11
3Y
10
12
Bus output
NC
—
13
No Connect Physically not connected in package
3Z
11
14
Bus output
3,4EN
12
15
Digital input Bus output port 3 and 4 driver enable
4Z
13
16
Bus output
NC
—
17
No Connect Physically not connected in package
4Y
14
18
Bus output
4A
15
19
Digital input Port 4 A data input
VCC
16
20
1A
4
Digital input Port 1 A data input
Ground
Bus port 1 Y (complementary to 1 Z)
Bus port 1 Z (complementary to 1 Y)
Bus port 2 Z (complementary to 2 Y)
Bus port 2 Y (complementary to 2 Z)
Device ground
Digital input Port 3 A data input
VCC
Bus port 3 Y (complementary to 3 Z)
Bus port 3 Z (complementary to 3 Y)
Bus port 4 Z (complementary to 4 Y)
Bus port 4 Y (complementary to 4 Z)
Device power
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: SN65LBC174A-EP
SN65LBC174A-EP
www.ti.com
SLLS732A – OCTOBER 2006 – REVISED NOVEMBER 2019
7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VCC
VI
Tstg
MIN
MAX
Supply voltage (2)
–0.3
6
V
Voltage at any bus (dc)
–10
15
V
Voltage at any bus (transient pulse through 100 Ω, See Figure 14)
–30
30
V
Input voltage at any A or EN terminal
–0.5
VCC + 0.5
V
–65
150
°C
260
°C
Storage temperature
(3)
Lead temperature 1.6 mm (1/16 in) from case for 10 s
(1)
(2)
(3)
UNIT
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to GND.
Long-term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of
overall device life.
7.2 ESD Ratings
VALUE
V(ESD)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
(1)
(2)
Y, Z (20-pin DW)
±13,000
Y, Z (16-pin DW)
±10,000
All other pins
±5000
All pins
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
VCC
Supply voltage
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
Voltage at any bus terminal
Y, Z
–7
12
V
VIH
High-level input voltage
A, EN
2
VCC
V
VIL
Low-level input voltage
A, EN
0
0.8
V
TA
Output current
–60
60
mA
Operating free-air temperature
–55
125
°C
7.4 Thermal Information
SN65LBC174A-EP
THERMAL METRIC (1)
DW (SOIC)
UNIT
20 PINS
16 PINS
RθJA
Junction-to-ambient thermal resistance
61.3
60.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
26.2
24.3
°C/W
RθJB
Junction-to-board thermal resistance
29.3
26.1
°C/W
ψJT
Junction-to-top characterization parameter
4.9
4.1
°C/W
ψJB
Junction-to-board characterization parameter
28.8
25.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
n/a
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: SN65LBC174A-EP
5
SN65LBC174A-EP
SLLS732A – OCTOBER 2006 – REVISED NOVEMBER 2019
www.ti.com
7.5 Electrical Characteristics
over recommended operating conditions
PARAMETER
TEST CONDITIONS
MIN
–1.5
TYP (1) MAX
VIK
Input clamp voltage
II = –18 mA
VO
Open-circuit output voltage
Y or Z, No load
0
VCC
No load (open circuit)
3
VCC
|VOD(SS)|
Steady-state differential output
voltage magnitude (2)
ΔVOD(SS)
Change in steady-state differential output
voltage between logic states
See Figure 7
–0.1
VOC(SS)
Steady-state common-mode output
voltage
See Figure 9
2
ΔVOC(SS)
Change in steady-state common-mode
output voltage between logic states
See Figure 9
II
Input current
A, G, G
IOS
High-impedance-state output current
IO(OFF)
Output current with power off
ICC
(1)
(2)
6
Supply current
V
RL = 54 Ω, See Figure 7
0.8
1.6
2.5
With common-mode loading, See Figure 8
0.8
1.6
2.5
VTEST = –7 V to 12 V,
See Figure 13
VI = 0 V or VCC,
No load
V
V
0.1
V
2.8
V
–0.04
0.04
V
–70
70
μA
–200
200
mA
EN at 0 V
–50
50
μA
VCC = 0 V
–10
10
μA
VI = 0 V
Short-circuit output current
IOZ
–0.77
UNIT
VI = VCC
2.4
All drivers enabled
25
All drivers disabled
1.5
mA
All typical values are at VCC = 5 V and 25°C.
The minimum VOD may not fully comply with TIA/EIA-485-A at operating temperatures below 0°C. System designers should take the
possibility of lower output signal into account in determining the maximum signal transmission distance.
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: SN65LBC174A-EP
SN65LBC174A-EP
www.ti.com
SLLS732A – OCTOBER 2006 – REVISED NOVEMBER 2019
7.6 Switching Characteristics
over recommended operating conditions
PARAMETER
TEST CONDITIONS
tPLH
Propagation delay time, low- to high-level output
tPHL
Propagation delay time, high- to low-level output
tr
Differential output voltage rise time
tf
Differential output voltage fall time
tsk(p)
Pulse skew |tPLH – tPHL|
tsk(o)
Output skew (1)
tsk(pp) Part-to-part skew
tPZH
RL = 54 Ω, CL = 50 pF,
See Figure 10
tPHZ
Propagation delay time, high-level output to high
impedance
tPZL
Propagation delay time, high impedance to lowlevel output
tPLZ
(1)
(2)
TA= 25°C
4.0
TA= –55°C to 125°C
4.0
TA= 25°C
4.0
TA= –55°C to 125°C
4.0
TA= 25°C
3
TA= –55°C to 125°C
3
TA= 25°C
3
TA= –55°C to 125°C
3
(2)
Propagation delay time, high impedance to highlevel output
Propagation delay time, low-level output to high
impedance
MIN
TYP MAX UNIT
8
11
16
8
11
16
7.5
11
24
7.5
11
24
ns
ns
ns
ns
0.6
ns
2
ns
3
ns
25
ns
25
ns
30
ns
20
ns
See Figure 11
See Figure 12
Output skew (tsk(o)) is the magnitude of the time delay difference between the outputs of a single device with all of the inputs connected
together.
Part-to-part skew (tsk(pp)) is the magnitude of the difference in propagation delay times between any specified terminals of two devices
when both devices operate with the same input signals, the same supply voltages, at the same temperature, and have identical
packages and test circuits.
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: SN65LBC174A-EP
7
SN65LBC174A-EP
SLLS732A – OCTOBER 2006 – REVISED NOVEMBER 2019
www.ti.com
7.7 Typical Characteristics
2.5
3.5
VOD − Differential Output Voltage − V
VOD − Differential Output Voltage − V
4
3
VCC = 5.25 V
2.5
VCC = 5 V
2
1.5
VCC = 4.75 V
1
0.5
0
0
20
40
60
80
IO − Output Current − mA
VCC = 5 V
1.5
VCC = 4.75 V
1
0.5
0
−60
100
Figure 1. Differential Output Voltage vs Output Current
−40
−20
0
20
40
60
TA − Free-Air Temperature − °C
80
100
Figure 2. Differential Output Voltage vs Free-Air
Temperature
8.5
I CC − Supply Current (Four Channels) − mA
144
8
Propagation Delay Time − ns
VCC = 5.25 V
2
VCC = 5.25 V
7.5
VCC = 4.75 V
7
6.5
6
5.5
142
140
138
136
134
132
130
128
5
−40
−20
0
20
40
60
TA − Free-Air Temperature − °C
80
1
10
Signaling Rate − Mbps
RL = 54 Ω
Figure 3. Propagation Delay Time vs Free-Air Temperature
CL = 50 pF
100
(Each Channel)
Figure 4. Supply Current (Four Channels) vs Signaling Rate
VOD − Differential Output Voltage − V
3
2.5
2
1.5
1
0.5
0
0
0.5 1
1.5 2 2.5 3 3.5 4 4.5 5
VCC − Supply Voltage − V
5.5 6
RL = 54 Ω
RL = 54 Ω
Figure 5. Differential Output Voltage vs Supply Voltage
8
CL = 50 pF
Figure 6. Eye Pattern, Pseudo-Random Data at 30 Mbps
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: SN65LBC174A-EP
SN65LBC174A-EP
www.ti.com
SLLS732A – OCTOBER 2006 – REVISED NOVEMBER 2019
8 Parameter Measurement Information
IOY
Y
II
A
IOZ
Z
VOD
54 Ω
VOY
GND
VI
VOZ
Figure 7. Test Circuit, VOD Without Common-Mode Loading
375 Ω
Y
A
Input
60 Ω
VOD
Z
VTEST = −7 V to 12 V
375 Ω
VTEST
VI
Figure 8. Test Circuit, VOD With Common-Mode Loading
Y
27 Ω
A
Z
Signal
Generator(A)
27 Ω
CL = 50 pF(B)
50 Ω
VOC
PRR = 1 MHz, 50% duty cycle, tr < 6 ns, tf < 6 ns, ZO = 50 Ω
Includes probe and jig capacitance.
Figure 9. VOC Test Circuit
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: SN65LBC174A-EP
9
SN65LBC174A-EP
SLLS732A – OCTOBER 2006 – REVISED NOVEMBER 2019
www.ti.com
Parameter Measurement Information (continued)
Y
A
RL = 54 Ω
CL = 50 pF(B) VOD
Z
Signal
Generator(A)
50 Ω
3V
1.5 V
Input
0V
tPLH
tPHL
≈ 1.5 V
90%
0V
10%
Output
tr
≈ −1.5 V
tf
PRR = 1 MHz, 50% duty cycle, tr < 6 ns, tf < 6 ns, ZO = 50 Ω
Includes probe and jig capacitance.
Figure 10. Output Switching Test Circuit and Waveforms
10
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: SN65LBC174A-EP
SN65LBC174A-EP
www.ti.com
SLLS732A – OCTOBER 2006 – REVISED NOVEMBER 2019
Parameter Measurement Information (continued)
Y
S1
A
3 V or 0 V(C)
Output
Z
CL = 50 pF(B)
RL = 110 Ω
Input
EN
Signal
Generator(A)
50 Ω
3V
1.5 V
Input
0V
tPZH
0.5 V
VOH
2.3 V
0V
Output
tPHZ
PRR = 1 MHz, 50% duty cycle, tr < 6 ns, tf < 6 ns, ZO = 50 Ω
Includes probe and jig capacitance.
3 V if testing Y output, 0 V if testing Z output.
Figure 11. Enable Timing Test Circuit and Waveforms, TPZH and TPHZ
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: SN65LBC174A-EP
11
SN65LBC174A-EP
SLLS732A – OCTOBER 2006 – REVISED NOVEMBER 2019
www.ti.com
Parameter Measurement Information (continued)
5V
RL = 110 Ω
Y
S1
A
0 V or 3 V(C)
Output
Z
CL = 50 pF(B)
Input
EN
Signal
Generator(A)
50 Ω
3V
1.5 V
Input
0V
tPZL
tPLZ
5V
Output
2.3 V
VOL
0.5 V
PRR = 1 MHz, 50% duty cycle, tr < 6 ns, tf < 6 ns, ZO = 50 Ω
Includes probe and jig capacitance.
3 V if testing Y output, 0 V if testing Z output.
Figure 12. Enable Timing Test Circuit and Waveforms, TPZL and TPLZ
Y
IO
VI
Z
VTEST
Voltage Source
VTEST = −7 V to 12 V
Slew Rate ≤1.2 V/µs
Figure 13. Test Circuit, Short-Circuit Output Current
12
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: SN65LBC174A-EP
SN65LBC174A-EP
www.ti.com
SLLS732A – OCTOBER 2006 – REVISED NOVEMBER 2019
Parameter Measurement Information (continued)
Y
Z
100 Ω
VTEST
0V
15 µs
Pulse Generator
15-µs Duration,
1% Duty Cycle
−VTEST
1.5 ms
Figure 14. Test Circuit Waveform, Transient Overvoltage Test
Y or Z Output
A or EN Input
VCC
VCC
16 V
20 V
100 kΩ
16 V
1 kΩ
Input
Output
16 V
9V
17 V
16 V
Figure 15. Equivalent Input and Output Schematic Diagrams
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: SN65LBC174A-EP
13
SN65LBC174A-EP
SLLS732A – OCTOBER 2006 – REVISED NOVEMBER 2019
www.ti.com
9 Detailed Description
9.1 Overview
The SN65LBC174A-EP is a quadruple differential line driver with tri-state outputs, designed for TIA/EIA-485 (RS485), TIA/EIA-422 (RS-422), and ISO 8482 (Euro RS-485) applications. This device is optimized for balanced
multipoint bus communication at data rates up to and exceeding 30 million bits per second. The transmission
media may be twisted-pair cables, printed-circuit board traces, or backplanes. The ultimate rate and distance of
data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the
environment. The transmitter features ESD protection to 12 kV on driver outputs, making it suitable for highspeed multipoint data transmission applications in harsh environments. These devices are designed using
LinBiCMOS, facilitating low-power consumption and robustness. Two EN inputs provide pair-wise enable control,
or these can be tied together externally to enable all four drivers with the same signal.
9.2 Functional Block Diagram
1Y
1A
1Z
1,2EN
2Y
2A
2Z
3Y
3A
3Z
3,4EN
4Y
4A
4Z
9.3 Feature Description
The device can be configured using the enable inputs to enable driver pairs 1 and 2, and/or 3 and 4. The high
voltage or logic 1 on the EN pin enables the devices differential outputs.
9.4 Device Functional Modes
The drivers implemented in the RS-485 device can be configured using the EN logic pins set to enabled or
disabled. This allows users to transmit or idle the bus as desired.
Table 1. Function Table (1)
(Each Driver)
(1)
14
OUTPUTS
INPUT
A
ENABLE
G
Y
Z
L
H
L
H
H
H
H
L
OPEN
H
H
L
L
OPEN
L
H
H
OPEN
H
L
OPEN
OPEN
H
L
X
L
Z
Z
H = high level, L = low level, X = irrelevant,
Z = high impedance (off)
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: SN65LBC174A-EP
SN65LBC174A-EP
www.ti.com
SLLS732A – OCTOBER 2006 – REVISED NOVEMBER 2019
10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
Extending SPI operation over RS-485 link.
10.2 Typical Application
The following block diagram shows an MCU host connected via RS-485 to a SPI slave device. This device can
be an ADC, DAC, MCU, or other SPI slave peripheral.
MCU or DSP
SPI MASTER
SN65LBC174A-EP
SN65LBC175A-EP
PERIPHERIAL
SPI SLAVE
SPI MOSI
SPISIMO
GPIO or Tie
Enabled
GPIO or Tie
Enabled
SPI CS
SPI CS
SPICLK
SPI CLK
GPIO or Tie
Enabled 2
GPIO or Tie
Enabled 2
GPIO Optional
Handshaking
GPIO Optional
Handshaking
SPI MISO
SPISOMI
Copyright © 2016, Texas Instruments Incorporated
Figure 16. Typical Application Circuit, MCU Master to Slave Link Via Serial Peripheral Interface
10.2.1 Design Requirements
This application can be implemented using standard SPI protocol on DSP or MCU devices. The interface is
independent of the specific frame or data requirements of the host or slave device. An additional but not required
handshake bit is provided that can be used for customer purposes.
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: SN65LBC174A-EP
15
SN65LBC174A-EP
SLLS732A – OCTOBER 2006 – REVISED NOVEMBER 2019
www.ti.com
Typical Application (continued)
10.2.2 Detailed Design Procedure
The interface design requirements are fairly straight forward in this single source/destination scenario. Trace
lengths and cable lengths need to be matched to maximize SPI timing. If there is a benefit to put the interface to
sleep, GPIOs can be used to control the enable signals of the transmitter and receiver. If GPIOs are not
available, or constant uptime needed, both the enables on transmit and receive can be hard tied enabled. The
link shown can operate at up to 30 Mbps, well within the capability of most SPI links.
10.2.3 Application Curve
RL = 54 Ω
CL = 50 pF
Figure 17. Eye Pattern, Pseudo-Random Data at 30 Mbps
16
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: SN65LBC174A-EP
SN65LBC174A-EP
www.ti.com
SLLS732A – OCTOBER 2006 – REVISED NOVEMBER 2019
11 Power Supply Recommendations
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies.
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: SN65LBC174A-EP
17
SN65LBC174A-EP
SLLS732A – OCTOBER 2006 – REVISED NOVEMBER 2019
www.ti.com
12 Layout
12.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the
operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low-impedance
power sources local to the analog circuitry.
• Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as close to
the device as possible.
• Place termination resistor as close as possible to the input pins (if end point node).
• Keep trace lengths from input pins to bus as short as possible to reduce stub lengths and reflections on any
nodes that are not end points of bus.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as
opposed to in parallel with the noisy trace.
12.2 Layout Example
J
M
P
C
MCUDSP
Via to GND
Via to Vcc
SN65LBC174A-EP
J
M
P
Figure 18. Layout With PCB Recommendations
18
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: SN65LBC174A-EP
SN65LBC174A-EP
www.ti.com
SLLS732A – OCTOBER 2006 – REVISED NOVEMBER 2019
13 Device and Documentation Support
13.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.3 Trademarks
LinBiCMOS, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: SN65LBC174A-EP
19
SN65LBC174A-EP
SLLS732A – OCTOBER 2006 – REVISED NOVEMBER 2019
www.ti.com
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
20
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: SN65LBC174A-EP
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
(4/5)
(6)
65LBC174AM16DWREP
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
65LBC174EP
SN65LBC174AMDWREP
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
65LBC174EP
V62/07611-01XE
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
65LBC174EP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
