SN55LBC176, SN65LBC176, SN75LBC176
SLLS067I – AUGUST 1990 – REVISED OCTOBER 2022
SNx5LBC176 Differential Bus Transceivers
1 Features
2 Description
•
•
The SN55LBC176, SN65LBC176, SN65LBC176Q,
and SN75LBC176 differential bus transceivers
are monolithic, integrated circuits designed for
bidirectional data communication on multipoint bustransmission lines. They are designed for balanced
transmission lines and meet ANSI Standard
TIA/EIA−485−A (RS-485) and ISO 8482:1987(E).
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Bidirectional Transceiver
Meets or Exceeds the Requirements of
ANSI Standard TIA/EIA−485−A and
ISO 8482:1987(E)
High-Speed Low-Power LinBiCMOS™
Circuitry
Designed for High-Speed Operation in Both
Serial and Parallel Applications
Low Skew
Designed for Multipoint Transmission on
Long Bus Lines in Noisy Environments
Very Low Disabled Supply Current . . .
200 µA Maximum
Wide Positive and Negative Input/Output
Bus Voltage Ranges
Thermal-Shutdown Protection
Driver Positive-and Negative-Current
Limiting
Open-Circuit Failsafe Receiver Design
Receiver Input Sensitivity . . . ±200 mV Max
Receiver Input Hysteresis . . . 50 mV Typ
Operates From a Single 5-V Supply
Glitch-Free Power-Up and Power-Down
Protection
Available in Q-Temp Automotive
HighRel Automotive Applications
Configuration Control / Print Support
Qualification to Automotive Standards
The SN55LBC176, SN65LBC176, SN65LBC176Q,
and SN75LBC176 combine a 3-state, differential line
driver and a differential input line receiver, both of
which operate from a single 5-V power supply. The
driver and receiver have active-high and active-low
enables, respectively, which can externally connect
together to function as a direction control. The driver
differential outputs and the receiver differential inputs
connect internally to form a differential input/output
(I/O) bus port that is designed to offer minimum
loading to the bus whenever the driver is disabled
or VCC = 0. This port features wide positive and
negative common-mode voltage ranges, making the
device suitable for party-line applications. Low device
supply current can be achieved by disabling the driver
and the receiver.
Package Information
PART NUMBER
SN55LBC176
SN65LBC176
SN75LBC176
(1)
PACKAGE(1)
BODY SIZE (NOM)
LCCC (20)
8.89 mm x 8.89 mm
CDIP (8)
9.60 mm x 6.67 mm
SOIC (8)
4.90 mm x 3.91 mm
PDIP (8)
9.81 mm x 6.35 mm
SOIC (8)
4.90 mm x 3.91 mm
PDIP (8)
9.81 mm x 6.35 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
3
DE
4
D
2
RE
R
6
A
1
7
Bus
B
Figure 2-1. Logic Diagram (Positive Logic)
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN55LBC176, SN65LBC176, SN75LBC176
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SLLS067I – AUGUST 1990 – REVISED OCTOBER 2022
Table of Contents
1 Features............................................................................1
2 Description.......................................................................1
3 Revision History.............................................................. 2
4 Description (Continued)..................................................3
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 Recommended Operating Conditions.........................4
6.3 Thermal Information: SN55LBC176............................4
6.4 Thermal Information: SN65LBC176, SN75LBC176....5
6.5 Dissipation Ratings..................................................... 5
6.6 Driver Electrical Characteristics.................................. 5
6.7 Driver Switching Characteristics................................. 7
6.8 Receiver Electrical Characteristics............................. 8
6.9 Receiver Switching Characteristics.............................8
7 Parameter Measurement Information............................ 9
8 Detailed Description......................................................12
8.1 Functional Block Diagram......................................... 12
8.2 Device Functional Modes..........................................12
9 Device and Documentation Support............................14
9.1 Device Support......................................................... 14
9.2 Trademarks............................................................... 14
9.3 Electrostatic Discharge Caution................................15
9.4 Glossary....................................................................15
10 Mechanical, Packaging, and Orderable
Information.................................................................... 15
3 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (December 2010) to Revision I (October 2022)
Page
• Added Pin Configuration and Functions section, Thermal Information tables, Detailed Description section,
Device Functional Modes, Device and Documentation Support section, and Mechanical, Packaging, and
Orderable Information section ........................................................................................................................... 1
2
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4 Description (Continued)
These transceivers are suitable for ANSI Standard TIA/EIA−485 (RS-485) and ISO 8482 applications to the
extent that they are specified in the operating conditions and characteristics section of this data sheet. Certain
limits contained in TIA/EIA−485−A and ISO 8482:1987 (E) are not met or cannot be tested over the entire
military temperature range.
The SN55LBC176 is characterized for operation from –55°C to 125°C. The SN65LBC176 is characterized for
operation from –40°C to 85°C, and the SN65LBC176Q is characterized for operation from –40°C to 125°C. The
SN75LBC176 is characterized for operation from 0°C to 70°C.
5 Pin Configuration and Functions
D, JG, OR P PACKAGE
(TOP VIEW)
R
RE
DE
D
1
8
2
7
3
6
4
5
VCC
B
A
GND
NC
R
NC
VCC
NC
FK PACKAGE
(TOP VIEW)
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
NC
B
NC
A
NC
NC
D
NC
GND
NC
NC
RE
NC
DE
NC
NC – No internal connection
Table 5-1. Pin Functions
PIN
TYPE
DESCRIPTION
SOIC,PDIP,
CDIP
LCCC
R
1
2
O
Logic output RS485 data
RE
2
5
I
Receiver enable/disable
DE
3
7
I
Driver enable/disable
D
4
10
I
Logic input RS485 data
GND
5
12
-
Ground
A
6
15
I/O
RS485 bus pin;
Non-Inverting
B
7
17
I/O
RS485 bus pin;
Inverted
VCC
8
20
-
5V Supply Voltage
-
1,2,3,6,8,9,1
1,13,14,16,1
8,19
-
No Internal Connection
NAME
NC
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
7
V
Supply voltage, VCC (2)
Voltage range at any bus terminal
–10
15
V
Input voltage, VI (D, DE, R, or RE)
–0.3
VCC + 0.5
V
Receiver output current, IO
–10
10
mA
150
°C
Continuous total power dissipation
See Section 6.5
Storage temperature range, Tstg
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 6.2 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltage, are with respect to network ground terminal.
6.2 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC
Voltage at any bus terminal (separately or common mode), VI or VIC
High-level input voltage, VIH
D, DE, and RE
Low-level input voltage, VIL
D, DE, and RE
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
12
V
–7
2
Differential input voltage, VID (1)
V
Driver
High-level output current, IOH
Receiver
V
12
V
–60
mA
–400
μA
Driver
Low-level output current, IOL
60
Receiver
8
Junction temperature, TJ
140
Operating free-air temperature, TA
SN55LBC176
−55
SN65LBC176
–40
85
SN65LBC176Q
–40
125
0
70
SN75LBC176
(1)
0.8
–12
mA
°C
125
°C
Differential input /output bus voltage is measured at the noninverting terminal A with respect to the inverting terminal B.
6.3 Thermal Information: SN55LBC176
THERMAL METRIC(1)
4
FK
JG
20 PINS
8 PINS
RθJA
Junction-to-ambient thermal resistance
61.6
99.5
RθJC(top)
Junction-to-case (top) thermal resistance
36.8
51.5
RθJB
Junction-to-board thermal resistance
36.1
86.5
ψJT
Junction-to-top characterization parameter
31.0
23.7
ψJB
Junction-to-board characterization parameter
36.0
80.2
RθJC(bot)
Junction-to-case (bottom) thermal resistance
4.2
11.6
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UNIT
°C/W
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6.4 Thermal Information: SN65LBC176, SN75LBC176
D
THERMAL METRIC(1)
P
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
116.7
65.6
RθJC(top)
Junction-to-case (top) thermal resistance
56.3
54.6
RθJB
Junction-to-board thermal resistance
63.4
42.1
ψJT
Junction-to-top characterization parameter
8.8
22.9
ψJB
Junction-to-board characterization parameter
62.6
41.6
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
n/a
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Dissipation Ratings
PACKAGE
D
(1)
(2)
THERMAL
MODEL
TA < 25°C
POWER RATING
DERATING
FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
TA = 110°C
POWER RATING
Low K(1)
526 mW
5.0 mW/°C
301 mW
226 mW
—
K(2)
882 mW
8.4 mW/°C
504 mW
378 mW
—
P
High
840 mW
8.0 mW/°C
480 mW
360 mW
—
JG
1050 mW
8.4 mW/°C
672 mW
546 mW
210 mW
FK
1375 mW
11.0 mW/°C
880 mW
715 mW
440 mW
In accordance with the low effective thermal conductivity metric definitions of EIA/JESD 51−3.
In accordance with the high effective thermal conductivity metric definitions of EIA/JESD 51−7.
6.6 Driver Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
Input clamp voltage
II = –18 mA
VO
Output voltage
IO = 0
0
6
V
| VOD1 |
Differential output voltage
IO = 0
1.5
6
V
| VOD2 |
RL = 54 Ω,
Differential output voltage
See
| VOD3 |
See
Δ| VOD |
Change in magnitude of
differential output voltage (1)
VOC
Common-mode output voltage
Δ| VOC |
Change in magnitude
of common-mode output
voltage(1)
IO
Output current
See Figure 7-1,
(2)
Vtest = – 7 V to 12 V,
Differential output voltage
–1.5
UNIT
VIK
See Figure 2,
(2)
RL = 54 Ω or 100 Ω,
Output disabled,
See (3)
V
55LBC176,
65LBC176,
65LBC176Q
1.1
75LBC176
1.5
55LBC176,
65LBC176,
65LBC176Q
1.1
75LBC176
1.5
5
–0.2
0.2
V
–1
3
V
–0.2
0.2
V
See Figure 7-1
VO = 12 V
VO = –7 V
V
5
V
1
–0.8
mA
IIH
High-level input current
VI = 2.4 V
–100
µA
IIL
Low-level input current
VI = 0.4 V
–100
µA
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6.6 Driver Electrical Characteristics (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
IOS
Short circuit output current
TEST CONDITIONS
MIN
VO = −7 V
–250
VO = 0
–150
VO = VCC
Receiver disabled
and driver enabled
ICC
(1)
(2)
(3)
6
Supply current
UNIT
mA
250
VO = 12 V
VI = 0 or VCC,
No load
MAX
55LBC176,
65LBC176Q
1.75
65LBC176,
75LBC176
1.5
55LBC176,
Receiver and driver 65LBC176Q
disabled
65LBC176,
75LBC176
mA
0.25
0.2
Δ| VOD | | and Δ | VOC | are the changes in magnitude of VOD and VOC, respectively, that occur when the input changes from a high
level to a low level.
This device meets the VOD requirements of TIA/EIA−485−A above 0°C only.
This applies for both power on and off; refer to TIA/EIA−485−A for exact conditions.
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6.7 Driver Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature
PARAMETER
TEST CONDITIONS
SN55LBC176
SN65LBC176Q
MIN
td(OD)
Differential output delay time
tt(OD)
Differential output transition time
tsk(p)
Pulse skew (|td(ODH) – td(ODL)|)
tPZH
8
RL = 54 Ω,
See Figure
7-3
CL = 50 pF,
Output enable time to high level
RL = 110 Ω,
See Figure
7-4
tPZL
Output enable time to low level
RL = 110 Ω,
tPHZ
tPLZ
(1)
TYP
SN65LBC176
SN75LBC176
MAX
MIN
31
8
12
TYP(1)
UNIT
MAX
25
12
0
ns
6
ns
65
35
ns
See Figure
7-5
65
35
ns
Output disable time from high level RL = 110 Ω,
See Figure
7-4
105
60
ns
Output disable time from low level
See Figure
7-5
105
35
ns
RL = 110 Ω,
6
ns
All typical values are at VCC = 5 V, TA = 25°C.
Table 6-1. Driver Symbol Equivalents
DATA SHEET PARAMETER
RS-485
VO
Voa, Vob
| VOD1 |
Vo
| VOD2 |
Vt (RL = 54 Ω)
| VOD |
Vt (test termination
measurement 2)
Δ | VOD |
|| Vt | – | V t||
VOC
| Vos |
Δ | VOC |
| Vos – V os |
IOS
None
IO
Iia, Iib
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6.8 Receiver Electrical Characteristics
over recommended ranges of common-mode input voltage, supply voltage, and operating free-air temperature (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input
threshold voltage
VO = 2.7 V,
IO = –0.4 mA
VIT –
Negative-going input
threshold voltage
VO = 0.5 V,
IO = 8 mA
Vhys
Hysteresis voltage (VIT+ –
VIT–) (see Figure 7-4)
VIK
Enable-input clamp voltage
MIN
TYP(1)
MAX
0.2
–0.2(2)
VID = 200 mV,
IOH = –400 µA,
V
V
50
II = –18 mA
UNIT
mV
–1.5
V
2.7
V
VOH
High level output voltage
VOL
Low level output voltage
IOZ
High-impedance-state
output current
VO = 0.4 V to 2.4 V
II
Line input current
Other input = 0 V,
See (3)
IIH
High-level enable-input
current
VIH = 2.7 V
–100
µA
IIL
Low-level enable-input
current
VIL = 0.4 V
–100
µA
rI
Input resistance
12
kΩ
See Figure 7-6
VID = −200 mV,
IOL = 8 mA,
See Figure 7-6
–20
Supply current
VI = 0 or VCC,
No load
20
µA
1
VI = –7 V
–0.8
Receiver and
driver disabled
3.9
SN55LBC176,
SN65LBC176,
SN65LBC176Q
0.25
SN75LBC176
(1)
(2)
(3)
V
VI = 12 V
Receiver enabled
and driver disabled
ICC
0.45
mA
mA
mA
0.2
All typical values are at VCC = 5 V, TA = 25°C.
The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet.
This applies for both power on and power off. Refer to ANSI Standard RS-485 for exact conditions.
6.9 Receiver Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature, CL = 15 pF
PARAMETER
SN55LBC176
SN65LBC176Q
SN65LBC176
SN75LBC176
TYP(1)
UNIT
MIN
MAX
MIN
MAX
11
37
11
33
ns
11
37
11
33
ns
tPLH
Propagation delay time, low- to
high-level single-ended output
tPHL
Propagation delay time, high- to
low-level single-ended output
tsk(p)
Pulse skew (| tPLH – tPHL|)
10
6
ns
tPZH
Output enable time to high level
35
35
ns
tPZL
Output enable time to low level
35
30
ns
tPHZ
Output disable time from high level
35
35
ns
tPLZ
Output disable time from low level
35
30
ns
(1)
8
TEST CONDITIONS
VID = –1.5 V to 1.5 V,
See Figure 7-7
See Figure 7-8
See Figure 7-8
3
All typical values are at VCC = 5 V, TA = 25°C.
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7 Parameter Measurement Information
RL
2
VOD2
RL
VOC
2
Figure 7-1. Driver VOD and VOC
375 Ω
VOD3
60 Ω
Vtest
375 Ω
Figure 7-2. Driver VOD3
3V
Input
Generator
(see Note A)
RL = 54 Ω
0V
td(ODH)
Output
50 Ω
Output
3V
1.5 V
1.5 V
CL = 50 pF
(see Note B)
td(ODL)
90%
50%
10%
tt(OD)
TEST CIRCUIT
≈ 2.5 V
50%
≈− 2.5 V
tt(OD)
VOLTAGE WAVEFORMS
Figure 7-3. Driver Test Circuit and Voltage Waveforms
Output
S1
3V
Input
1.5 V
1.5 V
0 V or 3 V
Generator
(see Note A)
CL = 50 pF
(see Note B)
50 Ω
TEST CIRCUIT
tPZH
RL = 110 Ω
0V
0.5 V
VOH
Output
2.3 V
tPHZ
Voff ≈ 0 V
VOLTAGE WAVEFORMS
Figure 7-4. Driver Test Circuit and Voltage Waveforms
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5V
3V
Input
RL = 110 Ω
S1
1.5 V
1.5 V
0V
Output
3 V or 0 V
tPZL
tPLZ
Generator
(see Note A)
CL = 50 pF
(see Note B)
50 Ω
2.3 V
Output
5V
0.5 V
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
Figure 7-5. Driver Test Circuit and Voltage Waveforms
A.
B.
C.
D.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO =
50 Ω.
CL includes probe and jig capacitance.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO =
50 Ω.
CL includes probe and jig capacitance.
VID
VOH
VOL
+ IOL
−I OH
Figure 7-6. Receiver VOH and VOL
3V
Input
Generator
(see Note A)
1.5 V
1.5 V
Output
51 Ω
1.5 V
0V
CL = 15 pF
(see Note B)
0V
tPHL
tPLH
Output
VOH
1.3 V
1.3 V
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
Figure 7-7. Receiver Test Circuit and Voltage Waveforms
10
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S1
1.5 V
2 kΩ
−1.5 V
S2
5V
CL = 15 pF
(see Note B)
Generator
(see Note A)
5 kΩ
1N916 or Equivalent
50 Ω
S3
TEST CIRCUIT
1.5 V
Input
3V
S1 to 1.5 V
S2 Open
S3 Closed
0V
Input
1.5 V
tPZH
3V
S1 to −1.5 V
S2 Closed
S3 Opened
0V
tPZL
VOH
≈ 4.5 V
1.5 V
Output
Output
0V
1.5 V
VOL
3V
S1 to 1.5 V
S2 Closed
S3 Closed
0V
1.5 V
Input
Input
tPHZ
3V
S1 to −1.5 V
S2 Closed
S3 Closed
0V
1.5 V
tPLZ
≈ 1.3 V
VOH
Output
0.5 V
Output
0.5 V
VOL
≈ 1.3 V
VOLTAGE WAVEFORMS
A.
B.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO =
50 Ω.
CL includes probe and jig capacitance.
Figure 7-8. Receiver Test Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Functional Block Diagram
3
DE
4
D
2
RE
R
6
A
1
7
Bus
B
Figure 8-1. Logic Diagram (Positive Logic)
DE
3
EN1
2
EN2
RE
6
D
R
A.
A
1
4
7
1
1
B
2
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Figure 8-2. Logic Symbol(A)
8.2 Device Functional Modes
Table 8-1. Driver Function Tables(1)
DRIVER
(1)
OUTPUTS
INPUT
D
ENABLE
DE
A
H
H
H
L
L
H
L
H
X
L
Z
Z
B
H = high level, L = low level, ? = indeterminate, X = irrelevant, Z = high impedance (off)
Table 8-2. Receiver Function Tables(1)
RECEIVER
12
DIFFERENTIAL INPUTS
VID = VIA – VIB
ENABLE
RE
OUTPUTS
R
VID ≥ 0.2 V
L
H
–0.2 V < VID < 0.2 V
L
?
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VID ≤ –0.2 V
L
L
X
H
Z
Open
L
H
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: SN55LBC176 SN65LBC176 SN75LBC176
SN55LBC176, SN65LBC176, SN75LBC176
www.ti.com
SLLS067I – AUGUST 1990 – REVISED OCTOBER 2022
EQUIVALENT OF D, RE, and
DE INPUTS
TYPICAL OF A AND B I/O PORTS
TYPICAL OF RECEIVER OUTPUT
VCC
VCC
VCC
100 kΩ NOM
A Port Only
3 kΩ
NOM
A or B
Output
Input
18 kΩ
NOM
100 kΩ NOM
B Port Only
1.1 kΩ
NOM
Figure 8-3. Schematics of Inputs and Outputs
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: SN55LBC176 SN65LBC176 SN75LBC176
Submit Document Feedback
13
SN55LBC176, SN65LBC176, SN75LBC176
www.ti.com
SLLS067I – AUGUST 1990 – REVISED OCTOBER 2022
9 Device and Documentation Support
9.1 Device Support
9.1.1 Thermal Characteristics of IC Packages
θJA (Junction-to-Ambient Thermal Resistance) is defined as the difference in junction temperature to ambient
temperature divided by the operating power.
θJA is NOT a constant and is a strong function of
• the PCB design (50% variation)
• altitude (20% variation)
• device power (5% variation)
θJA can be used to compare the thermal performance of packages if the specific test conditions are defined and
used. Standardized testing includes specification of PCB construction, test chamber volume, sensor locations,
and the thermal characteristics of holding fixtures. θJA is often misused when it is used to calculate junction
temperatures for other installations.
TI uses two test PCBs as defined by JEDEC specifications. The low-k board gives average in-use condition
thermal performance and consists of a single trace layer 25 mm long and 2-oz thick copper. The high-k board
gives best case in-use condition and consists of two 1-oz buried power planes with a single trace layer 25 mm
long with 2-oz thick copper. A 4% to 50% difference in θJA can be measured between these two test cards.
θJC (Junction-to-Case Thermal Resistance) is defined as difference in junction temperature to case divided by
the operating power. It is measured by putting the mounted package up against a copper block cold plate to
force heat to flow from die, through the mold compound into the copper block.
θJC is a useful thermal characteristic when a heatsink is applied to package. It is NOT a useful characteristic
to predict junction temperature as it provides pessimistic numbers if the case temperature is measured in a
non-standard system and junction temperatures are backed out. It can be used with θJB in 1-dimensional thermal
simulation of a package system.
θJB (Junction-to-Board Thermal Resistance) is defined to be the difference in the junction temperature and the
PCB temperature at the center of the package (closest to the die) when the PCB is clamped in a cold−plate
structure. θJB is only defined for the high-k test card.
θJB provides an overall thermal resistance between the die and the PCB. It includes a bit of the PCB thermal
resistance (especially for BGA’s with thermal balls) and can be used for simple 1-dimensional network analysis
of package system (see Figure 9-1).
Ambient Node
CA
Calculated
Surface Node
JC
Calculated/Measured
Junction
JB
Calculated/Measured
PC Board
Figure 9-1. Thermal Resistance
9.2 Trademarks
LinBiCMOS™ is a trademark of Texas Instruments Incorporated.
All trademarks are the property of their respective owners.
14
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Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: SN55LBC176 SN65LBC176 SN75LBC176
SN55LBC176, SN65LBC176, SN75LBC176
www.ti.com
SLLS067I – AUGUST 1990 – REVISED OCTOBER 2022
9.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.4 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: SN55LBC176 SN65LBC176 SN75LBC176
Submit Document Feedback
15
PACKAGE OPTION ADDENDUM
www.ti.com
18-Nov-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
5962-9318301Q2A
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
59629318301Q2A
SNJ55
LBC176FK
5962-9318301QPA
ACTIVE
CDIP
JG
8
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
9318301QPA
SNJ55LBC176
SN65LBC176D
LIFEBUY
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
6LB176
SN65LBC176DR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
6LB176
Samples
SN65LBC176DRG4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
6LB176
Samples
SN65LBC176P
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
65LBC176
Samples
SN65LBC176QD
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LB176Q
Samples
SN65LBC176QDG4
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LB176Q
Samples
SN65LBC176QDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LB176Q
Samples
SN65LBC176QDRG4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
(J176Q1, LB176Q)
Samples
SN75LBC176D
LIFEBUY
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
7LB176
SN75LBC176DR
LIFEBUY
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
7LB176
SN75LBC176DRG4
LIFEBUY
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
7LB176
SN75LBC176P
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
75LBC176
SNJ55LBC176FK
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
59629318301Q2A
SNJ55
LBC176FK
SNJ55LBC176JG
ACTIVE
CDIP
JG
8
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
9318301QPA
SNJ55LBC176
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
Addendum-Page 1
Samples
Samples
Samples
Samples
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
18-Nov-2022
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of