SN65LBC182PG4


 SLLS500A − MAY 2001 − REVISED MARCH 2005    

  FEATURES D One-Fourth Unit Load Allows up to 128 D D D D D D D D D Devices on a Bus ESD Protection for Bus Terminals: − ±15-kV Human Body Model − ±8-kV IEC61000-4-2, Contact Discharge − ±15-kV IEC61000-4-2, Air-Gap Discharge Meets or Exceeds the Requirements of ANSI Standard TIA/EIA-485-A and ISO 8482: 1987(E) Controlled Driver Output-Voltage Slew Rates Allow Longer Cable Stub Lengths Designed for Signaling Rates† Up to 250-kbps Low Disabled Supply Current . . . 250 µA Max Thermal Shutdown Protection Open-Circuit Fail-Safe Receiver Design Receiver Input Hysteresis . . . 70 mV Typ Glitch-Free Power-Up and Power-Down Protection APPLICATIONS D Utility Meters D Industrial Process Control D Building Automation DESCRIPTION The SN65LBC182 and SN75LBC182 are differential data line transceivers with a high level of ESD protection in the trade-standard footprint of the SN75176. They are designed for balanced transmission lines and meet ANSI standard TIA/EIA-485-A and ISO 8482. The SN65LBC182 and SN75LBC182 combine a 3-state, differential line driver and differential input line receiver, both of which operate from a single 5-V power supply. The driver and receiver have active-high and active-low enables, respectively, which can be externally connected together to function as a direction control. The driver outputs and the receiver inputs connect internally to form a differential input/output (I/O) bus port that is designed to offer minimum loading to the bus. This port operates over a wide range of common-mode voltage, making the device suitable for party-line applications. The device also includes additional features for party-line data buses in electrically noisy environment applications such as industrial process control or power inverters. The SN75LBC182 and SN65LBC182 bus pins also exhibit a high input resistance equivalent to one-fourth unit load allowing connection of up to 128 similar devices on the bus. The high ESD tolerance protects the device for cabled connections. (For an even higher level of protection, see the SN65/75LBC184, literature number SLLS236.) The differential driver design incorporates slew-rate-controlled outputs sufficient to transmit data up to 250 kbps. Slew-rate control allows longer unterminated cable runs and longer stub lengths from the main backbone than possible with uncontrolled voltage transitions. The receiver design provides a fail-safe output of a high level when the inputs are left floating (open circuit). Very low device supply current can be achieved by disabling the driver and the receiver. The SN65LBC182 is characterized for operation from −40°C to 85°C, and the SN75LBC182 is characterized for operation from 0°C to 70°C. functional block diagram DE D RE R 3 6 4 7 2 A B 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. †The signaling rate of a line, is the number of voltage transitions that are made per second expressed in the units bps (bits per second).      !"#   $"%&! '#( '"! !  $#!! $# )# #  #* "# '' +,( '"! $!#- '#  #!#&, !&"'# #-  && $##( Copyright  2001, Texas Instruments Incorporated www.ti.com 1 

 SLLS500A − MAY 2001 − REVISED MARCH 2005 schematic of inputs and outputs SN65LBC182D (Marked as 6LB182) SN75LBC182D (Marked as 7LB182) SN65LBC182P (Marked as 65LBC182) SN75LBC182P (Marked as 75LBC182) (TOP VIEW) R RE DE D 1 2 8 3 7 6 4 5 VCC VCC B A GND A Port Only 16 kΩ 12 µA Nominal 72 kΩ A or B I/O 16 kΩ B Port Only 12 µA Nominal Function Tables DRIVER INPUT D ENABLE DE H H OUTPUTS A B H L L H L H X L Z Z Open H H L RECEIVER DIFFERENTIAL INPUTS ENABLE RE OUTPUT R VID ≥ 0.2 V -0.2V < VID < 0.2 V VID ≤ -0.2 V X Open L L L H L H ? L Z H AVAILABLE OPTIONS PACKAGE TA PLASTIC SMALL-OUTLINE† (JEDEC MS-012) PLASTIC DUAL-IN-LINE PACKAGE (JEDEC MS-001) 0°C to 70°C SN75LBC182D SN75LBC182P −40°C to 85°C SN65LBC182D SN65LBC182P † Add R suffix for taped and reel. † For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. 2 www.ti.com 

 SLLS500A − MAY 2001 − REVISED MARCH 2005 absolute maximum ratings† over operating free−air temperature range unless otherwise noted Supply voltage range, (see Note 1) VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Voltage range at any bus terminal (A or B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −15 V to 15 V Input voltage, VI (D, DE, R or RE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V Receiver output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Electrostatic discharge: Human body model (see Note 2) A, B, GND . . . . . . . . . . . . . . . . . . . . . . 15 kV All pins . . . . . . . . . . . . . . . . . . . . . . . . . . 3 kV Contact discharge (IEC61000-4-2) A, B, GND . . . . . . . . . . . . . . . . . . . . . . . 8 kV Air discharge (IEC61000-4-2) A, B, GND . . . . . . . . . . . . . . . . . . . . . . 15 kV Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. 2. Tested in accordance with JEDEC Standard 22, Test Method A114-A. DISSIPATION RATING TABLE TA ≤ 25°C POWER RATING DERATING FACTOR‡ ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING D 725 mW 5.8 mW/°C 464 mW 377 mW P 1150 mW 9.2 mW/°C 736 mW PACKAGE 598 mW ‡ This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. NOTE: The maximum operating junction temperature is internally limited. Use the dissipation rating table to operate below this temperature recommended operating conditions Supply voltage, VCC Voltage at any bus I/O terminal (separately or common mode) VI or VIC High-level input voltage, VIH Low-level input voltage, VIL MAX UNIT 5 5.25 V 12 V −7 D, DE, RE 0.8 −12 12 −60 60 −8 4 SN65LBC182 −40 85 SN75LBC182 0 70 Driver Operating free-air temperature, TA NOM 2 Differential input voltage, VID (see Note 3) Output current, IO MIN 4.75 Receiver V V mA °C NOTE 3: Differential input/output bus voltage is measured at the noninverting terminal A with respect to the inverting terminal B. www.ti.com 3 

 SLLS500A − MAY 2001 − REVISED MARCH 2005 driver electrical characteristics over recommended operating conditions PARAMETER TEST CONDITIONS VIK VO Input clamp voltage |VOD| Differential output voltage ∆VOD VOC(SS) Change in magnitude of differential output voltage ∆VOC(SS) Change in steady-state common-mode output voltage VOC(PP) II = −18 mA IO = 0 Output voltage Peak-to-peak change in common-mode output voltage during state transitions MAX VCC VCC V V −0.2 VCC 0.2 1 3 −0.2 0.2 V 0 See Figure 1 1.5 2.2 See Figure 2 1.5 2.2 See Figure 1 V V See Figures 1 and 4 0.8 IOZ IIH High-impedance output current See receiver input currents High-level input current (D, DE) IIL IOS Low-level input current (D, DE) VI = 2.4 V VI = 0.4 V Short-circuit output current VO = −7 V to 12 V ICC Supply current V 50 µA 250 mA µA −50 −250 SN75LBC182 SN65LBC182 UNIT −1.5 RL = 54 Ω, Vtest = −7 V to 12 V, Steady-state common-mode output voltage TYP† MIN No load, DE at VCC, RE at VCC 12 25 12 30 mA † All typical values are at VCC = 5 V and TA = 25°C. driver switching characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX tr tf Differential output signal rise time 0.25 0.72 1.2 Differential output signal fall time 0.25 0.73 1.2 tPLH tPHL Propagation delay time, low-to-high-level output tsk(p) tPZH Pulse skew (tPHL − tPLH) tPHZ tPZL Output disable time from high level tPLZ Output disable time from low level 4 RL = 54 Ω, See Figure 3 CL = 50 pF, 1.3 Propagation delay time, high-to-low-level output Output enable time to high level Output enable time to low level UNIT µs 1.3 0.075 3.5 RL = 110 Ω, See Figure 5 RL = 110 Ω, See Figure 6 www.ti.com 0.15 3.5 3.5 3.5 µss µss 

 SLLS500A − MAY 2001 − REVISED MARCH 2005 receiver electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER VIT+ VIT− Positive-going input threshold voltage Vhys VIK Hysteresis voltage (VIT+ − VIT-) VOH VOL High-level output voltage IOZ High-impedance-state output current TEST CONDITIONS Low-level output voltage TYP† 70 II = −18 mA VID = 200 mV, IO = −8 mA, VID = 200 mV, IO = 4 mA, VO = 0.4 to 2.4 V VIH = 12 V, VCC = 5 V VIH = 12 V, VCC = 0 V VIH = −7 V, VCC = 5 V Bus input current IIH IIL High-level input current (RE) VIH = −7 V, VCC = 0 V VIH = 2 V Low-level input current (RE) VIL = 0.8 V mV −1.5 See Figure 7 V 2.8 V See Figure 7 0.4 V ±1 µA 250 250 Other input at 0 V −200 A µA −200 50 µA 3.5 mA 250 µA µA −50 DE at 0 V, RE at 0 V Supply current UNIT V −0.2 II ICC MAX 0.2 Negative-going input threshold voltage Enable-input clamp voltage MIN No load DE at 0 V, RE at VCC 175 † All typical values are at VCC = 5 V and TA = 25°C. receiver switching characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX tr tf Differential output signal rise time tPLH tPHL Propagation delay time, low-to-high-level output Propagation delay time, high-to-low-level output 150 tPZH tPZL Output enable time to high level 100 tPHZ tPLZ Output disable time from high level tsk(p) Pulse skew  tPHL − tPLH Differential output signal fall time Output enable time to low level UNIT 20 20 CL = 50 pF, See Figure 8 Output disable time from low level See Figure 7 150 100 100 100 50 www.ti.com ns ns ns ns 5 

 SLLS500A − MAY 2001 − REVISED MARCH 2005 PARAMETER MEASUREMENT INFORMATION IO 27 Ω II 0 V or 3 V IO VO 50 pF† VOD 27 Ω VOC VO †Includes probe and jig capacitance Figure 1. Driver Test Circuit, VOD and VOC Without Common-Mode Loading 375 Ω VOD Input 60 Ω VTEST = −7 V to 12 V 375 Ω VTEST Figure 2. Driver Test Circuit, VOD With Common-Mode Loading 3V RL = 54 Ω Signal Generator{ Input CL = 50 pF} 1.5 V 1.5 V 0V VOD tPLH 50 Ω Output tPHL 90% 90% 10% 10% tr †PRR = 1 MHz, 50% duty cycle, tr < 6 ns, tf < 6 ns, Zo = 50 Ω ‡Includes probe and jig capacitance tf Figure 3. Driver Switching Test Circuit and Waveforms VOC VOC(PP) ∆VOC(SS) Figure 4. VOC Definitions 6 www.ti.com VOD(H) 0V VOD(L) 

 SLLS500A − MAY 2001 − REVISED MARCH 2005 PARAMETER MEASUREMENT INFORMATION Output 3V S1 Input 1.5 V 1.5 V 0 or 3 V Generator (see Note A) RL = 110 Ω CL = 50 pF (see Note B) 0V 0.5 V tPZH VOH 50 Ω Output 2.3 V tPHZ TEST CIRCUIT Voff ≈ 0 V VOLTAGE WAVEFORMS NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1.25 kHz, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns, ZO = 50 Ω. B. CL includes probe and jig capacitance. Figure 5. Driver tPZH and tPHZ Test Circuit and Voltage Waveforms 5V 3V Input RL = 110 Ω S1 1.5 V 0V Output 0 or 3 V Generator (see Note A) 1.5 V tPZL tPLZ CL = 50 pF (see Note B) 50 Ω 2.3 V Output 5V 0.5 V VOL TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1.25 kHz, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns, ZO = 50 Ω. B. CL includes probe and jig capacitance. Figure 6. Driver tPZL and tPLZ Test Circuit and Voltage Waveforms II A VID Input VI B 1.5 V Inputs RE 50% VO 50 pF (see Note A) Output 3V 1.5 V 0V 50% tPLH Output IO R tPHL 90% 90% 10% 10% tr NOTE A: This value includes probe and jig capacitance (± 10%). VOH 50% VOL tf Figure 7. Receiver tPLH and tPHL Test Circuit and Voltage Waveforms www.ti.com 7 

 SLLS500A − MAY 2001 − REVISED MARCH 2005 PARAMETER MEASUREMENT INFORMATION 5V A 620 Ω 0 V or 3 V R 1.5 V B 620 Ω 50 pF (see Note A) RE VO Input 3V A 0V 3V Inputs RE 3V 1.5 V 0V tPHZ Output VO tPZH 0.5 V 0V tPLZ 0.5 V tPZL ∼ 2.5 V VOH ∼ 2.5 V 0.5 V 0.5 V NOTE A: This value includes probe and jig capacitance (± 10%). Figure 8. Receiver tPZL, tPLZ, tPZH, and tPHZ Test Circuit and Voltage Waveforms 8 www.ti.com VOL 

 SLLS500A − MAY 2001 − REVISED MARCH 2005 TYPICAL CHARACTERISTICS DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs TEMPERATURE DRIVER PROPAGATION DELAY TIME vs TEMPERATURE 800 RL = 54 Ω 2.5 tpd − Driver Propagation Delay Time − ns VOD − Driver Differential Output Voltage − V 3.0 VCC = 5.25 V VCC = 5 V 2.0 VCC = 4.75 V 1.5 1.0 −40 −20 0 20 40 60 780 760 tPHL 740 720 tPLH 700 680 660 640 −40 80 TA − Free-Air Temperature − °C −20 DRIVER TRANSITION TIME vs TEMPERATURE 40 60 80 DIFFERENTIAL OUTPUT VOLTAGE vs OUTPUT CURRENT 900 4.5 4.0 VOD − Differential Output Voltage − V 800 tt − Driver Transition Time − ns 20 Figure 10 Figure 9 tf 700 tr 600 500 400 300 −40 0 TA − Free-Air Temperature − °C −20 0 20 40 60 3.5 3.0 VCC = 5.5 V 2.5 VCC = 4.5 V 2.0 1.5 VCC = 5 V 1.0 0.5 0.0 80 0 TA − Free-Air Temperature − °C 10 20 30 40 50 60 70 80 90 100 IO − Output Current − mA Figure 11 Figure 12 www.ti.com 9 

 SLLS500A − MAY 2001 − REVISED MARCH 2005 TYPICAL CHARACTERISTICS RECEIVER INPUT CURRENT vs INPUT VOLTAGE 0.25 I(I) − Receiver Input Current − mA 0.20 0.15 0.10 0.05 −0.00 A, B (VCC = 0 V) −0.05 B (VCC = 5 V) −0.10 A (VCC = 5 V) −0.15 −0.20 −10 −5 0 5 10 15 VI − Input Voltage − V Figure 13 APPLICATION INFORMATION SN65LBC182 SN75LBC182 SN65LBC182 SN75LBC182 RT RT Up to 128 Transceivers NOTE A: The line should be terminated at both ends in its characteristic impedance (RT = ZO). Stub lengths off the main line should be kept as short as possible. Figure 14. Typical Application Circuit 10 www.ti.com PACKAGE OPTION ADDENDUM www.ti.com 13-Aug-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN65LBC182D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 6LB182 SN65LBC182DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 6LB182 SN65LBC182DRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 6LB182 SN65LBC182P ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 65LBC182 SN75LBC182D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 7LB182 SN75LBC182DG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 7LB182 SN75LBC182DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 7LB182 SN75LBC182P ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 75LBC182 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of