SN65LV1023AMDBREP

SN65LV1023A-EP SN65LV1224B-EP www.ti.com SGLS358 – SEPTEMBER 2006 10-MHz To 66-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER • FEATURES • • • • • (1) Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –55°C to 125°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree (1) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. • • • • • • • • 100-Mbps to 660-Mbps Serial LVDS Data Payload Bandwidth at 10-MHz to 66-MHz System Clock Pin-Compatible Superset of DS92LV1023/DS92LV1224 Chipset (Serializer/Deserializer) Power Consumption 6 cycles, another 1026 SYNC pattern transmission initiates. 13 TCLK_R/F 14 TCLK LVTTL-level reference clock input. The SN65LV1023A accepts a 10-MHz to 66-MHz clock. TCLK strobes parallel data into the input latch and provides a reference frequency to the PLL. 1, 12, 13 AGND Analog circuit ground (PLL and analog circuits) 4, 11 AVCC Analog circuit power supply (PLL and analog circuits) 14, 20, 22 DGND Digital circuit ground 21, 23 DVCC Digital circuit power supply 10 LOCK LVTTL level output. LOCK goes low when the deserializer PLL locks onto the embedded clock edge. Digital circuit ground Parallel LVTTL data inputs LVTTL logic input. Low selects a TCLK falling-edge data strobe; high selects a TCLK rising-edge data strobe. DESERIALIZER LVTTL logic input. Asserting this pin low turns off the PLL and places outputs into a high-impedance state, putting the device into a low-power mode. To initiate power down, this pin is held low for a minimum of 16 ns. As long as PWRDN is held low, the device is in the power down state. 7 PWRDN 2 RCLK_R/F 9 RCLK 3 REFCLK LVTTL logic input. Use this pin to supply a REFCLK signal for the internal PLL frequency. 8 REN LVTTL logic input. Low places ROUT0–ROUT9 and RCLK in the high-impedance state. 5 RI+ Serial data input. Noninverting LVDS differential input 6 RI– Serial data input. Inverting LVDS differential input 28–24, 19–15 ROUT0–ROUT9 LVTTL logic input. Low selects an RCLK falling-edge data strobe; high selects an RCLK rising-edge data strobe. LVTTL level output recovered clock. Use RCLK to strobe ROUTx. Parallel LVTTL data outputs Submit Documentation Feedback 7 SN65LV1023A-EP SN65LV1224B-EP www.ti.com SGLS358 – SEPTEMBER 2006 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT VCC to GND –0.3 V to 4 V LVTTL input voltage –0.3 V to (VCC + 0.3 V) LVTTL output voltage –0.3 V to (VCC + 0.3 V) LVDS receiver input voltage –0.3 V to 3.9 V LVDS driver output voltage –0.3 V to 3.9 V LVDS output short circuit duration Electrostatic discharge: 10 ms HBM up to 6 kV MM up to 200 V Junction temperature 150°C Storage temperature (2) –65°C to 150°C Lead temperature (soldering, 4 seconds) 260°C DB package maximum package power dissipation 1.27 W TA = 25°C DB package derating (1) (2) 10.8 mW/°C above 25°C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Long term high temperature storage and/or extended use at maximum operating conditions may result in a reduction of overall device life. See http://www.ti.com/ep_quality for additional information on enhanced plastic packaging. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) VCC (1) MIN NOM MAX 3 3.3 3.6 V 0 2.4 V ID 2 ǒ Ǔ V Supply voltage Receiver input voltage range VCM Receiver input common mode range V V 2.4 * Supply noise voltage TA (1) 8 Operating free-air temperature –55 25 ID 2 UNIT 100 mVp-p 125 °C By design, DVCC and AVCC are separated internally and does not matter what the difference is for |DVCC–AVCC|, as long as both are within 3 V to 3.6 V. Submit Documentation Feedback SN65LV1023A-EP SN65LV1224B-EP www.ti.com SGLS358 – SEPTEMBER 2006 ELECTRICAL CHARACTERISTICS over recommended operating supply and temperature ranges (unless otherwise specified) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCC V 0.8 V SERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS (1) VIH High-level input voltage VIL Low-level input voltage VCL Input clamp voltage IIN Input current, (2) 2 GND ICL = –18 mA VIN = 0 V or 3.6 V –200 -0.86 –1.5 V ±100 200 µA DESERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS (3) VIH High-level input voltage 2 VCC V VIL Low-level input voltage GND 0.8 V VCL Input clamp voltage ICL = –18 mA IIN Input current (pull-up and pull-down resistors on inputs) VIN = 0 V or 3.6 V VOH High-level output voltage IOH = –5 mA VOL Low-level output voltage IOL = 5 mA IOS Output short-circuit current VOUT = 0 V IOZ High-impedance output current PWRDN or REN = 0.8 V, VOUT = 0 V or VCC –0.62 –200 –1.5 V 200 µA VCC V 2.2 3 GND 0.25 0.5 V –47 –85 mA –10 ±1 10 µA 350 450 SERIALIZER LVDS DC SPECIFICATIONS (Apply to Pins DO+ and DO–) RL = 27 Ω, See Figure 20 VOD Output differential voltage (DO+)–(DO–) ∆VOD Output differential voltage unbalance VOS Offset voltage ∆VOS Offset voltage unbalance IOS Output short circuit current D0 = 0 V, DINx = high, PWRDN and DEN = 2.4 V IOZ High-impedance output current PWRDN or DEN = 0.8 V, DO = 0 V or VCC IOX Power-off output current VCC = 0 V, DO = 0 V or 3.6 V CO Output single-ended capacitance mV 35 1.1 mV 1.2 1.3 V 4.8 35 mV –10 –90 mA –10 ±1 10 µA –20 ±1 25 µA 1 pF DESERIALIZER LVDS DC SPECIFICATIONS (Apply to Pins RI+ and RI–) VTH Differential threshold high voltage VTL Differential threshold low voltage IIN Input current CI Input single-ended capacitance VCM = 1.1 V 50 –50 mV mV VIN = 2.4 V, VCC = 3.6 V or 0 V –10 ±1 15 VIN = 0 V, VCC = 3.6 V or 0 V –10 ±0.05 10 0.5 µA pF SERIALIZER SUPPLY CURRENT (Applies to Pins DVCC and AVCC) ICCD Serializer supply current worst case RL = 27 Ω, See Figure 5 ICCXD Serializer supply current PWRDN = 0.8 V f = 10 MHz 20 25 f = 66 MHz 55 70 200 500 f = 10 MHz 15 35 f = 66 MHz 80 95 0.36 1 mA µA DESERIALIZER SUPPLY CURRENT (applies to pins DVCC and AVCC) ICCR Deserializer supply current, worst case ICCXR Deserializer supply current, power down (1) (2) (3) CL = 15 pF, See Figure 5 PWRDN = 0.8 V, REN = 0.8 V mA mA Apply to DIN0–DIN9, TCLK, PWRDN, TCLK_R/F, SYNC1, SYNC2, and DEN High IIN values are due to pullup and pulldown resistors on the inputs. Apply to pins PWRDN, RCLK_R/F, REN, and REFCLK = inputs; apply to pins ROUTx, RCLK, and LOCK = outputs (see Deserializer truth table) Submit Documentation Feedback 9 SN65LV1023A-EP SN65LV1224B-EP www.ti.com SGLS358 – SEPTEMBER 2006 SERIALIZER TIMING REQUIREMENTS FOR TCLK over recommended operating supply and temperature ranges (unless otherwise specified) PARAMETER MIN TYP MAX UNIT 15.15 T 100 ns Transmit clock high time 0.4T 0.5T 0.6T ns tTCIL Transmit clock low time 0.4T 0.5T 0.6T ns tt(CLK) TCLK input transition time 3 6 tJIT TCLK input jitter tTCP Transmit clock period tTCIH TEST CONDITIONS See Figure 19 Frequency tolerance –100 ns 150 ps (RMS) +100 ppm MAX UNIT SERIALIZER SWITCHING CHARACTERISTICS over recommended operating supply and temperature ranges (unless otherwise specified) PARAMETER TEST CONDITIONS MIN RL = 27 Ω, CL = 10 pF to GND, See Figure 6 TYP tTLH(L) LVDS low-to-high transition time tLTHL(L) LVDS high-to-low transition time tsu(DI) DIN0–DIN9 setup to TCLK tsu(DI) DIN0–DIN9 hold from TCLK td(HZ) DO± high-to-high impedance state delay td(LZ) DO± low-to-high impedance state delay td(ZH) DO± high-to-high impedance state-to-high delay 5 td(ZL) DO± high-to-high impedance state-to-low delay 6.5 tw(SPW) SYNC pulse duration t(PLD) Serializer PLL lock time td(S) Serializer delay RL = 27 Ω, See Figure 13 tDJIT Deterministic jitter RL = 27 Ω, CL = 10 pF to GND RL = 27 Ω, CL = 10 pF to GND, See Figure 9 0.2 ns 0.25 ns 0.5 ns 4 RL = 27 Ω, CL = 10 pF to GND, See Figure 10 ns 2.5 2.5 RL = 27 Ω, See Figure 12 ns 6×tTCP ns 1026×tTCP tTCP ns tTCP+2 tTCP+3 230 ps 150 tRJIT Random jitter RL = 2.7 Ω, CL = 10 pF to GND ns 10 ps (RMS) DESERIALIZER TIMING REQUIREMENTS FOR REFCLK over recommended operating supply and temperature ranges (unless otherwise specified) PARAMETER tRFCP REFCLK period tRFDC REFCLK duty cycle tt(RF) REFCLK transition time TEST CONDITIONS TYP MAX UNIT T 100 ns 30% 50% 70% 3 Frequency tolerance 10 MIN 15.15 –100 Submit Documentation Feedback 6 +100 ns ppm SN65LV1023A-EP SN65LV1224B-EP www.ti.com SGLS358 – SEPTEMBER 2006 DESERIALIZER SWITCHING CHARACTERISTICS over recommended operating supply and temperature ranges (unless otherwise specified) PARAMETER t(RCP) Receiver out clock period tTLH(C)) CMOS/TTL low-to-high transition time tTHL(C)) CMOS/TTL high-to-low transition time td(D) (1) Deserializer delay, See Figure 14 t(ROS) TEST CONDITIONS t(RCP) = t(TCP), See Figure 13 CL = 15 pF, CL = 15 pF, See Figure 7 PIN/FREQ RCLK MIN TYP 15.15 ROUT0–ROUT9 , LOCK, RCLK MAX UNIT 100 ns 1.2 ns 1.1 Room temperature, 10 MHz 3.3 V 1.75×t(RCP) +4.2 1.75×t(RCP) +12.6 66 MHz 1.75×t(RCP) +7.4 1.75×t(RCP) +9.7 ROUTx data valid before RCLK See Figure 15 RCLK 10 MHz 0.4×t(RCP) 0.5×t(RCP) RCLK 66 MHz 0.4×t(RCP) 0.5×t(RCP) 10 MHz –0.4×t(RCP) –0.5×t(RCP) 66 MHz –0.4×t(RCP) –0.5×t(RCP) 40% 50% ns ns ns t(ROH) ROUTx data valid after RCLK t(RDC) RCLK duty cycle td(HZ) High-to-high impedance state delay 6.5 ns td(LZ) Low-to-high impedance state delay 4.7 ns td(HR) High-impedance state to high delay 5.3 ns td(ZL) High-impedance state to low delay 4.7 ns t(DSR1) Deserializer PLL lock time from PWRDN (with SYNCPAT) t(DSR2) Deserializer PLL lock time from SYNCPAT td(ZHLK) High-impedance state to high delay (power up) tRNM Deserializer noise margin (1) (2) (3) See Figure 16 See Figure 17, Figure 18, and (2) ROUT0–ROUT9 10 MHz 850 × tRFCP 66 MHz 850 × tRFCP 10 MHz 2 66 MHz 0.303 LOCK See Figure 19 and (3) 60% 3 10 MHz 3680 66 MHz 540 ns µs ns ps The deserializer delay time for all frequencies does not exceed two serial bit times. t(DSR1) represents the time required for the deserializer to register that a lock has occurred upon powerup or when leaving the powerdown mode. t(DSR2) represents the time required to register that a lock has occurred for the powered up and enabled deserializer when the input (RI±) conditions change from not receiving data to receiving synchronization patterns (SYNCPATs). In order to specify deserializer PLL performance, tDSR1 and tDSR2 are specified with REFCLK active and stable and specific conditions of SYNCPATs. tRNM represents the phase noise or jitter that the deserializer can withstand in the incoming data stream before bit errors occur. Submit Documentation Feedback 11 SN65LV1023A-EP SN65LV1224B-EP www.ti.com SGLS358 – SEPTEMBER 2006 TIMING DIAGRAMS AND TEST CIRCUITS TCLK ODD DIN EVEN DIN Figure 3. Worst-Case Serializer ICC Test Pattern SUPPLY CURRENT vs TCLK FREQUENCY 60 66 mA, 48.880 MHz ICC − Supply Current − mA 50 40 ICC 30 20 10 mA, 14.732 MHz 10 0 0 20 40 TCLK Frequency − MHz Figure 4. 12 Submit Documentation Feedback 60 80 SN65LV1023A-EP SN65LV1224B-EP www.ti.com SGLS358 – SEPTEMBER 2006 TIMING DIAGRAMS AND TEST CIRCUITS (continued) RCLK ODD ROUT EVEN ROUT Figure 5. Worst-Case Deserializer ICC Test Pattern 10 pF tTLH(L) DO+ tTHL(L) RL 80% Vdiff 80% 20% 20% DO− 10 pF Vdiff = (DO+) − (DO−) Figure 6. Serializer LVDS Output Load and Transition Times CMOS/TTL Output Deserializer tTHL(C) tTLH(C) 80% 15 pF 80% 20% 20% Figure 7. Deserializer CMOS/TTL Output Load and Transition Times tt(CLK) TCLK tt(CLK) 90% 10% 90% 10% 3V 0V Figure 8. Serializer Input Clock Transition Time Submit Documentation Feedback 13 SN65LV1023A-EP SN65LV1224B-EP www.ti.com SGLS358 – SEPTEMBER 2006 TIMING DIAGRAMS AND TEST CIRCUITS (continued) tTCP 1.5 V TCLK 1.5 V For TCLK_R/F = Low 1.5 V th(DI) tsu(DI) DIN [9:0] 1.5 V Setup Hold 1.5 V Figure 9. Serializer Setup/Hold Times Parasitic Package and Trace Capacitance 3V DEN 1.5 V 1.5 V 0V td(ZH) td(HZ) VOH 13.5 Ω DO+ 50% 1.1 V DO− DO± 50% 1.1 V td(ZL) td(LZ) 13.5 Ω DEN 1.1 V 50% 50% VOL Figure 10. Serializer High-Impedance State Test Circuit and Timing PWRDN 2V 0.8 V 1026 Cycles td(HZ) or td(LZ) TCLK td(ZH) or td(ZL) tPLD DO± 3-State Output Active Figure 11. Serializer PLL Lock Time and PWRDN High-Impedance State Delays 14 Submit Documentation Feedback 3-State SN65LV1023A-EP SN65LV1224B-EP www.ti.com SGLS358 – SEPTEMBER 2006 TIMING DIAGRAMS AND TEST CIRCUITS (continued) REN PWRDN TCLK tw(SP) SYNC1 or SYNC2 DO± DATA SYNC Pattern TCLK SYNC1 or SYNC2 tw(SP) Min. Timing Met DO± SYNC Pattern DATA Figure 12. SYNC Timing Delays DIN DIN0 − DIN9 SYMBOL N DIN0 − DIN9 SYMBOL N+1 td(S) TCLK Timing for TCLK_R/F = High Start D00 − D09 SYMBOL N−1 Bit Stop Start Bit Bit D00 − D09 SYMBOL N Stop Bit DO Figure 13. Serializer Delay Submit Documentation Feedback 15 SN65LV1023A-EP SN65LV1224B-EP www.ti.com SGLS358 – SEPTEMBER 2006 TIMING DIAGRAMS AND TEST CIRCUITS (continued) Start Bit D00 − D09 SYMBOL N Stop Start Bit Bit D00 − D09 SYMBOL N+1 Stop Start Bit Bit D00 − D09 SYMBOL N+2 Stop Bit RI 1.2 V 1V tDD RCLK Timing for TCLK_R/F = High ROUT ROUT0 − ROUT9 SYMBOL N−1 ROUT0 − ROUT9 SYMBOL N+1 ROUT0 − ROUT9 SYMBOL N Figure 14. Deserializer Delay tLow tHigh RCLK RCLK_R/F = Low tHigh tLow RCLK RCLK_R/F = High tROH tROS ROUT [9:0] 1.5 V Data Valid Before RCLK Data Valid After RCLK 1.5 V Figure 15. Deserializer Data Valid Out Times 7 V x (LZ/ZL), Open (HZ/ZH) VOH REN 500 Ω 450 Ω 1.5 V 1.5 V VOL Scope td(LZ) VOL + 0.5 V 50 Ω td(ZL) VOL + 0.5 V VOL ROUT[9:0] td(HZ) td(ZH) VOH VOH − 0.5 V Figure 16. Deserializer High-Impedance State Test Circuit and Timing 16 Submit Documentation Feedback VOH − 0.5 V SN65LV1023A-EP SN65LV1224B-EP www.ti.com SGLS358 – SEPTEMBER 2006 TIMING DIAGRAMS AND TEST CIRCUITS (continued) PWRDN 2V 0.8 V REFCLK 1.5 V t(DSR1) DATA RI± Not Important td(ZHL) LOCK SYNC Patterns 3-State 3-State td(HZ) or td(LZ) td(ZH) or td(ZL) ROUT[9:0] 3-State 3-State SYNC Symbol or DIN[9:0] RCLK 3-State 3-State RCLK_R/F = Low REN Figure 17. Deserializer PLL Lock Times and PWRDN 3-State Delays Submit Documentation Feedback 17 SN65LV1023A-EP SN65LV1224B-EP www.ti.com SGLS358 – SEPTEMBER 2006 TIMING DIAGRAMS AND TEST CIRCUITS (continued) 3.6 V 3V VCC 0V PWRDN 0.8 V REFCLK t(DSR2) DATA 1.2 V RI± Not Important 1V SYNC Patterns LOCK 3-State td(ZH) or td(ZL) ROUT[9:0] td(HZ) or td(LZ) 3-State 3-State SYNC Symbol or DIN[9:0] RCLK 3-State 3-State REN Figure 18. Deserializer PLL Lock Time From SyncPAT 1.2 V VTH RI± VTL 1V tDJIT tDJIT tRNM tRNM tSW Ideal Sampling Position tSW: Setup and Hold Time (Internal Data Sampling Window) tDJIT: Serializer Output Bit Position Jitter That Results From Jitter on TCLK tRNM: Receiver Noise Margin Time Figure 19. Receiver LVDS Input Skew Margin 18 Submit Documentation Feedback SN65LV1023A-EP SN65LV1224B-EP www.ti.com SGLS358 – SEPTEMBER 2006 TIMING DIAGRAMS AND TEST CIRCUITS (continued) DO+ RL 10 DIN Parallel-to-Serial DO− > TCLK VOD = (DO+) − (DO−) Differential Output Signal Is Shown as (DO+) − (DO−) Figure 20. VOD Diagram DEVICE STARTUP PROCEDURE It is recommended that the PWRDNB pin on both the SN65LV1023A and the SN65LV1224B device be held to a logic LOW level until after the power supplies have powered up to at least 3 V as shown in Figure 21. 3.0 V VDD PWRDNB Figure 21. Device Startup Submit Documentation Feedback 19 SN65LV1023A-EP SN65LV1224B-EP www.ti.com SGLS358 – SEPTEMBER 2006 APPLICATION INFORMATION DIFFERENTIAL TRACES AND TERMINATION The performance of the SN65LV1023A/SN65LV1224B is affected by the characteristics of the transmission medium. Use controlled-impedance media and termination at the receiving end of the transmission line with the media’s characteristics impedance. Use balanced cables such as twisted pair or differential traces that are ran close together. A balanced cable picks up noise together and appears to the receiver as common mode. Differential receivers reject common-mode noise. Keep cables or traces matched in length to help reduce skew. Running the differential traces close together helps cancel the external magnetic field, as well as maintain a constant impedance. Avoiding sharp turns and reducing the number of vias also helps. TOPOLOGIES There are several topologies that the serializers can operate. Three common examples are shown below. Figure 22 shows an example of a single-terminated point-to-point connection. Here a single termination resistor is located at the deserializer end. The resistor value should match that of the characteristic impedance of the cable or PC board traces. The total load seen by the serializer is 100 Ω. Double termination can be used and typically reduces reflections compared with single termination. However, it also reduces the differential output voltage swing. AC-coupling is only recommended if the parallel TX data stream is encoded to achieve a dc-balanced data stream. Otherwise the ac-capacitors can induce common mode voltage drift due to the dc-unbalanced data stream. Serialized Data 100 Ω Parallel Data In Parallel Data Out Figure 22. Single-Terminated Point-to-Point Connection Figure 23 shows an example of a multidrop configuration. Here there is one transmitter broadcasting data to multiple receivers. A 50-kΩ resistor at the far end terminates the bus. ASIC ASIC ASIC ASIC 50 Ω Figure 23. Multidrop Configuration Figure 24 shows an example of multiple serializers and deserializers on the same differential bus, such as in a backplane. This is a multipoint configuration. In this situation, the characteristic impedance of the bus can be significantly less due to loading. Termination resistors that match the loaded characteristic impedance are required at each end of the bus. The total load seen by the serializer in this example is 27 Ω. 20 Submit Documentation Feedback SN65LV1023A-EP SN65LV1224B-EP www.ti.com SGLS358 – SEPTEMBER 2006 APPLICATION INFORMATION (continued) ASIC ASIC ASIC 54 Ω ASIC 54 Ω Figure 24. Multiple Serializers and Deserializers on the Same Differential Bus Submit Documentation Feedback 21 PACKAGE MATERIALS INFORMATION www.ti.com 14-Aug-2019 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN65LV1224BMDBREP Package Package Pins Type Drawing SSOP DB 28 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 16.4 Pack Materials-Page 1 8.1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.4 2.5 12.0 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Aug-2019 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65LV1224BMDBREP SSOP DB 28 2000 350.0 350.0 43.0 Pack Materials-Page 2 PACKAGE OUTLINE DB0028A SSOP - 2 mm max height SCALE 1.500 SMALL OUTLINE PACKAGE C 8.2 TYP 7.4 A 0.1 C PIN 1 INDEX AREA SEATING PLANE 26X 0.65 28 1 2X 10.5 9.9 NOTE 3 8.45 14 15 28X B 5.6 5.0 NOTE 4 SEE DETAIL A (0.15) TYP 0.38 0.22 0.15 C A B 2 MAX 0.25 GAGE PLANE 0 -8 0.95 0.55 0.05 MIN DETAIL A A 15 TYPICAL 4214853/B 03/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-150. www.ti.com EXAMPLE BOARD LAYOUT DB0028A SSOP - 2 mm max height SMALL OUTLINE PACKAGE SYMM 28X (1.85) (R0.05) TYP 1 28X (0.45) 28 26X (0.65) SYMM 15 14 (7) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK OPENING SOLDER MASK OPENING METAL UNDER SOLDER MASK METAL EXPOSED METAL EXPOSED METAL 0.07 MAX ALL AROUND NON-SOLDER MASK DEFINED (PREFERRED) 0.07 MIN ALL AROUND SOLDER MASK DEFINED SOLDER MASK DETAILS 15.000 4214853/B 03/2018 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DB0028A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 28X (1.85) SYMM (R0.05) TYP 1 28X (0.45) 28 26X (0.65) SYMM 14 15 (7) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4214853/B 03/2018 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. 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