SN65LVCP114EVM

User's Guide SLLU160 – December 2011 SN65LVCP114 Evaluation Module (EVM) The Texas Instruments SN65LVCP114 Evaluation Module (EVM) board is used to evaluate the SN65LVCP114, 14.2Gbps Quad 1:2-2:1 Mux, Linear-Redriver with Signal Conditioning. This document provides guidance on the device's proper use by showing some operating configurations and test modes. The EVM board schematic and layout information are also provided for the customer. Information in this guide assists the customer in choosing the optimal design methods and materials in designing a complete system. SLLU160 – December 2011 Submit Documentation Feedback SN65LVCP114 Evaluation Module (EVM) Copyright © 2011, Texas Instruments Incorporated 1 www.ti.com WARNING This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices, pursuant to subpart J, part 15 of FCC rules. These rules are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case the user, at their own expense, must take whatever measures are necessary to correct this interference. Contents 1 Introduction .................................................................................................................. 3 2 EVM PCB and High-Speed Design Considerations .................................................................... 3 3 SN65LVCP114 EVM Kit Contents ........................................................................................ 3 4 SN65LVCP114 EVM Board Configuration ............................................................................... 4 5 Test Setup ................................................................................................................... 5 6 I2C Mode ..................................................................................................................... 6 7 GPIO Mode .................................................................................................................. 6 8 Schematics ................................................................................................................... 8 9 Bill of Materials ............................................................................................................. 16 10 Board Layout ............................................................................................................... 18 Appendix A Jumper Shunt Settings ........................................................................................... 25 Appendix B Typical Evaluation Setups ....................................................................................... 25 List of Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ....................................................................................................... SN65LVCP114 EVM Jumper Description ............................................................................... SN65LVCP114 EVM Schematic, Port A ................................................................................. SN65LVCP114 EVM Schematic, Port B ................................................................................. SN65LVCP114 EVM Schematic, Port C ............................................................................... SN65LVCP114 EVM Schematic, Controls_1 .......................................................................... SN65LVCP114 EVM Schematic, Controls_2 .......................................................................... SN65LVCP114 EVM Schematic, Controls_3 .......................................................................... SN65LVCP114 EVM Schematic, Power Distribution ................................................................. SN65LVCP114 EVM Schematic, USB Interface ...................................................................... SN65LVCP114 EVM PCB Layer Construction ........................................................................ SN65LVCP114 Board Layout: Top Signal (Layer 1 of 6) ............................................................ SN65LVCP114 Board Layout: Internal Ground (Layer 2 of 6) ...................................................... SN65LVCP114 Board Layout: Internal Power (Layer 3 of 6) ........................................................ SN65LVCP114 Board Layout: Internal Signal (Layer 4 of 6) ........................................................ SN65LVCP114 Board Layout: Internal Ground (Layer 5 of 6) ...................................................... SN65LVCP114 Board Layout: Bottom Signal (Layer 6 of 6) ........................................................ Receive Side Use Case .................................................................................................. Transmit Side Use Case.................................................................................................. Combined Bus Extension Use Case .................................................................................... SN65LVCP114 EVM 4 5 8 9 10 11 12 13 14 15 18 19 20 21 22 23 24 25 26 26 List of Tables 1 2 SN65LVCP114 EVM Pin and Jumper Functionality .................................................................... 5 SN65LVCP114 Evaluation Module (EVM) Copyright © 2011, Texas Instruments Incorporated SLLU160 – December 2011 Submit Documentation Feedback Introduction www.ti.com 2 3 4 5 1 ................................................................................ SN65LVCP114 EVM Jumper and EQ Settings ......................................................................... SN65LVCP114 EVM GPIO Mode Settings .............................................................................. SN65LVCP114 EVM Bill of Materials ................................................................................... SN65LVCP114 EVM I2C Mode Settings 6 6 7 16 Introduction The Texas Instruments (TI) SN65LVCP114 is a 14.2Gbps asynchronous, protocol-agnostic, low-latency QUAD 1:2-2:1 mux, linear-redriver switch with signal conditioning. The device linearly compensates for channel loss in backplane and active-cable applications. The architecture of the SN65LVCP114 crosspoint switch is designed to work effectively with ASIC or FPGA products implementing digital equalization by using decision feedback equalizer (DFE) technology. SN65LVCP114 mux, linear-redriver switch preserves the integrity (composition) of the received signal ensuring optimum DFE and system performance. SN65LVCP114 provides low-power mux, linear-redriver solution while at the same time extending the effectiveness of DFE. 2 EVM PCB and High-Speed Design Considerations The EVM and the contents of this guide are used to evaluate device parameters in addition to helping with high-speed board layout. As the frequency of operation increases, the board designer must take special care to ensure that the highest signal integrity is maintained. To achieve this, the board's impedance is controlled to 50 Ω single-ended or 100 Ω differential impedance for both the low and high-speed differential serial and clock connections. The use of vias is minimized and, when necessary, are designed to minimize impedance discontinuities along the transmission line. Care was taken to control trace length mismatch (board skew) to less than ±0.1 MIL. The board layout is designed and optimized to support high-speed operation. Understanding impedance control and transmission line effects is crucial when designing high-speed boards. Some of the advanced features offered by this board include: • SN65LVCP114 printed circuit board (PCB) designed for optimal high-speed signal integrity using Rogers Material for the outer signal layers and FR-4 for the inner layers. All Gigabit signals are routed over the Rogers Material for minimal signal loss. • SMA and header fixtures are easily connected to test equipment. • All input/output signals are accessible for rapid prototyping. • On-board capacitors provide AC coupling of high-speed transmit and receive signals. 3 SN65LVCP114 EVM Kit Contents The SN65LVCP114 EVM kit contains the following: • SN65LVCP114 EVM board • SN65LVCP114 EVM User’s Guide (this document) • SN65LVCP114 datasheet • CD-ROM containing the graphical user interface (GUI) software SLLU160 – December 2011 Submit Documentation Feedback SN65LVCP114 Evaluation Module (EVM) Copyright © 2011, Texas Instruments Incorporated 3 SN65LVCP114 EVM Board Configuration 4 www.ti.com SN65LVCP114 EVM Board Configuration The SN65LVCP114 is operated from a 2.5-V or 3.3-V power supply with a 1.0 A or greater current rating. The SN65LVCP114 has three ports; each port has four lanes. The switch logic of the SN65LVCP114 is implemented to support 2:1 MUX per lane, 1:2 DEMUX per lane, and independent lane switching. Each of the ports are independently programmed for receive equalization. The device also supports loopback on all three ports. The EVM provides SMA connections for one lane per port for device evaluation with full configuration control of the device through I2C using the SN65LVCP114 GUI provided. Limited configuration control is available through GPIO. Refer to Section 7 for more details. Figure 1. SN65LVCP114 EVM 4 SN65LVCP114 Evaluation Module (EVM) Copyright © 2011, Texas Instruments Incorporated SLLU160 – December 2011 Submit Documentation Feedback Test Setup www.ti.com Figure 2. SN65LVCP114 EVM Jumper Description 5 Test Setup The SN65LVCP114 EVM gives the developer two control interface options for operation, I2C or GPIO mode. Input and Output differential pairs are available through edge-launch SMAs with approximately 2.5 inches of trace with Rogers Low–Dielectric material with 0.1 µF AC Coupling capacitors. Power to the device, VCC, is applied using banana jacks (P1, P2). The USB-to-I2C circuitry on the board uses power from the USB 5-V signal. Table 1. SN65LVCP114 EVM Pin and Jumper Functionality Description Ref Des Symbol J1, J3 AINP2, AINN2 Differential input, lane 2, Fabric switch A side J2, J4 AOUTP2, AOUTN2 Differential output, lane 2, Fabric switch A side J5, J7 BINP2, BINN2 Differential input, lane 2, Fabric switch B side J6, J8 BOUTP2, BOUTN2 Differential output, lane 2, Fabric switch B side J9, J11 CINP2, CINN2 Differential input, lane 2, Fabric switch C side J10, J12 COUTP2, COUTN2 Differential output, lane 2, Fabric switch C side P1 VCC Banana jack, positive power supply connection P2 GND Banana jack, ground power supply connection J13 USB USB cable connection JMP2 CS Don't Care JMP5 PDZ High, normal operation Low, powers down the device, inputs off and outputs disabled, resets the I2C JMP1 I2C_SEL Configures the device in I2C or GPIO mode of operation High, enables I2C mode Low, enables GPIO mode JMP8 I2C_A0_EQA1 3 level control for EQ gain of port A I2C Address JMP6 I2C_A1_EQB1 3 level control for EQ gain of port B I2C Address JMP16 EQ_C0 3 level control for EQ gain of port C Don't care JMP3 I2C_A2_EQC1 3 level control for EQ gain of port C I2C Address GPIO mode SLLU160 – December 2011 Submit Documentation Feedback I2C mode High, acts as Chip Select Low, disables the I2C interface SN65LVCP114 Evaluation Module (EVM) Copyright © 2011, Texas Instruments Incorporated 5 I2C Mode www.ti.com Table 1. SN65LVCP114 EVM Pin and Jumper Functionality (continued) 6 Ref Des Symbol JMP10 JMP13 Description GPIO mode I2C mode EQ_A0 3 level control for EQ gain of port A Don't care EQ_B0 3 level control for EQ gain of port B Don't care JMP7 DIAG High, enables the same data on the line side (Port C) to be output on both fabric side ports (Port A & B) Low, normal operation Don't care JMP26 LN_EN_2 High, enables lane 2 of ports A, B & C Don't care I2C Mode The I2C mode is implemented using the SN65LVCP114 user interface software included in the CD-ROM with the EVM. Refer to the SN65LVCP114 EVM GUI User’s Guide for details on how to use the GUI. Table 2 shows the appropriate jumper settings on the EVM to configure the device in I2C mode. Refer to Appendix A for jumper shunt settings. See the SN65LVCP114 Datasheet for a detailed description of the register map. Table 2. SN65LVCP114 EVM I2C Mode Settings 7 Ref Des Symbol I2C Mode Pin Settings JMP8 I2C_A0_EQA1 Low JMP6 I2C_A1_EQB1 Low JMP3 I2C_A2_EQC1 Low JMP5 PDZ High, normal operation Low, powers down the device, inputs off and outputs disabled, resets the I2C JMP1 I2C_SEL Configures the device in I2C or GPIO mode of operation High, enables I2C mode GPIO Mode Although it is recommended to use the EVM in I2C mode so that the user has full control of the device some control of the SN65LVCP114 device is available on the EVM through GPIO mode. Refer to Table 3 for the different jumper and EQ settings. Table 4 shows the appropriate jumper and default settings on the EVM to configure and control the device in GPIO mode. Refer to Appendix A for jumper shunt settings. See the SN65LVCP114 Datasheet for a detailed description of the control signals. Table 3. SN65LVCP114 EVM Jumper and EQ Settings 6 EQ[x]0 EQ[x]1 Peaking in dB 0 0 1.3 0 HiZ 2 0 1 3.6 HiZ 0 5 HiZ HiZ 6.5 HiZ 1 8.3 1 0 10 1 HiZ 11.9 1 1 13.9 SN65LVCP114 Evaluation Module (EVM) Copyright © 2011, Texas Instruments Incorporated SLLU160 – December 2011 Submit Documentation Feedback GPIO Mode www.ti.com Table 4. SN65LVCP114 EVM GPIO Mode Settings Ref Des Symbol GPIO Mode Pin Description JMP8 I2C_A0_EQA1 3 level control for EQ gain of port A JMP6 I2C_A1_EQB1 3 level control for EQ gain of port B JMP3 I2C_A2_EQC1 3 level control for EQ gain of port C JMP10 EQ_A0 3 level control for EQ gain of port A JMP13 EQ_B0 3 level control for EQ gain of port B JMP16 EQ_C0 3 level control for EQ gain of port C LPA Default setting, Loopback disabled LPB Default setting, Loopback disabled LPC Default setting, Loopback disabled SEL0 Default setting, port B is selected on Lane 0 SEL1 Default setting, port B is selected on Lane 1 SEL2 Default setting, port B is selected on Lane 2 SEL3 Default setting, port B is selected on Lane 3 JMP2 CS Don't Care JMP5 PDZ High, normal operation Low, powers down the device, inputs off and outputs disabled, resets the I2C JMP7 DIAG High, enables the same data on line side (Port C) to be output on both fabric side ports (Port A & B) Low, normal operation LN_EN_0 Default setting, lane 0 of ports A, B & C are disabled LN_EN_1 Default setting, lane 1 of ports A, B & C are disabled LN_EN_2 High, enables lane 2 of ports A, B & C Low, disables lane 0 of ports A, B & C LN_EN_3 Default setting, lane 3 of ports A, B & C are disabled DIS_AGC_A Default setting, AGC loop enable DIS_AGC_B Default setting, AGC loop enable DIS_AGC_C Default setting, AGC loop enable VOD_A Default setting; VOD output range = 600 mV VOD_B Default setting; VOD output range = 600 mV VOD_C Default setting; VOD output range = 600 mV GAIN_A Default setting; Receiver Gain = 0.5 GAIN_B Default setting; Receiver Gain = 0.5 JMP26 JMP1 GAIN_C Default setting; Receiver Gain = 0.5 FST_SW Default setting; fast switching, the idle outputs are squelched I2C_SEL Configures the device in I2C or GPIO mode of operation High, enables I2C mode Low, enables GPIO mode SLLU160 – December 2011 Submit Documentation Feedback SN65LVCP114 Evaluation Module (EVM) Copyright © 2011, Texas Instruments Incorporated 7 Schematics 8 www.ti.com Schematics Figure 3. SN65LVCP114 EVM Schematic, Port A 8 SN65LVCP114 Evaluation Module (EVM) Copyright © 2011, Texas Instruments Incorporated SLLU160 – December 2011 Submit Documentation Feedback Schematics www.ti.com Figure 4. SN65LVCP114 EVM Schematic, Port B SLLU160 – December 2011 Submit Documentation Feedback SN65LVCP114 Evaluation Module (EVM) Copyright © 2011, Texas Instruments Incorporated 9 Schematics www.ti.com Figure 5. SN65LVCP114 EVM Schematic, Port C 10 SN65LVCP114 Evaluation Module (EVM) Copyright © 2011, Texas Instruments Incorporated SLLU160 – December 2011 Submit Documentation Feedback Schematics www.ti.com Figure 6. SN65LVCP114 EVM Schematic, Controls_1 SLLU160 – December 2011 Submit Documentation Feedback SN65LVCP114 Evaluation Module (EVM) Copyright © 2011, Texas Instruments Incorporated 11 Schematics www.ti.com Figure 7. SN65LVCP114 EVM Schematic, Controls_2 12 SN65LVCP114 Evaluation Module (EVM) Copyright © 2011, Texas Instruments Incorporated SLLU160 – December 2011 Submit Documentation Feedback Schematics www.ti.com Figure 8. SN65LVCP114 EVM Schematic, Controls_3 SLLU160 – December 2011 Submit Documentation Feedback SN65LVCP114 Evaluation Module (EVM) Copyright © 2011, Texas Instruments Incorporated 13 Schematics www.ti.com Figure 9. SN65LVCP114 EVM Schematic, Power Distribution 14 SN65LVCP114 Evaluation Module (EVM) Copyright © 2011, Texas Instruments Incorporated SLLU160 – December 2011 Submit Documentation Feedback Schematics www.ti.com Figure 10. SN65LVCP114 EVM Schematic, USB Interface SLLU160 – December 2011 Submit Documentation Feedback SN65LVCP114 Evaluation Module (EVM) Copyright © 2011, Texas Instruments Incorporated 15 Bill of Materials 9 www.ti.com Bill of Materials Table 5. SN65LVCP114 EVM Bill of Materials Reference Value Part Part Number Manufacturer C1–C12, C22, C29–C45 0.1 µF 0201 CAP LMK063BJ104KP-F Taiyo Yuden C14 47 µF 1210 CAP EMK325BJ476MM-T Taiyo Yuden C15 22 µF 1206 CAP EMK316BJ226ML-T Taiyo Yuden C46–C49, C52, C53, C55, C59-C61 0.1 µF 0402 CAP C1005X5R1E104K TDK Corporation C50, C51, C56 1 µF 0402 CAP LMK105BJ105KV-F Taiyo Yuden C54 10 µF 0603 CAP C1608X5R1A106M TDK Corporation C57, C58 22 pF 0402 CAP C0402COG500-220JNE Venkel D1, D4 LED - GREEN C170 HSMG-C170 Avago Technologies D2 LED - RED C170 SML-LXT0805IW-TR Lumex Opto/Components D3 LED - ORANGE C170 HSMD-C170 Avago Technologies JMP1, JMP2, JMP5, JMP7, JMP26 1X3 0.1" HTSW-150-08-G-S Samtec JMP3, JMP6, JMP8, JMP10, JMP13, JMP16 1X4T 0.1" HTSW-150-08-G-S Samtec JMP35 2X2 0.1x0.1" HTSW-150-08-G-D Samtec J1–J12 Edge Mount SMA CON_02K243-40M 32K243-40ML5 Rosenberger J13 USB - B Type B Type USB-B-S-F-B-TH Samtec P1, P2 Banana Plug - Metal 4 mm 108-0740-001 Emerson Network Power Q1, Q2 NPN SOT23 MMBT4401 Fairchild Semiconductor R1–R4, R6-R8, R10–R15, R18, R19, R23, R27, R28, R32, R36, R37, R41, R51, R58, R65, R66, R71, R88–R90, R99–R104 4.99 KΩ 0402 RES RG1005P-4991-B-T5 Susumu Co., Ltd. R9 1.2 KΩ 0402 RES ERJ-XGNJ122Y Panasonic - ECG R57, R59, R63, R83 100 Ω 0402 RES RC0402FR-07100RL Yageo R60 52.3 KΩ 0402 RES ERJ-2RKF5232X Panasonic - ECG R61, R62, R68, R69, R73, R78 100 KΩ 0402 RES RC0402FR-07100KL Yageo R64 30.1 KΩ 0402 RES ERJ-2RKF3012X Panasonic - ECG R67 49.9 Ω 0402 RES RC0402FR-0749R9L Yageo R70, R76 DNI_0 Ω 0402 RES ERJ-2GE0R00X Panasonic - ECG R72 15 KΩ 0402 RES ERJ-2RKF1502X Panasonic - ECG R74, R75, R105, R106 4.02 KΩ 0402 RES CRCW04024K02FKED Vishay/Dale R77, R79 0.0 (Zero Ohm) 0402 RES RC0402JR-070RL Yageo R80, R97, R98 1.5 KΩ 0402 RES RG1005P-152-B-T5 Susumu Co., Ltd. 16 SLLU160 – December 2011 Submit Documentation Feedback SN65LVCP114 Evaluation Module (EVM) Copyright © 2011, Texas Instruments Incorporated Bill of Materials www.ti.com Table 5. SN65LVCP114 EVM Bill of Materials (continued) Reference Value Part Part Number Manufacturer R81, R82 33 Ω 0402 RES RR0510R-330-D Susumu Co., Ltd. R84 1 MΩ 0402 RES RMCF0402FT1M00 STACKPOLE ELEC. INC. R85–R87, R91–R96 4.99 KΩ_DNI 0402 RES RG1005P-4991-B-T5 Susumu Co., Ltd. SW1 Momentary Push-Button Switch 6.00 mm x 6.00 mm EVQ-PBE05R Panasonic - ECG SW2 1 PIN DIP SMD SMT SDA01H0SB ITT Cannon - C&K U1 LVCP114_ZJA 197pin_0.8 mm pitch BGA SN65LVCP114ZJA Texas Instruments U2 DUAL NPN SOT-23-6 ZXTD09N50DE6TA Zetex Inc U4 Voltage Supervisor with Manual Reset SOT-23-5 TPS3125J18DBVR Texas Instruments U5 USB Microcontroller 64-LQFP TUSB3210PM Texas Instruments U6 Bidirectional Level Shifter 20-TSSOP TXB0108PWR Texas Instruments U7 512Kb EEPROM 8-SOIC 24LC512-I/SM Microchip Technology U8 Single Output LDO 8-SON TPS73701DRB Texas Instruments X1 12.00 MHz Crystal SMD ECS-120-32-5PVX ECS Inc #4-40 Machine Screw H703-ND Digikey #4-40 Rounded Thread 2029K-ND Digikey SLLU160 – December 2011 Submit Documentation Feedback SN65LVCP114 Evaluation Module (EVM) Copyright © 2011, Texas Instruments Incorporated 17 Board Layout 10 www.ti.com Board Layout Figure 11. SN65LVCP114 EVM PCB Layer Construction NOTE: Always consult your board manufacturer for their process/design requirements to ensure the desired impedance is achieved. 18 SN65LVCP114 Evaluation Module (EVM) Copyright © 2011, Texas Instruments Incorporated SLLU160 – December 2011 Submit Documentation Feedback Board Layout www.ti.com Figure 12. SN65LVCP114 Board Layout: Top Signal (Layer 1 of 6) SLLU160 – December 2011 Submit Documentation Feedback SN65LVCP114 Evaluation Module (EVM) Copyright © 2011, Texas Instruments Incorporated 19 Board Layout www.ti.com Figure 13. SN65LVCP114 Board Layout: Internal Ground (Layer 2 of 6) 20 SN65LVCP114 Evaluation Module (EVM) Copyright © 2011, Texas Instruments Incorporated SLLU160 – December 2011 Submit Documentation Feedback Board Layout www.ti.com Figure 14. SN65LVCP114 Board Layout: Internal Power (Layer 3 of 6) SLLU160 – December 2011 Submit Documentation Feedback SN65LVCP114 Evaluation Module (EVM) Copyright © 2011, Texas Instruments Incorporated 21 Board Layout www.ti.com Figure 15. SN65LVCP114 Board Layout: Internal Signal (Layer 4 of 6) 22 SN65LVCP114 Evaluation Module (EVM) Copyright © 2011, Texas Instruments Incorporated SLLU160 – December 2011 Submit Documentation Feedback Board Layout www.ti.com Figure 16. SN65LVCP114 Board Layout: Internal Ground (Layer 5 of 6) SLLU160 – December 2011 Submit Documentation Feedback SN65LVCP114 Evaluation Module (EVM) Copyright © 2011, Texas Instruments Incorporated 23 Board Layout www.ti.com Figure 17. SN65LVCP114 Board Layout: Bottom Signal (Layer 6 of 6) 24 SN65LVCP114 Evaluation Module (EVM) Copyright © 2011, Texas Instruments Incorporated SLLU160 – December 2011 Submit Documentation Feedback www.ti.com Appendix A Jumper Shunt Settings The table below shows the different shunt settings of the 3 and 4 pin jumpers on the EVM. Appendix B Typical Evaluation Setups Figure 18. Receive Side Use Case SLLU160 – December 2011 Submit Documentation Feedback Jumper Shunt Settings Copyright © 2011, Texas Instruments Incorporated 25 Appendix B www.ti.com Figure 19. Transmit Side Use Case Figure 20. Combined Bus Extension Use Case 26 Typical Evaluation Setups Copyright © 2011, Texas Instruments Incorporated SLLU160 – December 2011 Submit Documentation Feedback EVALUATION BOARD/KIT/MODULE (EVM) ADDITIONAL TERMS Texas Instruments (TI) provides the enclosed Evaluation Board/Kit/Module (EVM) under the following conditions: The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claims arising from the handling or use of the goods. Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30 days from the date of delivery for a full refund. THE FOREGOING LIMITED WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES. Please read the User's Guide and, specifically, the Warnings and Restrictions notice in the User's Guide prior to handling the product. This notice contains important safety information about temperatures and voltages. For additional information on TI's environmental and/or safety programs, please visit www.ti.com/esh or contact TI. No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, or combination in which such TI products or services might be or are used. TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not exclusive. TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. REGULATORY COMPLIANCE INFORMATION As noted in the EVM User’s Guide and/or EVM itself, this EVM and/or accompanying hardware may or may not be subject to the Federal Communications Commission (FCC) and Industry Canada (IC) rules. For EVMs not subject to the above rules, this evaluation board/kit/module is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end product fit for general consumer use. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC or ICES-003 rules, which are designed to provide reasonable protection against radio frequency interference. Operation of the equipment may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may be required to correct this interference. General Statement for EVMs including a radio User Power/Frequency Use Obligations: This radio is intended for development/professional use only in legally allocated frequency and power limits. Any use of radio frequencies and/or power availability of this EVM and its development application(s) must comply with local laws governing radio spectrum allocation and power limits for this evaluation module. It is the user’s sole responsibility to only operate this radio in legally acceptable frequency space and within legally mandated power limitations. Any exceptions to this are strictly prohibited and unauthorized by Texas Instruments unless user has obtained appropriate experimental/development licenses from local regulatory authorities, which is responsibility of user including its acceptable authorization. For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant Caution This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment. FCC Interference Statement for Class A EVM devices This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instruction manual, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his own expense. FCC Interference Statement for Class B EVM devices This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures: • Reorient or relocate the receiving antenna. • Increase the separation between the equipment and receiver. • Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. • Consult the dealer or an experienced radio/TV technician for help. For EVMs annotated as IC – INDUSTRY CANADA Compliant This Class A or B digital apparatus complies with Canadian ICES-003. Changes or modifications not expressly approved by the party responsible for compliance could void the user’s authority to operate the equipment. Concerning EVMs including radio transmitters This device complies with Industry Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device. Concerning EVMs including detachable antennas Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser) gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for successful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna types listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated. Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited for use with this device. Cet appareil numérique de la classe A ou B est conforme à la norme NMB-003 du Canada. Les changements ou les modifications pas expressément approuvés par la partie responsable de la conformité ont pu vider l’autorité de l'utilisateur pour actionner l'équipement. Concernant les EVMs avec appareils radio Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est autorisée aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement. Concernant les EVMs avec antennes détachables Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage radioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope rayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante. Le présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le manuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne non inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de l'émetteur. SPACER SPACER SPACER SPACER SPACER SPACER SPACER SPACER 【Important Notice for Users of this Product in Japan】 】 This development kit is NOT certified as Confirming to Technical Regulations of Radio Law of Japan If you use this product in Japan, you are required by Radio Law of Japan to follow the instructions below with respect to this product: 1. 2. 3. Use this product in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for Enforcement of Radio Law of Japan, Use this product only after you obtained the license of Test Radio Station as provided in Radio Law of Japan with respect to this product, or Use of this product only after you obtained the Technical Regulations Conformity Certification as provided in Radio Law of Japan with respect to this product. Also, please do not transfer this product, unless you give the same notice above to the transferee. Please note that if you could not follow the instructions above, you will be subject to penalties of Radio Law of Japan. Texas Instruments Japan Limited (address) 24-1, Nishi-Shinjuku 6 chome, Shinjuku-ku, Tokyo, Japan http://www.tij.co.jp 【ご使用にあたっての注】 本開発キットは技術基準適合証明を受けておりません。 本製品のご使用に際しては、電波法遵守のため、以下のいずれかの措置を取っていただく必要がありますのでご注意ください。 1. 2. 3. 電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用いただく。 実験局の免許を取得後ご使用いただく。 技術基準適合証明を取得後ご使用いただく。 なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。 　　　上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。 日本テキサス・インスツルメンツ株式会社 東京都新宿区西新宿６丁目２４番１号 西新宿三井ビル http://www.tij.co.jp SPACER SPACER SPACER SPACER SPACER SPACER SPACER SPACER SPACER SPACER SPACER SPACER SPACER SPACER SPACER SPACER EVALUATION BOARD/KIT/MODULE (EVM) WARNINGS, RESTRICTIONS AND DISCLAIMERS For Feasibility Evaluation Only, in Laboratory/Development Environments. Unless otherwise indicated, this EVM is not a finished electrical equipment and not intended for consumer use. It is intended solely for use for preliminary feasibility evaluation in laboratory/development environments by technically qualified electronics experts who are familiar with the dangers and application risks associated with handling electrical mechanical components, systems and subsystems. It should not be used as all or part of a finished end product. Your Sole Responsibility and Risk. You acknowledge, represent and agree that: 1. 2. 3. 4. You have unique knowledge concerning Federal, State and local regulatory requirements (including but not limited to Food and Drug Administration regulations, if applicable) which relate to your products and which relate to your use (and/or that of your employees, affiliates, contractors or designees) of the EVM for evaluation, testing and other purposes. You have full and exclusive responsibility to assure the safety and compliance of your products with all such laws and other applicable regulatory requirements, and also to assure the safety of any activities to be conducted by you and/or your employees, affiliates, contractors or designees, using the EVM. Further, you are responsible to assure that any interfaces (electronic and/or mechanical) between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electrical shock hazard. You will employ reasonable safeguards to ensure that your use of the EVM will not result in any property damage, injury or death, even if the EVM should fail to perform as described or expected. You will take care of proper disposal and recycling of the EVM’s electronic components and packing materials. Certain Instructions. It is important to operate this EVM within TI’s recommended specifications and environmental considerations per the user guidelines. Exceeding the specified EVM ratings (including but not limited to input and output voltage, current, power, and environmental ranges) may cause property damage, personal injury or death. If there are questions concerning these ratings please contact a TI field representative prior to connecting interface electronics including input power and intended loads. Any loads applied outside of the specified output range may result in unintended and/or inaccurate operation and/or possible permanent damage to the EVM and/or interface electronics. Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative. During normal operation, some circuit components may have case temperatures greater than 60°C as long as the input and output are maintained at a normal ambient operating temperature. These components include but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors which can be identified using the EVM schematic located in the EVM User's Guide. When placing measurement probes near these devices during normal operation, please be aware that these devices may be very warm to the touch. As with all electronic evaluation tools, only qualified personnel knowledgeable in electronic measurement and diagnostics normally found in development environments should use these EVMs. Agreement to Defend, Indemnify and Hold Harmless. You agree to defend, indemnify and hold TI, its licensors and their representatives harmless from and against any and all claims, damages, losses, expenses, costs and liabilities (collectively, "Claims") arising out of or in connection with any use of the EVM that is not in accordance with the terms of the agreement. This obligation shall apply whether Claims arise under law of tort or contract or any other legal theory, and even if the EVM fails to perform as described or expected. Safety-Critical or Life-Critical Applications. If you intend to evaluate the components for possible use in safety critical applications (such as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, such as devices which are classified as FDA Class III or similar classification, then you must specifically notify TI of such intent and enter into a separate Assurance and Indemnity Agreement. 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