SN65LVCP15PW

SN65LVCP15 www.ti.com SLLS875B – OCTOBER 2008 – REVISED OCTOBER 2013 Link Replicator for Fibre Channel, Gigabit Ethernet, and HDTV Data Rates Check for Samples: SN65LVCP15 FEATURES 1 • • • • • • Replicates Serial Links Such as Fibre Channel, Gigabit Ethernet, and HDTV Links T11 Fibre Channel Compliant at 1.0634 Gb/s IEEE802.3-2005 Gigabit Ethernet Compliant at 1.25 Gb/s (1000Base-X) Support for SMPTE-292M Data Rate at 1.485 Gb/s Compatible With VSC7132-01 No External Components Required • • • • 0.455 W Maximum Power Dissipation 3.3 V Power Supply 28-Pin, 4,4 mm × 9,7 mm TSSOP Package Footprint Compatible with VSC7132 APPLICATIONS • • Test Equipment Gigabit Ethernet and Fibre Channel Switches/Repeaters DESCRIPTION The SN65LVCP15 is a high performance serial link mux for use in Fibre Channel (1.0625 Gb/s), Gigabit Ethernet (1.25 Gb/s), and other high speed interface applications. A common application involves a serializer/deserializer (SerDes), such as the TLK2201B, which would normally be connected to the IN± and OUT± ports in order to provide duplicate set of links on the IN0/OUT0 and IN1/OUT1 ports. This type of application is often used to implement high speed test ports that can be monitored without affecting the serial data stream of the application. A popular application is in Line Cards, that use serial links from a SerDes like TLK2201B (SLLS585), where the SN65LVCP15 provides redundant, hot-swappable links to redundant Switch Fabric Cards. During normal operation, IN is sent to both OUT0 and OUT1 whose buffers are enabled when OE0 and OE1 are HIGH. OUT0 can select between IN and IN1. OUT1 can select between IN and IN0. OUT can select between IN0 and IN1. In Link Replicator applications, such as the Line Card to Switch Card links, IN is transmitted to both OUT0 and OUT1 which either IN0 or IN1 is selected at OUT. In host Adapter applications, IN goes to OUT0 (an internal connector) which returns data and IN0. IN0 is looped to OUT1 (an external connector) which returns data on IN1 and then back to the SerDes on OUT. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008–2013, Texas Instruments Incorporated SN65LVCP15 SLLS875B – OCTOBER 2008 – REVISED OCTOBER 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION ORDERABLE PART NUMBER DESCRIPTION SN65LVCP15PW (1) 28-Pin TSSOP, 4,4 mm × 9,7 mm Body (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) VDD Power supply voltage, TTL VIN(P) DC input voltage, PECL VIN(T) DC input voltage, TTL VIN(TTL) DC voltage applied to outputs for high output state ESD Electrostatic discharge voltage (human body model) TJA Junction to Ambient Thermal Resistance (Assumes High K Board) (1) VALUE UNIT 0.5 to 4.0 V –0.5 to VDD +0.5 V –0.5 to +5.5 V –0.5 to VDD +0.5 V 2 kV 61.7 °C/W Stresses listed under absolute maximum ratings may be applied to devices one at a time without causing permanent damage. Functionality at or above the values listed is not implied. Exposure to theses values for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS VDD MIN MAX Power supply voltage 3.14 3.47 UNIT V Operating temperature range –40 85 °C AC ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN 1 TYP MAX UNIT 1.5 Gb/s f Operating frequency range t1 Flow-through propagation delay Delay from any input to any output tr, tf Serial data rise and fall time 20% to 80% tDJ Deterministic jitter added to serial input 1 Gb/s to 1.25 Gb/s. Measured on K28.5+, K28.5– pattern 35 1.25 Gb/s to 1.5 Gb/s. Measured on K28.5+, K28.5– pattern 45 1 ns 300 ps ps pp IN± IN0± IN1± OUT± OUT0± OUT1± t1 t1 tJ Figure 1. Timing Waveforms 2 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: SN65LVCP15 SN65LVCP15 www.ti.com SLLS875B – OCTOBER 2008 – REVISED OCTOBER 2013 DC ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIH(TTL) Input HIGH voltage 2 5.5 VIL(TTL) Input LOWS voltage 0 0.8 V IIH(TTL) Input HIGH current VIN = 2.4 V -100 100 μA IIL(TTL) Input HIGH current VIN = 0.5 V –100 100 μA VDD Supply voltage VDD = 3.30 V ±5% 3.14 3.47 V IDD Supply current Outputs open, VDD = VDD max 131 mA PD Power dissipation Outputs open, VDD = VDD max 455 mW ΔVIN Receiver differential peak-to-peak input sensitivity (IN, IN0, IN1) AC coupled, Internally biased at VDD/2 300 2600 mVPP 50 Ω to VDD – 2 V 1000 2200 mVPP 75 Ω to VDD – 2 V 1200 2200 mVPP ΔVOUT50 ΔVOUT75 Output differential peak-to-peak voltage swing (OUT, OUT0, OUT1) V APPLICATION EXAMPLE Signal Re-Driver Example 0.01 mF 0.01 mF TX+ I+ R O1+ RX+ RT RT 0.01 mF 0.01 mF TX- I- RX- O1- R SN65LVCP15 TLK2201B TLK2201B 0.01 mF RX+ 0.01 mF O+ I1+ RT TX+ R RT 0.01 mF RX- 0.01 mF O- I1- TXR R is 150 Ω for both 100 Ω differential or 150 Ω differential traces. RT matches the differential impedance of the link. For optimal signal integrity performance, A/C coupling is recommended. Figure 2. TLK2201B and SN65LVCP15 Interconnect Signal Repeating Example TLK2201B TLK2201B SN65LVCP15 TX TX RX RX TX RX TLK2201B SerDes Figure 3. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: SN65LVCP15 3 SN65LVCP15 SLLS875B – OCTOBER 2008 – REVISED OCTOBER 2013 www.ti.com PACKAGE INFORMATION – PIN DIAGRAM SN65LVCP15 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 VDDP0 OE0 MUX VSS IN+ INVSS OE1 VDD VDDP OUT+ OUTVDDP VSS 28 27 26 25 24 23 22 21 20 19 18 17 16 15 OUT0+ OUT0VDDP0 VSS IN0+ IN0VDDP1 OUT1+ OUT1VDDP1 IN1+ IN1MUX0 MUX1 PIN FUNCTIONS PIN TYPE LEVEL IN+, IN– IN0+, IN0– IN1+, IN1– I PECL Differential (biased to VDD/2) High-speed serial inputs 11, 12 28, 27 21, 20 OUT+, OUT– OUT0+, OUT0– OUT1+, OUT1– O PECL Differential high-speed serial outputs 2 8 OE0 OE1 I TTL OE0/OE1 enables OUT0/OUT1 when HIGH. When LOW, OUTx is powered down and both OUTx+ and OUTx– float HIGH. NO. NAME 5, 6 24, 23 18, 17 DESCRIPTION 3 MUX I TTL Determines source of OUT. Selects either IN0 (LOW) or IN1 (HIGH). 15 MUX1 I TTL Determines source of OUT1. Selects either IN (HIGH) or IN0 (LOW). 16 MUX0 I TTL Determines source of OUT0. Selects either IN (LOW) or IN1 (HIGH). 9 VDD Pwr 3.3 V power supply for digital logic 10, 13 1, 26 19, 22 VDDP VDDP0 VDDP1 Pwr High-speed output power supply: 3.3 V supply for PECL drivers. VDDP0 is for OUT0, VDDP is for OUT, and VDDP1 is for OUT1. 4, 7 14, 25 VSS Pwr Ground MOISTURE SENSITIVITY LEVEL This device is rated moisture sensitivity level 3 or better as specified in the joint IPC and JEDEC standard IPC/JEDEC J-STD-020. For more information, see the IPC and JEDEC standards. 4 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: SN65LVCP15 SN65LVCP15 www.ti.com SLLS875B – OCTOBER 2008 – REVISED OCTOBER 2013 REVISION HISTORY Changes from Original (October 2008) to Revision A • Page Deleted IO - DC output HIGH current, PECL from the ABSOLUTE MAXIMUM RATINGS table ......................................... 2 Changes from Revision A (November 2008) to Revision B • Page Changed Case operating temperature To: Operating temperature range and the range From: 0 to 85°C To: –40 to 85°C ...................................................................................................................................................................................... 2 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: SN65LVCP15 5 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN65LVCP15PW ACTIVE TSSOP PW 28 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVCP15 SN65LVCP15PWR ACTIVE TSSOP PW 28 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVCP15 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of