SN65LVCP408
www.ti.com
SLLS842A – JUNE 2009 – REVISED JUNE 2010
Gigabit 8 x 8 CROSSPOINT SWITCH
Check for Samples: SN65LVCP408
FEATURES
DESCRIPTION
•
•
The SN65LVCP408 is a 8 × 8 non-blocking
crosspoint switch in a flow-through pin-out allowing
for ease in PCB layout. VML signaling is used to
achieve a high-speed data throughput while using low
power. Each of the output drivers includes a 8:1
multiplexer to allow any input to be routed to any
output. Internal signal paths are fully differential to
achieve the high signaling speeds while maintaining
low signal skews. The SN65LVCP408 incorporates
100-Ω termination resistors for those applications
where board space is a premium. Built-in transmit
pre-emphasis and receive equalization for superior
signal integrity performance.
23
•
•
•
•
•
•
•
•
•
•
Up to 4.25 Gbps Operation
Non-Blocking Architecture Allows Each
Output to be Connected to Any Input
30 ps of Deterministic Jitter
Selectable Transmit Pre-Emphasis Per Lane
Selectable Receive Equalization
Available Packaging 64 Pin QFP
Propagation Delay Times: 500 ps Typical
Inputs Electrically Compatible With
CML Signal Levels
Operates From a Single 3.3-V Supply
Ability to 3-STATE Outputs
Integrated Termination Resistors
I2C™ Control Interface
The SN65LVCP408 is characterized for operation
from –40°C to 85°C. (See operating free air condition
requirements)
VCC
I2C_EN
SWT
GND
0Y
0Z
VCC
1Y
1Z
GND
2Y
2Z
VCC
3Y
3Z
GND
1
APPLICATIONS
•
•
•
•
•
Clock Buffering/Clock MUXing
Wireless Base Stations
High-Speed Network Routing
Telecom/Datacom
XAUI 802.3ae Protocol Backplane Redundancy
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
GND
VCC
RESN
GND
0A
0B
VCC
1A
1B
GND
2A
2B
VCC
3A
3B
VBB
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
ADDR2
ADDR1
SDA
SCL
GND
4Y
4Z
VCC
5Y
5Z
GND
6Y
6Z
VCC
7Y
7Z
GND
4A
4B
VCC
5A
5B
GND
6A
6B
VCC
7A
7B
GND
VCC
EQ
PRE
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
I2C is a trademark of Philips Electronics.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2010, Texas Instruments Incorporated
SN65LVCP408
SLLS842A – JUNE 2009 – REVISED JUNE 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ADDR1
ADDR2
SCL
SDA
RESN
I2C_EN
I 2C
IF
Registers
LOGIC DIAGRAM
SWT
24
2x 1
MUX
24
24
VBB
RT
EQ
0A
0B
RT
3
EQ
PRE
2
0Y
0Z
8x1
MUX
3-State_0
3
VBB
PRE
2
RT
EQ
7A
7B
7Y
8x1
MUX
RT
7Z
EQ
3-State_7
8x 8
MUX
2
A.
VBB: Receiver input internal biasing voltage (allows ac coupling)
B.
RT: Internal 50-Ω receiver termination (100-Ω differential)
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SLLS842A – JUNE 2009 – REVISED JUNE 2010
PIN FUNCTIONS
Pin
NAME
NO.
TYPE
DESCRIPTION
Differential Inputs (with
50-Ω termination to Vbb)
xA=P; xB=N
Line Side Differential Inputs CML compatible
Differential Output xY=P;
xZ=N
Switch Side Differential Outputs. VML
Inputs
I2C Control Interface (SCL: Clock, SDA: Data, ADDR:
Address)
High Speed I/O
xA
5, 8, 11, 14, 18, 21, 24 ,27
xB
6, 9, 12, 15, 19, 22, 25, 28
xY
34, 37, 40 43, 51, 54, 57, 60
xZ
33, 36, 39, 42, 50, 53, 56, 59
Control Signals
SCL
45
SDA
46
ADDR1
47
ADDR2
48
EQ
31
Input
Equalization setting when I2C is not enabled. EQ=0 for 13dB
and setting EQ=1 for 9dB.
PRE
32
Input
Pre-Emphasis setting when I2C is not enabled. PRE=0 for 0
dB and PRE=1 for 6 dB
I2C_EN
63
Input
Enables I2C control interface I2C_EN=1 for enable; When
EN=0 then the PRE and EQ pins are used to set the
Pre-Emphasis and Equalization settings rather than the I2C
register map. When EN=0 the I2C register map is still open
for read and write operations.
SWT
62
Input
Enable switch event when toggled
RESN
3
Input (Active Low)
Configuration Reset. Resets I2C register space (Active Low).
Note upon device startup the RESN pin must be driven low
to reset the device registers.
Power Supply 3.3v±5%
Power Supply
VCC
2, 7, 13, 20, 26, 30, 35, 41, 52,
58, 64
Power
GND
1,4, 10, 17, 23, 29 , 38, 44, 49,
55, 61
Ground
VBB
16
PowerPAD™
Input
Receiver input biasing voltage
Ground
The ground center pad of the package must be connected to
GND plane.
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SN65LVCP408
SLLS842A – JUNE 2009 – REVISED JUNE 2010
www.ti.com
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
VCC
IN+
RT(SE)
= 50 W
Gain
Stage
+ EQ
VCC
RBBDC
RT(SE)
= 50 W
IN−
VBB
ESD
LineEndTermination
Self−Biasing Network
Figure 1. Equivalent Input Circuit Design
OUT+
49.9 W
OUT−
49.9 W
VOCM
1 pF
Figure 2. Common-Mode Output Voltage Test Circuit
AVAILABLE OPTIONS (1)
(1)
(2)
TA
DESCRIPTION
–40°C to 85°C
Serial multiplexer
PACKAGED DEVICE (2)
PAP (64 pin)
SN65LVCP408
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
The package is available taped and reeled. Add an R suffix to device types (e.g., SN65LVCP408PAP). Temperature range assumes 1
m/s airflow.
PACKAGE THERMAL CHARACTERISTICS
PACKAGE THERMAL CHARACTERISTICS (1)
qJA (junction-to-ambient)
(1)
4
NOM
100LFM airflow is required otherwise a 4x4 thermal via array must be
implemented with 6 layer or greater PCB.
21.2
UNIT
°C/W
See application note SPRA953 for a detailed explanation of thermal parameters (http://www-s.ti.com/sc/psheets/spra953/spra953.pdf).
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SLLS842A – JUNE 2009 – REVISED JUNE 2010
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
UNIT
VCC
Supply voltage range
(2)
–0.5 V to 6 V
Control inputs, all outputs
Voltage range
ESD
TJ
Receiver inputs
Human Body Model (3)
Charged-Device Model
–0.5 V to (VCC + 0.5 V)
–0.5 V to 4 V
All pins
(4)
6 kV
All pins
Maximum junction temperature
500 V
See Package Thermal Characteristics Table
Moisture sensitivity level
2
Reflow temperature package soldering, 4 seconds
(1)
(2)
(3)
(4)
260°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
Tested in accordance with JEDEC Standard 22, Test Method A114-A.
Tested in accordance with JEDEC Standard 22, Test Method C101.
RECOMMENDED OPERATING CONDITIONS
MIN
dR
Operating data rate
VCC
Supply voltage
VCC(N)
Supply voltage noise amplitude
TJ
Junction temperature
TA
Operating free-air temperature
3.135
(1)
NOM
3.3
MAX
UNIT
4.25
Gbps
3.465
10 Hz to 2.125 GHz
Assumes 4x4 thermal via array is
implemented with 6 layer or greater PCB
otherwise 100LFM airflow is required.
V
20
mV
125
°C
-40
85
°C
100
1750
mVPP
100
1560
mVPP
100
1000
mVPP
1.5
|V |
1.6 V * ID
CC
2
V
DIFFERENTIAL INPUTS
dR(in) ≤ 4.25 Gbps
Receiver peak-to-peak differential input
1.25 Gbps < dR(in) ≤ 4.25 Gbps
(2)
voltage
dR(in) > 4.25 Gbps
VID
VICM
Receiver common-mode
input voltage
Note: for best jitter performance ac
coupling is recommended.
CONTROL INPUTS
VIH
High-level input voltage
2
VCC + 0.3
V
VIL
Low-level input voltage
–0.3
0.8
V
120
Ω
DIFFERENTIAL OUTPUTS
RL
(1)
(2)
Differential load resistance
80
100
Maximum free-air temperature operation is allowed as long as the device maximum junction temperature is not exceeded.
Differential input voltage VID is defined as | IN+ – IN– |.
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SLLS842A – JUNE 2009 – REVISED JUNE 2010
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ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
DIFFERENTIAL INPUTS
VIT+
Positive going differential
input high threshold
VIT–
Negative going differential
input low threshold
A(EQ)
Equalizer gain
RT(D)
Termination resistance,
differential
VBB
Open-circuit Input voltage
(input self-bias voltage)
R(BBDC)
Biasing network dc
impedance
R(BBAC)
Biasing network ac
impedance
50
–50
at 1.875 GHz (EQ=1)
mV
9
80
AC-coupled inputs
mV
100
dB
120
Ω
1.6
V
30
kΩ
375 MHz
42
2.125 GHz
8.4
Ω
DIFFERENTIAL OUTPUTS
VODH
High-level output voltage
650
mVPP
VODL
Low-level output voltage
–650
mVPP
VODB
Output differential voltage
without preemphasis (2)
VOCM
Output common mode voltage
ΔVOC(SS)
Change in steady-state
common-mode output voltage
between logic states
RL = 100 Ω ±1%, Pre-Emph=0 dB
1000
V
ODB(PP)
1500
1.8
See Figure 2
mVPP
V
1
Output preemphasis voltage
ratio,
V(PE)
1300
mV
0
3
RL = 100 Ω ±1%; x = L or S;
See Figure 3
dB
6
VODPE(PP)
10
t(PRE)
Preemphasis duration
measurement
Output preemphasis is set to 10 dB during test
Measured with a 100-MHz clock signal;
RL = 100 Ω ±1%, See Figure 4
175
ps
ro
Output resistance
Differential on-chip termination between OUT+ and
OUT–
100
Ω
CONTROL INPUTS
IIH
High-level Input current
VIN = VCC
IIL
Low-level Input current
VIN = GND
R(PU)
Pullup resistance
5
-125
mA
-90
mA
35
kΩ
POWER CONSUMPTION
PD
Device power dissipation
All outputs terminated 100 Ω
PZ
Device power dissipation in
3-State
All outputs in 3-state
ICC
Device current consumption
All outputs terminated 100 Ω
(1)
(2)
6
PRBS 27-1
pattern at 4.25
Gbps
1.52
W
864
mW
440
mA
All typical values are at TA = 25°C and VCC = 3.3 V supply unless otherwise noted. They are for reference purposes and are not
production tested.
Differential output voltage V(ODB) is defined as | OUT+ – OUT– |.
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SWITCHING CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
MULTIPLEXER
t(SM)
Multiplexer switch time
Multiplexer to valid output
15
ns
0.5
0.7
ns
0.5
0.7
ns
DIFFERENTIAL OUTPUTS
Low-to-high propagation
delay
tPLH
tPHL
High-to-low propagation
delay
tr
Rise time
tf
Fall time
tsk(p)
Pulse skew, | tPHL – tPLH | (2)
tsk(o)
Output skew (3)
Propagation delay input to output, See Figure 6
90
20% to 80% of VO(DB); Test Pattern: 100-MHz clock signal;
See Figure 5 and Figure 8
ps
90
All outputs terminated with 100 Ω
25
(4)
ps
20
ps
75
ps
tsk(pp)
Part-to-part skew
150
ps
tzd
3-State switch time to
Disable
Assumes 50 Ω to Vcm and 150 pF load on each output;
Tested using I2C
30
ns
tze
3-State switch time to
Enable
Assumes 50 Ω to Vcm and 150 pF load on each output;
Tested using I2C
20
ns
–15
RJ
Device random jitter, rms
See Figure 8 for test circuit. BERT setting 10
Alternating 10-pattern.
0 dB preemphasis
Intrinsic deterministic device
See Figure 8 for the test
jitter (5), peak-to-peak
circuit.
DJ
(1)
(2)
(3)
(4)
(5)
(6)
0 dB preemphasis
Absolute deterministic
See Figure 8 for the test
output jitter (6), peak-to-peak
circuit.
PRBS 27-1
pattern
PRBS 27-1
pattern
0.8
4.25 Gbps
2 ps-rms
30
1.25Gbps;
EQ=13dB
Over 25-inch
FR4 trace
4.25 Gbps;
EQ=13dB
Over FR4 trace
2-inch to 43
inches long
ps
15
ps
40
All typical values are at 25°C and with 3.3 V supply unless otherwise noted.
tsk(p) is the magnitude of the time difference between the tPLH and tPHL of any output of a single device.
tsk(o) is the magnitude of the time difference between the tPLH and tPHL of any two outputs of a single device.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
The SN65LVCP408 built-in passive input equalizer compensates for ISI. For a 25-inch FR4 transmission line with 8-mil trace width, the
LVCP408 typically reduces jitter by 29 ps from the device input to the device output.
Absolute deterministic output jitter reflects the deterministic jitter measured at the SN65LVCP408 output. The value is a real measured
value with a Bit error tester as described in Figure 8. The absolute DJ reflects the sum of all deterministic jitter components accumulated
over the link: DJ(absolute) = DJ(Signal generator) + DJ(transmission line) + DJ(intrinsic(LVCP408)).
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PARAMETER MEASUREMENT INFORMATION
1−bit
1 to N bit
3−dB Preemphasis
VODPE3(pp)
10−dB Preemphasis
VOCM
VODB(PP)
VODPE2(pp)
6−dB Preemphasis
VODPE1(pp)
0−dB Preemphasis
VOH
VOL
Figure 3. Preemphasis and Output Voltage Waveforms and Definitions
1−bit
VODPE3(pp)
10−dB Preemphasis
1 to N bit
VODB(PP)
80%
20%
tPRE
Figure 4. t(PRE) Preemphasis Duration Measurement
80%
80%
VODB
20%
20%
tr
tf
Figure 5. Driver Output Transition Time
8
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PARAMETER MEASUREMENT INFORMATION (continued)
VID = 0 V
IN
t PHLD
t PLHD
VOD = 0 V
OUT
Figure 6. Propagation Delay Input to Output
VA
Clock Input
VID = 0 V
VOD = 0 V
Ideal Output
VB
VY − VZ
1/fo
Period Jitter
1/fo
Cycle-to-Cycle Jitter
Actual Output
Actual Output
VOD = 0 V
VOD = 0 V
VY − VZ
VY − VZ
tc(n)
tc(n)
tc(n +1)
tjit(cc) = | tc(n) − tc(n + 1) |
tjit(pp) = | tc(n) − 1/fo |
Peak-to-Peak Jitter
VA
PRBS Input
VY
PRBS Output
VID = 0 V
VOD = 0 V
VZ
VB
tjit(pp)
A.
All input pulses are supplied by an Agilent 81250 Stimulus System.
B.
The measurement is made with the AgilentParBert measurement software.
Figure 7. Driver Jitter Measurement Waveforms
Pattern
Generator
DC
Block
Coax
DC
Block
Coax
DC
Block
Pre-amp
SMA
SMA
25-inch FR4
(63,5 cm)
Coupled
Transmission Line
400 mVPP
RX
+
EQ
