SN65LVDS1050PWG4

SN65LVDS1050 www.ti.com SLLS343B – APRIL 1999 – REVISED APRIL 2003 HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS FEATURES • • • • • • Typically Meets or Exceeds ANSI TIA/EIA-644-1995 Standard Operates From a Single 2.4-V to 3.6-V Supply Signaling Rates up to 400 Mbit/s Bus-Terminal ESD Exceeds 12 kV Low-Voltage Differential Signaling With Typical Output Voltages of 285 mV and a 100-Ω Load Propagation Delay Times • Driver: 1.7-ns Typical • • • • Receiver: 3.7-ns Typical Driver: 25-mW Typical Receiver: 60-mW Typical Power Dissipation at 200 MHz • Driver: 25-mW Typical • Receiver: 60-mW Typical • • • LVTTL Input Levels Are 5-V Tolerant Receiver Maintains High Input Impedance Receiver Has Open-Circuit Fail Safe • Available in Thin Shink Outline Packaging With 20-mil Lead Pitch SN65LVDS1050PW (Marked as DL1050 or LDS1050) (TOP VIEW) 1B 1A 1R RE 2R 2A 2B GND 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 13 12 DE VCC 1D 1Y 1Z DE 2Z 2Y 2D 10 9 11 2D 2 3 1R 1 4 RE 6 5 7 2R 1Y 1Z 2Y 2Z 1A 1B 2A 2B DRIVER FUNCTION TABLE INPUTS OUTPUTS D DE Y Z L H L H H H H L Open H L H X L Z Z H = high level, L = low level, Z = high impedance, X = don’t care RECEIVER FUNCTION TABLE INPUTS OUTPUT VID = VA - VB RE R VID ≥ 100 mV L H -100 mV < VID < 100 mV L ? VID ≤ -100 mV L L Open L H X H Z DESCRIPTION The SN65LVDS1050 is similar to the SN65LVDS050 except that it is characterized for operation with a lower supply voltage range and packaged in the thin shrink outline package for portable battery-powered applications. 1 14 15 1D H = high level, L = low level, Z = high impedance, X = don’t care The differential line drivers and receivers use low-voltage differential signaling (LVDS) to achieve signaling rates as high as 400 Mbps. The drivers provide a minimum differential output voltage magnitude of 247 mV into a 100-Ω load and receipt of 100-mV signals with up to 1 V of ground potential difference between a transmitter and receiver. The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100-Ω characteristic impedance. The transmission media may be printed-circuit board traces, backplanes, or cables. Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment and other application-specific characteristics. The SN65LVDS1050 is characterized for operation from -40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1999 – 2003, Texas Instruments Incorporated SN65LVDS1050 www.ti.com SLLS343B – APRIL 1999 – REVISED APRIL 2003 EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS VCC VCC VCC 300 kΩ 50 Ω 5Ω 10 kΩ D or RE Input Y or Z Output 50 Ω DE Input 7V 7V 7V 300 kΩ VCC VCC 300 kΩ 300 kΩ 5Ω A Input R Output B Input 7V 7V 2 7V SN65LVDS1050 www.ti.com SLLS343B – APRIL 1999 – REVISED APRIL 2003 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT Supply voltage range, VCC (2) -0.5 V to 4 V Voltage range (D, R, DE, RE) -0.5 V to 6 V Voltage range (Y, Z, A, and B) -0.5 V to 4 V Y, Z, A, B , and GND (3) Electrostatic discharge CLass 3, A:12 kV, B:600 V All terminals Class 3, A:7 kV, B:500 V Continuous power dissipation See Dissipation Rating Table Storage temperature range -65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds (1) (2) (3) 250°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other condition beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages are with respect to network ground terminal. Tested in accordance with MIL-STD-883C Method 3015.7. DISSIPATION RATING TABLE PACKAGE TA≤ 25°C POWER RATING DERATING FACTOR ABOVE TA=25°C TA=85°C POWER RATING PW 774 mW 6.2 mW/°C 402 mW RECOMMENDED OPERATING CONDITIONS (1) MIN NOM MAX UNIT Supply voltage, VCC 2.4 2.7 3.6 V High-level input voltage, VIH 2 0.8 V V Low-level input voltage, VIL Magnitude of differential input voltage, |VID| 0.1 0.6 V Driver output voltage, VOY or VOZ 0 2.4 V 520 mV Magnitude of differential output voltage with disabled driver, |VOD(dis)| Common-mode input voltage, VIC (see Figure 5) V  0 2.4
ID 2 V VCC-0.8 Operating free-air temperature, TA (1) 40 °C 85 The common-mode input voltage, VIC, is not fully 644 compliant when VCC = 2.4 V. DEVICE ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER ICC (1) Supply current TYP (1) MAX UNIT Driver and receiver enabled, No receiver load, Driver RL=100 Ω 12 20 Driver enabled, Receiver disabled, RL=100 Ω 10 16 Driver disabled, Receiver enabled, No load 3 6 Disabled 0.5 1 TEST CONDITIONS MIN mA All typical values are at 25°C and with a 2.7-V supply. 3 SN65LVDS1050 www.ti.com SLLS343B – APRIL 1999 – REVISED APRIL 2003 DRIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS |VOD| Differential output voltage magnitude ∆|VOD| Change in differential output voltage magnitude between logic states VOC(SS) Steady-state common-mode output voltage ∆VOC(SS) Change in steady-state common-mode output voltage between logic states VOC(PP) Peak-to-peak common-mode output voltage IIH High-level input current IIL Low-level input current IOS Short-circuit output current IO(OFF) Off-state output current CIN Input capacitance RL=100Ω, See Figure 1 and Figure 2 DE MIN TYP MAX UNIT 247 285 454 50 1.125 1.37 5 V 50 50 mV 50 150 mV 0.5 20 2 20 0.5 10 2 20 VOY or VOZ=0 V 3 10 VOD=0 V 3 10 See Figure 3 VIH=5 V D DE VIL=0.8 V D mV 50 µA µA mA DE=0 V, VOY=VOZ=0 V DE=V CC, VOY=VOZ=0 V, V CC < 1.5 V -1 1 3 µA pF RECEIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT VITH+ Positive-going differential input voltage threshold VITH- Negative-going differential input voltage threshold VOH High-level output voltage IOH=-8 mA VOL Low-level output voltage IOL=8 mA II Input current (A or B inputs) II(OFF) Power-off input current (A or B inputs) VCC=0 ±20 IIH High-level input current (enables) VIH=5 V ±10 µA IIL Low-level input current (enables) VIL=0.8 V ±10 µA IOZ High-impedance output current VO =0 or 5 V ±10 µA (1) 4 All typical values are at 25°C and with a 2.7-V supply. See Figure 5 and Table 1 100 100 2 V 0.4 VI=0 2 VI=2.4 V 1.2 mV 20 V µA µA SN65LVDS1050 www.ti.com SLLS343B – APRIL 1999 – REVISED APRIL 2003 DRIVER SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER tPLH TEST CONDITIONS MIN Propagation delay time, low-to-high-level output TYP (1) M 1.7 2. 7 AXUNIT ns tPHL Propagation delay time, high-to-low-level output tr Differential output signal rise time tf Differential output signal fall time tsk(p) Pulse skew (|tpHL - tpLH|) 300 tsk(o) Channel-to-channel output skew (2) 150 ps ten Enable time 7.8 10 ns tdis Disable time 6.6 10 ns (1) (2) RL=100Ω, CL=10 pF, See Figure 2 See Figure 4 1.7 3 ns 0.8 1 ns 0.8 1 ns ps All typical values are at 25°C and with a 2.7-V supply. tsk(o) is the maximum delay time difference between drivers on the same device. RECEIVER SWITCHING CHARCTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT tPLH Propagation delay time, low-to-high-level output tPHL Propagation delay time, high-to-low-level output tsk(p) Pulse skew (|tpHL - tpLH|) tr Output signal rise time 0.8 1.5 ns tf Output signal fall time 0.8 1.5 ns tPZH Propagation delay time, high-level-to-high-impedance output 5.4 ns tPZL Propagation delay time, low-level-to-low-impedance output 6.3 ns tPHZ Propagation delay time, high-impedance-to-high-level output 6.1 ns tPLZ Propagation delay time, low-impedance-to-high-level output 6.9 ns (1) CL=10 pF, See Figure 6 See Figure 7 3.7 5.2 ns 3.7 4.5 ns 0.3 ns All typical values are at 25°C and with a 2.7-V supply. 5 SN65LVDS1050 www.ti.com SLLS343B – APRIL 1999 – REVISED APRIL 2003 PARAMETER MEASUREMENT INFORMATION DRIVER IOY Driver Enable Y II A IOZ VOD V VOY Z VI OY
V OZ 2 VOC VOZ Figure 1. Driver Voltage and Current Definitions Driver Enable Y 100 Ω ±1% VOD Input Z CL = 10 pF (2 Places) 2V 1.4 V 0.8 V Input tPHL tPLH 100% 80% Output VOD(H) 0V VOD(L) 20% 0% tf tr All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. Figure 2. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal 6 SN65LVDS1050 www.ti.com SLLS343B – APRIL 1999 – REVISED APRIL 2003 49.9 Ω, ±1% (2 Places) Driver Enable 3V Y Input 0V Z VOC VOC(PP) CL = 10 pF (2 Places) VOC(SS) VOC All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. The measurement of VOC(PP) is made on test equipment with a -3 dB bandwidth of at least 300 MHz. Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage 49.9 Ω, ±1% (2 Places) Y 0.8 V or 2 V Z DE 1.2 V CL = 10 pF (2 Places) VOY VOZ 2V 1.4 V 0.8 V DE VOY or VOZ ten D at 2 V and input to DE 1.2 V 1.15 V ~1 V D at 0.8 V and input to DE tdis VOZ or VOY ten ~1.4 V 1.25 V 1.2 V tdis All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. Figure 4. Driver Enable and Disable Time Circuit and Definitions 7 SN65LVDS1050 www.ti.com SLLS343B – APRIL 1999 – REVISED APRIL 2003 RECEIVER A V IA
V IB VID 2 R VIA VIC B VO VIB Figure 5. Receiver Voltage Definitions Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages APPLIED VOLTAGES (V) RESULTING DIFFERENTIAL INPUT VOLTAGE (mV) RESULTING COMMON-MODE INPUT VOLTAGE (V) VIA VIB VID VIC 1.25 1.15 100 1.2 1.15 1.25 100 1.2 2.4 2.3 100 2.35 2.3 2.4 100 2.35 0.1 0 100 0.05 0 0.1 100 0.05 1.5 0.9 600 1.2 0.9 1.5 600 1.2 2.4 1.8 600 2.1 1.8 2.4 600 2.1 0.6 0 600 0.3 0 0.6 600 0.3 8 SN65LVDS1050 www.ti.com SLLS343B – APRIL 1999 – REVISED APRIL 2003 VID VIA VIB CL 10 pF VO VIA 1.4 V VIB 1V VID 0.4 V 0V –0.4 V tPHL VO tPLH VOH 2.4 V 1.4 V 0.4 V VOL tf tr All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T. Figure 6. Timing Test Circuit and Waveforms 9 SN65LVDS1050 www.ti.com SLLS343B – APRIL 1999 – REVISED APRIL 2003 B 1.2 V 500 Ω A Inputs CL 10 pF RE + – VO VTEST All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T. 2.5 V VTEST A 1V 2V 1.4 V RE 0.8 V tPZL tPZL tPLZ 2.5 V 1.4 V R VOL +0.5 V VOL 0V VTEST A 1.4 V 2V RE 1.4 V 0.8 V tPZH R tPZH VOH –0.5 V tPHZ VOH 1.4 V 0V Figure 7. Enable/Disable Time Test Circuit and Waveforms 10 SN65LVDS1050 www.ti.com SLLS343B – APRIL 1999 – REVISED APRIL 2003 TYPICAL CHARACTERISTICS RECEIVER DISABLED DRIVER OUTPUT CURRENT vs OUTPUT VOLTAGE DRIVER LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 4 VOZ = 0 VCC = 3.3 V, TA = 25°C, DR at 0 V 20 VOL - Low-Level Output Voltage - V I O - Disabled Driver Output Current - mA 25 15 10 5 VOZ = 1.2 0 VOZ = 2.4 -5 -10 VCC = 2.4 V TA = 25°C 3 2 1 -15 -20 0 0.5 1 1.5 2 2.5 0 3 0 VO - Output Voltage - V 2 3 Figure 8. Figure 9. DRIVER HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT RECEIVER LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 3.5 4 3 VCC = 2.4 V TA = 25°C 3 VCC = 2.4 V TA = 25°C VOL - Low-Level Output Votlage - V VOH - High-Level Output Voltage - V 1 IOL - Low-Level Output Current - mA 2.5 2 1.5 1 0.5 0 -4 -3 -2 -1 IOH - High-Level Output Current - mA Figure 10. 0 2 1 0 0 10 20 30 IOL - Low-Level Output Current - mA 40 Figure 11. 11 SN65LVDS1050 www.ti.com SLLS343B – APRIL 1999 – REVISED APRIL 2003 RECEIVER HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT DRIVER HIGH-TO-LOW LEVEL PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 2.5 t PLH - High-To-Low Propagation Delay Time - ns 3 VOH - High-Level Output Voltage - V VCC = 2.4 V TA = 25°C 2 1 0 -50 -40 -10 -30 -20 IOH - High-Level Output Current - mA Figure 12. 12 0 2 VCC = 3.3 V VCC = 2.7 V VCC = 3.6 V 1.5 -50 -30 10 -10 50 30 70 TA - Free-Air Temperature - °C Figure 13. 90 SN65LVDS1050 www.ti.com SLLS343B – APRIL 1999 – REVISED APRIL 2003 RECEIVER HIGH-TO-LOW LEVEL PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 2 VCC = 3.3 V VCC = 2.7 V VCC = 3.6 V 1.5 -50 -30 -10 10 50 30 70 TA - Free-Air Temperature - °C 90 4.5 VCC = 3.3 V 4 VCC = 2.7 V 3.5 VCC = 3.6 V 3 2.5 -50 -30 10 -10 50 30 70 TA - Free-Air Temperature - °C Figure 14. 90 Figure 15. RECEIVER LOW-TO-HIGH LEVEL PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE t PLH - Low-To-High Level Propagation Delay Time - ns t PLH - Low-To-High Propagation Delay Time - ns 2.5 t PLH - High-To-Low Level Propagation Dealy Time - ns DRIVER LOW-TO-HIGH LEVEL PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 4.5 VCC = 2.7 V 4 VCC = 3.3 V 3.5 VCC = 3.6 V 3 2.5 -50 -30 10 -10 50 30 70 TA - Free-Air Temperature - °C 90 Figure 16 13 SN65LVDS1050 www.ti.com SLLS343B – APRIL 1999 – REVISED APRIL 2003 APPLICATION INFORMATION The devices are generally used as building blocks for high-speed point-to-point data transmission. Ground differences are less than 1 V with a low common-mode output and balanced interface for very low noise emissions. Devices can interoperate with RS-422, PECL, and IEEE-P1596. Drivers/Receivers maintain ECL speeds without the power and dual supply requirements. Transmission Distance – m 1000 30% Jitter 100 5% Jitter 10 1 24 AWG UTP 96 Ω (PVC Dielectric) 0.1 100k 1M 10M 100M Data Rate – Hz Figure 17. Data Transmission Distance Versus Rate Fail Safe One of the most common problems with differential signaling applications is how the system responds when no differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in that its output logic state can be indeterminate when the differential input voltage is between -100 mV and100 mV and within its recommended input common-mode voltage range. TI’s LVDS receiver is different in how it handles the open-input circuit situation, however. Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver pulls each line of the signal pair to near VCC through 300-kΩ resistors as shown in Figure 11. The fail-safe feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the output to a high-level, regardless of the differential input voltage. 14 SN65LVDS1050 www.ti.com SLLS343B – APRIL 1999 – REVISED APRIL 2003 VCC 300 kΩ 300 kΩ A Rt 100 Ω Typ Y B VIT ≈ 2.3 V Figure 18. Open-Circuit Fail Safe of the LVDS Receiver It is only under these conditions that the output of the receiver is valid with less than a 100-mV differential input voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as long as it is connected as shown in the figure. Other termination circuits may allow a dc current to ground that could defeat the pullup currents from the receiver and the fail-safe feature. 15 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN65LVDS1050PW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 DL1050 SN65LVDS1050PWG4 ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 DL1050 SN65LVDS1050PWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 DL1050 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of