SN65LVDS117DGG

SN65LVDS109 SN65LVDS117 www.ti.com SLLS369F – AUGUST 1999 – REVISED FEBRUARY 2005 DUAL 4-PORT AND DUAL 8-PORT LVDS REPEATERS FEATURES • • • • • • • • • • • • Two Line Receivers and Eight ('109) or Sixteen ('117) Line Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz Outputs Arranged in Pairs From Each Bank Enabling Logic Allows Individual Control of Each Driver Output Pair, Plus All Outputs Low-Voltage Differential Signaling With Typical Output Voltage of 350 mV and a 100-Ω Load Electrically Compatible With LVDS, PECL, LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT, SSTL, or HSTL Outputs With External Termination Networks Propagation Delay Times < 4.5 ns Output Skew Less Than 550 ps Bank Skew Less Than150 ps Part-to-Part Skew Less Than 1.5 ns Total Power Dissipation Typically