SN65LVDS151DA

SN65LVDS151 www.ti.com SLLS444A – DECEMBER 2000 MuxIt™ SERIALIZER-TRANSMITTER FEATURES • • • • • • • • • A Member of the MuxIt™ Serializer-Deserializer Building-Block Chip Family Supports Serialization of up to 10 Bits of Parallel Data Input at Rates up to 200 Mbps PLL Lock/Valid Input Provided to Enable Link Data Transfers Cascadable With Additional SN65LVDS151 MuxIt Serializer-Transmitters for Wider Parallel Input Data Channel Widths LVDS Compatible Differential Inputs and Outputs Meet or Exceed the Requirements of ANSI TIA/EIA-644-A LVDS Inputs and Outputs ESD Protection Exceeds 12 kV HBM LVTTL Compatible Inputs for Lock/Valid, Enables, and Parallel Data Inputs Are 5-V Tolerant Operates With 3.3 V Supply Packaged in 32-Pin DA Thin Shrink Small-Outline Package With 26 Mil Terminal Pitch SN65LVDS151DA (Marked as 65LVDS151) VCC GND LCRI+ LCRI– CI_EN DI–9 DI–8 DI–7 DI–6 DI–5 DI–4 DI–3 DI–2 DI–1 DI–0 GND 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 25 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 CI– CI+ LVI MCI– MCI+ GND VCC LCO+ LCO– VCC EN LCO_EN VCC5 GND DO+ DO– DESCRIPTION MuxIt is a family of general-purpose, multiple-chip building blocks for implementing parallel data serializers and deserializers. The system allows for wide parallel data to be transmitted through a reduced number of transmission lines over distances greater than can be achieved with a single-ended (e.g., LVTTL or LVCMOS) data interface. The number of bits multiplexed per transmission line is user-selectable and allows for higher transmission efficiencies than with existing fixed ratio solutions. MuxIt utilizes the LVDS (TIA/EIA-644-A) low voltage differential signaling technology for communications between the data source and data destination. The MuxIt family initially includes three devices supporting simplex communications: the SN65LVDS150 phase locked loop frequency multiplier, the SN65LVDS151 serializer-transmitter, and the SN65LVDS152 receiver-deserializer. The SN65LVDS151 consists of a 10-bit parallel-in/serial-out shift register, three LVDS differential transmission line receivers, a pair of LVDS differential transmission line drivers, plus associated input buffers. It accepts up to 10 bits of user data on parallel data inputs (DI-0 → DI-9) and serializes (multiplexes) the data for transmission over an LVDS transmission line link. Two or more SN65LVDS151 units may be connected in series (cascaded) to accommodate wider parallel data paths for higher serialization values. Data is transmitted over the LVDS serial link at M times the input parallel data clock frequency. The multiplexing ratio M, or number of bits per data clock cycle, is programmed on the companion SN65LVDS150 MuxIt programmable PLL frequency multiplier with configuration pins (M1 → M5). The range of multiplexing ratio M supported by the SN65LVDS150 MuxIt programmable PLL frequency multiplier is between 4 and 40. Table 1 shows some of the combinations of LCRI and MCI supported by the SN65LVDS150 MuxIt programmable PLL frequency multiplier. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. MuxIt is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2000, Texas Instruments Incorporated SN65LVDS151 www.ti.com SLLS444A – DECEMBER 2000 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) Data is parallel loaded into the SN65LVDS151 input latches on the first rising edge of the M-clock input (MCI) signal following a rising edge of the link clock reference input (LCRI). The data is read out serially from the SN65LVDS151 shift registers on the rising edges of the M-clock input (MCI). The lowest order bit of parallel input data, DI-0, is output from DO on the third rising edge of MCI following the rising edge of LCRI. The remaining bits of parallel input data, DI-1 → DI-(M-1) are clocked out sequentially, in ascending order, by subsequent MCI rising edges. The link clock output (LCO) signal rising edge is synchronized to the data output (DO) by an internal circuit clocked by MCI. The LCO signal rising edge follows the first rising edge of MCI after the rising edge of LCRI. Examples of operating waveforms for values of M = 4 and M = 10 are provided in Table 1. Both the LCRI and MCI signals are intended to be sourced from the SN65LVDS150 MuxIt programmable frequency multiplier. They are carried over LVDS differential connections to minimize skew and jitter. The SN65LVDS151 includes LVDS differential line drivers for both the serialized data output (DO) stream and the link clock output (LCO). The cascade input (CI) is also an LVDS connection, and when it is used it is tied to the DO output of the preceding SN65LVDS151. An internal power-on reset (POR) and an enable input (EN) control the operation of the SN65LVDS151. When VCC is below 1.5 V, or when EN is low, the device is in a low-power disabled state, and the DO and LCO differential outputs are in a high-impedance state. When VCC is above 3 V and EN is high, the device and the two differential outputs are enabled and operating to specifications. The link clock output enable input (LCO_EN) is used to turn off the LCO output when it is not being used. Cascade input enable (CI_EN) is used to turn off the CI input when it is not being used. Serialized data bits are output from the DO output, starting in ascending order, from parallel input bit DI-0. The number of serialized data bits output per data clock cycle is determined by the multiplexing ratio M. For values of M less than or equal to 10, the cascade input (CI±) is not used, and only the first M parallel input bits (DI-0 thought DI-[M-1]) are used. For values of M greater than 10, all ten parallel input bits (DI-0 though DI-9) are used, and the cascade input is used to shift in the remaining data bits from additional SN65LVDS151 serializers. Table 2 shows which input data bits are used as a function of the multiplier M. Table 1. Example Combinations of LCRI and MCI Supported by the SN65LVDS150 Muxit Programmable PLL Frequency Multiplier LCRI, MHz 2 MCI, MHz M MINIMUM MAXIMUM MINIMUM MAXIMUM 4 5 50 20 200 10 5 20 50 200 20 5 10 100 200 40 5 5 200 200 Submit Documentation Feedback SN65LVDS151 www.ti.com SLLS444A – DECEMBER 2000 Table 2. Input Data Bits Used as a Function of the Multiplier M M=4 1st M=5 M=6 M=7 M=8 M=9 M = 10 M >10 bit output DI-0 DI-0 DI-0 DI-0 DI-0 DI-0 DI-0 DI-0 2nd bit output DI-1 DI-1 DI-1 DI-1 DI-1 DI-1 DI-1 DI-1 3rd bit output DI-2 DI-2 DI-2 DI-2 DI-2 DI-2 DI-2 DI-2 4th bit output DI-3 DI-3 DI-3 DI-3 DI-3 DI-3 DI-3 DI-3 5th bit output Invalid DI-4 DI-4 DI-4 DI-4 DI-4 DI-4 DI-4 6th bit output Invalid Invalid DI-5 DI-5 DI-5 DI-5 DI-5 DI-5 7th bit output Invalid Invalid Invalid DI-6 DI-6 DI-6 DI-6 DI-6 8th bit output Invalid Invalid Invalid Invalid DI-7 DI-7 DI-7 DI-7 9th bit output Invalid Invalid Invalid Invalid Invalid DI-8 DI-8 DI-8 10th bit output Invalid Invalid Invalid Invalid Invalid Invalid DI-9 DI-9 11th Invalid Invalid Invalid Invalid Invalid Invalid Invalid CI bits + bits output BLOCK DIAGRAM CI DI–9 DI–8 DI–7 DI–5 DI–4 Shift Register Input Latches DI–6 DI–3 DI–2 DI–1 DI–0 Control Logic LCRI MCI EN LVI DO LCO CI_EN LCO_EN NOTE: The CI input includes a 110 Ω termination resistor. Submit Documentation Feedback 3 SN65LVDS151 www.ti.com SLLS444A – DECEMBER 2000 M=4 DI–n Current Frame Next Frame Data Clock LCRI MCI LCO DO DI(3) DI(0) DI(1) DI(2) DI(3) DI(0) Current Frame M = 10 DI–n Current Frame Next Frame Data Clock LCRI MCI LCO DO DI(9) DI(0) DI(1) DI(2) DI(3) DI(4) DI(5) DI(6) DI(7) DI(8) Current Frame Figure 1. Operating Waveform Examples 4 Submit Documentation Feedback DI(9) DI(0) SN65LVDS151 www.ti.com SLLS444A – DECEMBER 2000 EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS VCC VCC 300 kΩ 300 kΩ LCRI–, MCI–, or CI– Inputs LCRI+, MCI+, or CI+ Inputs 4V 50 Ω 10 kΩ LCO+, LCO–, DO+, or DO– Outputs 4V 4V 110 Ω, (CI Input Only) VCC5 VCC DI-n Inputs Only EN, LVI, CI_EN, LCO_EN, or DI-n Inputs 400 Ω 6V 300 kΩ Submit Documentation Feedback 5 SN65LVDS151 www.ti.com SLLS444A – DECEMBER 2000 Terminal Functions TERMINAL NAME CI+, CI– CI_EN DO–, DO+ EN GND NO. I/O TYPE DESCRIPTION 31, 32 I LVDS Cascade input. This may be used to connect additional SN65LVDS151 units when the multiplexing ratio M value is greater than 10. This input has an internal 110-Ω nominal termination resistor. 5 I LVTTL Cascade input enable. Used to enable or disable the cascade input differential receiver. A high-level input enables the CI input, a low-level input disables the CI input. 17, 18 O LVDS Data output. This is the data being transmitted to the destination end of the serial link, or being supplied to another SN65LVDS151 unit in cascade. 22 I LVTTL Enable. Controls device operation. A high-level input enables the device; a low-level input disables and resets the device. When initially enabled, all outputs are in a low-level condition. NA Circuit ground 25, 24 O LVDS Link clock output This is the data block synchronization clock being transmitted to the destination end of the serial link. LCO_EN 21 I LVTTL Link clock output enable. Used to disable the link clock output when it is not being used. A high-level input enables the LCO output; a low-level input disables the LCO output. LCRI+, LCR– 3, 4 I LVDS Link clock reference input. This is the clock for latching in the parallel data; it comes from the PLL frequency multiplier. LVI 30 I LVTTL Lock/valid input. This is a signal required for proper Muxlt system operation. It is directly connected to the LVO output of a SN65LVDS150. It is used to inhibit the operation of this device until after the PLL has stabilized. A low level input forces a reset of the internal latches and shift registers, and forces the DO and LCO outputs to a low level. A high level input enables operation. 28, 29 I LVDS M-clock input. This is the high frequency multiplied clock input from the local PLL frequency multiplier. It synchronizes the transmission of the link data 6-15 I LVTTL Parallel data inputs. Data is latched into the device on the first rising edge of MCI following a rising edge of LCRI. 1, 23, 26 NA Supply voltage 20 NA 5-V VCC tolerance bias. Tied to 5 V nominal when the LVTTL inputs are being driven by a device powered from a 5-V supply, otherwise tied to local VCC LCO+, LCO– MCI+, MC– DI-9–DI-0 VCC VCC5 2, 16, 19, 27 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT Supply voltage range, VCC (2) –0.5 V to 4 V DI-0 through DI-9 inputs Voltage range EN, CI_EN, LCO_EN, LVI inputs, VCC5 CI±, LCRI±, or MCI± Inputs, DO±, or LCO± outputs Electrostatic discharge, human body model (3) Charged-device model (4) ±12 kV ±2 kV All pins ±500 V See Dissipation Rating Table –65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 6 –0.5 to 4 V All pins Storage temperature range (2) (3) (4) –0.5 V to 5.5 V MCI±, LCRI±, CI±, DO±, LCO±, and GND Continuous power dissipation (1) –0.5 V to VCC5 +0.5 V 260°C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. Tested in accordance with JEDEC Standard 22, Test Method A114-B. Tested in accordance with JEDEC Standard 22, Test Method C101. Submit Documentation Feedback SN65LVDS151 www.ti.com SLLS444A – DECEMBER 2000 DISSIPATION RATING TABLE PACKAGE TA≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 85°C POWER RATING DA 1453 mW 11.6 mW/°C 756 mW RECOMMENDED OPERATING CONDITIONS VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage |VID| Magnitude of differential input voltage VIC Common-mode input voltage TA MIN NOM MAX 3 3.3 3.6 2 DI-0 - DI-9, EN, LVI, LCO_EN, CI_EN | ID 2 0.8 V 0.6 V |V |V Operating free-air temperature V V 0.1 LCRI, MCI, CI UNIT 2.4
| ID 2 V VCC-0.8 V 85 °C 40 TIMING REQUIREMENTS PARAMETERS TEST CONDITIONS tsu(1) LCRI↑setup time before MCI↑ th(1) LCRI hold time after MCI↑ tsu(2) Data setup time, DI-0–DI-9 before MCI↑ after LCRI↑ th(2) Data hold time, DI-0–DI-9 valid after MCI↑ after LCRI↑ tsu(3) CI setup time before MCI↑ th(3) CI hold time after MCI↑ tc Clock cycle time tw High-level clock pulse width duration See Figure 2 See Figure 3 TA ≤ 25°C TA = 85°C MAX ns 0.3 ns 0 ns 2 ns 0.8 See Figure 4 ns 1.1 0V ns LCRI 20 200 MCI 5 50 0.4 tc 0.6 tc MCI, LCRI LCRI UNIT 0.5 2.5 LCRI ns ns 0V th(1) tsu(1) MCI MIN 0V MCI 0V Figure 2. Clock Input Timing Requirements Submit Documentation Feedback 7 SN65LVDS151 www.ti.com SLLS444A – DECEMBER 2000 LCRI 0V LCRI 0V tsu(1) MCI DI–n tsu(1) 0V





MCI








th(2) tsu(2) 1.4 V 0V DI–n 1.4 V Figure 3. Data Input Timing Requirements MCI 0V MCI 0V th(3) tsu(3) +100 mV CI –100 mV +100 mV CI –100 mV Figure 4. Cascade Input Timing Requirements ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS VITH+ Positive-going differential input voltage threshold VITH- Negative-going differential input voltage threshold |VOD(SS)| Steady-state differential output voltage magnitude ∆|VOD(SS)| Change in steady-state differential output voltage magnitude between logic states VOC(SS) Steady-stade common-mode output voltage ∆VOC(SS) Change in steady-state common-mode output voltage between logic states VOC(PP) Peak-to-peak change common-mode output voltage ICC Supply current IID Differential input current RL = 100 Ω, VID = ±100 mV, See Figure 6 and Figure 7 See Figure 8 mV –100 247 mV 340 454 mV –50 50 mV 1.125 1.375 –50 50 mV mV 150 30 Disabled 0.5 1 f(MCI) = 200 MHz, f(LCRI) = 20 MHz, RL = 100 Ω, DI-n= 1010101010 35 65 (II+ - II-) (LCRI, MCI inputs) VI = 0 V VI = 2.4 V VI = 0 V VI = 2.4 V LCRI, MCI inputs UNIT 100 22 VIC = 0.05 V to 2.35 V, VID = ±0.1 V CI input MAX 50 VID = 0.4 V, VIC = 2.2 V or 0.2 V Input current TYP (1) Enabled, RL = 100 Ω (II+ - II-) (CI input) LCRI, MCI inputs II See Figure 5 MIN V mA 3 4.4 mA –2 2 µA –2 –20 –1.2 –4 –40 –2.4 20 µA II(OFF) Power-off output current IIH High-level input current EN, LVI, DI-n, LCO_EN VIH = 2 V 20 µA IIL Low-level input current EN, LVI, DI-n, LCO_EN VIL = 0.8 V 10 µA IOS (1) 8 Short-circuit output current CI input DO, LCO VCC = 0 V , VI = 3.6 V µA 40 VO+ or VO- = 0 V –10 10 VOD = 0 V –10 10 All typical values are at TA = 25°C and with VCC = 3.3 V. Submit Documentation Feedback µA mA SN65LVDS151 www.ti.com SLLS444A – DECEMBER 2000 ELECTRICAL CHARACTERISTICS (continued) over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS TYP (1) MIN MAX UNIT IOZ High-impedance output current VO = 0 V or VCC –5 5 µA IO(OFF) Power-off output current VCC = 1.5 V , VI = 3.6 V –5 5 µA CI Input capacitance LCRI, MCI inputs VID = (0.4sin(4E6πt) + 0.5) V 3 pF SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS td(1) Propagation delay time, MCI↑ to DO↑ td(2) Propagation delay time, MCI↑ to DO↓ td(3) Propagation delay time, MCI↑ to LCO↑ tr Differential output signal rise time tf Differential output signal fall time tsk(p) Pulse skew (|tPHL– tPLH|), DO MIN TYP MAX TA ≤ 25°C 3 5 5.8 TA = 85°C 3 5 6.1 3 5 5.8 3 5 6.1 TA ≤ 25°C 3 5 5.8 TA = 85°C 3 5 6.1 0.3 0.8 1.5 ns 0.3 0.8 1.5 ns –250 0 250 ps 0 2.3 ns 0 250 ps 3 20 ns 3 10 ns 4 10 ns TA ≤ 25°C TA = 85°C RL = 100 Ω, CL = 10 pF, See Figure 9 RL = 100 Ω, CL = 10 pF, See Figure 10 tsk(pp) Part-to-part output skew, DO tsk(ω) Multiple-frequency skew, LCO↑ to DO↑ or DO↓ tPZL Propagation delay time, high-impedance to low-level See Figure 11 tPLZ Propagation delay time, low-level to high-impedance tPHZ Propagation delay time, high-level to high-impedance EN input to DO, LCO output, See Figure 12 -250 UNIT ns ns ns PARAMETER MEASUREMENT INFORMATION + VID – VI+ (VI+ + VI–)/2 VIC VI– Figure 5. Receiver Voltage Definitions Submit Documentation Feedback 9 SN65LVDS151 www.ti.com SLLS444A – DECEMBER 2000 Table 3. Receiver Minimum and Maximum Input Threshold Test Voltages APPLIED VOLTAGES RESULTING DIFFERENTIAL INPUT VOLTAGE RESULTING COMMONMODE INPUT VOLTAGE VI+ VI– VID VIC 1.25 V 1.15 V 100 mV 1.2 V 1.15 V 1.25 V –100 mV 1.2 V 2.4 V 2.3 V 100 mV 2.35 V 2.3 V 2.4 V –100 mV 2.35 V 0.1 V 0V 100 mV 0.05 V 0V 0.1 V –100 mV 0.05 V 1.5 V 0.9 V 600 mV 1.2 V 0.9 V 1.5 V –600 mV 1.2 V 2.4 V 1.8 V 600 mV 2.1 V 1.8 V 2.4 V –600 mV 2.1 V 0.6 V 0V 600 mV 0.3 V 0V 0.6 V –600 mV 0.3 V IO+ + IO– VOD VO+ – VO– (VO+ + VO–)/2 VOC Figure 6. Driver Voltage and Current Definitions 3.74 kΩ + VOD 100 Ω + _ 0 V ≤ Vtest ≤ 2.4 V – 3.74 kΩ Figure 7. VOD Test Circuit 49.9 Ω ±1% (2 PLCS) VOC(PP) + VOC(SS) VOC – A. 50 pF VOC All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, Pulse width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T. The measurement of VOC(PP) is made on test equipment with a –3 dB bandwidth of at least 5 GHz. Figure 8. Test Circuit and Definitions for the Driver Common-Mode Output Voltage 10 Submit Documentation Feedback SN65LVDS151 www.ti.com SLLS444A – DECEMBER 2000 0V MCI 0V MCI td(1) td(2) DO 0V DO 0V td(3) td(3) LCO 0V LCO 0V Figure 9. Output Timing Waveforms 0.4 V MCI 0V –0.4 V + DI (0–9) LCRI VOD Logic tPLH 100 Ω ±1% tPHL 100% 80% – MCI CL = 10 pF (2 PLCS) VOD(H) DO, LCO 0V DUT VOD(L) 20% 0% tr A. tf All input pulses are supplied by generators having the following characteristics: tr or tf ≤ 1 ns, MCI pulse repetition rate (PRR) = 50 Mpps, MCI Pulse width = 10 ± 0.2 ns, LCRI pulse repetition rate (PRR) = 5 Mpps, LCRI pulse width = 100 ±20 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T. Figure 10. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal 0V LCO tsk(ϖ) DO 0V Figure 11. LCO to DO Multiple-Frequency Skew Waveforms Submit Documentation Feedback 11 SN65LVDS151 www.ti.com SLLS444A – DECEMBER 2000 50 Ω ±1% + DI (0–9) LCRI VOD Logic – MCI 50 Ω ±1% + _ 1.2 V CL = 10 pF (2 PLCS) DUT 2V 1.4 V Input 0.8 V ≅ 0.34 V 0.1 V 0V VOD tPHZ 0V –0.1 V ≅ –0.34 V VOD tPLZ tPZL Figure 12. Enable/Disable Time Waveforms TYPICAL CHARACTERISTICS AVERAGE SUPPLY CURRENT vs FREQUENCY I CC – Average Supply Current – mA 40 VCC = 3.3 V, TA = 25°C 35 30 25 20 15 10 5 0 0 50 100 150 f – Frequency – Hz Figure 13. 12 Submit Documentation Feedback 200 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN65LVDS151DA ACTIVE TSSOP DA 32 46 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 65LVDS151 Samples SN65LVDS151DAR ACTIVE TSSOP DA 32 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 65LVDS151 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of