SN65LVDS1DBVT

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents SN65LVDS1, SN65LVDS2, SN65LVDT2 SLLS373L – JULY 1999 – REVISED DECEMBER 2014 SN65LVDxx High-Speed Differential Line Drivers and Receivers 1 Features 2 Applications • • • • • 1 • • • • • • • • • • • • Meets or Exceeds the ANSI TIA/EIA-644 Standard Designed for Signaling Rates (1) up to: – 630 Mbps for Drivers – 400 Mbps for Receivers Operates From a 2.4-V to 3.6-V Supply Available in SOT-23 and SOIC Packages Bus-Terminal ESD Exceeds 9 kV Low-Voltage Differential Signaling With Typical Output Voltages of 350 mV Into a 100-Ω Load Propagation Delay Times – 1.7-ns Typical Driver – 2.5-ns Typical Receiver Power Dissipation at 200 MHz – 25 mW Typical Driver – 60 mW Typical Receiver LVDT Receiver Includes Line Termination Low Voltage TTL (LVTTL) Level Driver Input Is 5V Tolerant Driver Is Output High-Impedance with VCC < 1.5 V Receiver Output and Inputs are High-Impedance With VCC < 1.5 V Receiver Open-Circuit Fail Safe Differential Input Voltage Threshold Less Than 100 mV Wireless Infrastructure Telecom Infrastructure Printer 3 Description The SN65LVDS1, SN65LVDS2, and SN65LVDT2 devices are single, low-voltage, differential line drivers and receivers in the small-outline transistor package. The outputs comply with the TIA/EIA-644 standard and provide a minimum differential output voltage magnitude of 247 mV into a 100-Ω load at signaling rates up to 630 Mbps for drivers and 400 Mbps for receivers. When the SN65LVDS1 device is used with an LVDS receiver (such as the SN65LVDT2) in a point-to-point connection, data or clocking signals can be transmitted over printed-circuit board traces or cables at very high rates with very low electromagnetic emissions and power consumption. The packaging, low power, low EMI, high ESD tolerance, and wide supply voltage range make the device ideal for battery-powered applications. The SN65LVDS1, SN65LVDS2, and SN65LVDT2 devices are characterized for operation from –40°C to 85°C. Device Information(1) PART NUMBER SN65LVDS1 SN65LVDS2 SN65LVDT2 (1) The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bit per second) PACKAGE BODY SIZE (NOM) SOIC (8) 4.90 mm × 3.91 mm SOT (5) 2.90 mm × 1.60 mm SOIC (8) 4.90 mm × 3.91 mm SOT (5) 2.90 mm × 1.60 mm SOIC (8) 4.90 mm × 3.91 mm SOT (5) 2.90 mm × 1.60 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic VSUPPLY VCC SN65LVDT2 SN65LVDS1 VCC VCC Z B VCC A R VCC 100 W Trace D Y LVTTL Out GND LVTTL In NC NC NC NC GND NC NC GND GND 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN65LVDS1, SN65LVDS2, SN65LVDT2 SLLS373L – JULY 1999 – REVISED DECEMBER 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 9 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Options....................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 4 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 4 4 4 5 5 6 6 7 8 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Driver Electrical Characteristics ................................ Receiver Electrical Characteristics ........................... Driver Switching Characteristics ............................... Receiver Switching Characteristics........................... Typical Characteristics .............................................. Parameter Measurement Information ................ 10 Detailed Description ............................................ 14 9.1 Overview ................................................................. 14 9.2 Functional Block Diagram ....................................... 14 9.3 Feature Description................................................. 14 9.4 Device Functional Modes........................................ 17 10 Application and Implementation........................ 19 10.1 Application Information.......................................... 19 10.2 Typical Applications .............................................. 19 11 Power Supply Recommendations ..................... 26 12 Layout................................................................... 26 12.1 Layout Guidelines ................................................. 26 12.2 Layout Example .................................................... 30 13 Device and Documentation Support ................. 32 13.1 13.2 13.3 13.4 13.5 13.6 Device Support...................................................... Documentation Support ....................................... Related Links ........................................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 32 32 32 32 32 32 14 Mechanical, Packaging, and Orderable Information ........................................................... 32 4 Revision History Changes from Revision K (November 2008) to Revision L • 2 Page Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 Submit Documentation Feedback Copyright © 1999–2014, Texas Instruments Incorporated Product Folder Links: SN65LVDS1 SN65LVDS2 SN65LVDT2 SN65LVDS1, SN65LVDS2, SN65LVDT2 www.ti.com SLLS373L – JULY 1999 – REVISED DECEMBER 2014 5 Device Options PART NUMBER INTEGRATED TERMINATION PACKAGE SN65LVDS1DBV SOT-23 (5) SN65LVDS1D SOIC (8) SN65LVDS2DBV SOT-23 (5) SN65LVDS2D SOIC (8) SN65LVDT2DBV √ SOT-23 (5) SN65LVDT2D √ SOIC (8) 6 Pin Configuration and Functions SN65LVDS2 and SN65LVDT2 DBV Package (TOP VIEW) SN65LVDS1 DBV Package (TOP VIEW) VCC 1 GND 2 Z 3 5 4 VCC 1 GND 2 A 3 D Y 5 R 4 B 110-W Resistor for LVDT Only SN65LVDS1 D Package (TOP VIEW) VCC D NC GND 1 8 2 7 3 6 4 5 Z Y NC NC SN65LVDS2 and SN65LVDT2 D Package (TOP VIEW) B A NC NC 1 8 2 7 3 6 4 5 VCC R NC GND 110-W Resistor for LVDT Only Pin Functions: SN65LVDS1 PIN NAME I/O DESCRIPTION DBV D VCC 1 1 -- Supply voltage GND 2 4 -- Ground D 5 2 I LVTTL input signal Y 4 7 O Differential (LVDS) non-inverting output Z 3 8 O Differential (LVDS) inverting output NC -- 3, 5, 6 -- No connect Copyright © 1999–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: SN65LVDS1 SN65LVDS2 SN65LVDT2 3 SN65LVDS1, SN65LVDS2, SN65LVDT2 SLLS373L – JULY 1999 – REVISED DECEMBER 2014 www.ti.com Pin Functions: SN65LVDS2, SN65LVDT2 PIN NAME I/O DESCRIPTION DBV D VCC 1 8 -- Supply voltage GND 2 5 -- Ground A 3 2 I Differential (LVDS) non-inverting output B 4 1 I Differential (LVDS) inverting output R 5 7 O LVTTL output signal NC -- 3, 4, 6 -- No connect 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) PARAMETER Supply voltage range, VCC (2) MIN MAX UNIT –0.5 4 V (A or B) –0.5 4 V (D) –0.5 VCC + 2 V Output voltage, VO (Y or Z) –0.5 4 V Differential input voltage magnitude, |VID| SN65LVDT2 only 1 V Input voltage range, VI Receiver output current, IO –12 12 mA Storage temperature, Tstg –65 150 °C (1) (2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages are with respect to network ground terminal. 7.2 ESD Ratings VALUE V(ESD) (1) (2) (3) Electrostatic discharge Human-body model electrostatic discharge, HBM ESD (1) All pins ±4000 Bus pins (A, B, Y, Z) ±9000 Machine-model electrostatic discharge, MM ESD (2) ±400 Field-induced-charge device model electrostatic discharge, FCDM ESD (3) ±1500 UNIT V Test method based upon JEDEC Standard 22, Test Method A114-A. Bus pins stressed with respect to GND and VCC separately. Test method based upon JEDEC Standard 22, Test Method A114-A. Test method based upon EIA-JEDEC JESD22-C101C. 7.3 Recommended Operating Conditions PARAMETER VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage TA Operating free-air temperature |VID| Magnitude of differential input voltage Input voltage (any combination of input or common-mode voltage) 4 Submit Documentation Feedback MIN NOM MAX 2.4 3.3 3.6 UNIT V 2 5 V 0 0.8 V –40 85 °C 0.1 0.6 V 0 VCC – 0.8 V Copyright © 1999–2014, Texas Instruments Incorporated Product Folder Links: SN65LVDS1 SN65LVDS2 SN65LVDT2 SN65LVDS1, SN65LVDS2, SN65LVDT2 www.ti.com SLLS373L – JULY 1999 – REVISED DECEMBER 2014 7.4 Thermal Information THERMAL METRIC SN65LVDS1, SN65LVDS2, SN65LVDT2 (1) D DBV 8 PINS 5 PINS RθJA Junction-to-ambient thermal resistance 172.4 322.6 Power rating TA ≤ 25°C 725 385 TA ≤ 85°C 402 200 (1) UNIT °C/W mW For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 7.5 Driver Electrical Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER MIN (1) TYP (2) MAX RL = 100 Ω, 2.4 ≤ VCC < 3 V 200 350 454 RL = 100 Ω, 3 ≤ VCC < 3.6 V 247 350 454 See Figure 10 –50 50 1.125 1.375 –50 50 mV 25 100 mV TEST CONDITIONS |VOD| Differential output voltage magnitude Δ|VOD| Change in differential output voltage magnitude between logic states VOC(SS) Steady-state common-mode output voltage ΔVOC(SS) Change in steady-state common-mode output voltage between logic states VOC(PP) Peak-to-peak common-mode output voltage ICC Supply current IIH High-level input current IIL Low-level input current See Figure 10 VI = 0 V or VCC, No load mV V 2 4 5.5 8 VIH = 5 V 2 20 μA VIL = 0.8 V 2 10 μA VOY or VOZ = 0 V 3 10 VI = 0 V or VCC, RL = 100 Ω IOS Short-circuit output current IO(OFF) Power-off output current VCC = 1.5 V, VO = 3.6 V Ci Input capacitance VI = 0.4sin(4E6πt) + 0.5 V (1) (2) UNIT VOD = 0 V 10 –1 mA mA 1 3 μA pF The algebraic convention, in which the least positive (most negative) limit is designated as a minimum, is used in this data sheet. All typical values are at 25°C and with a 3.3-V supply. Copyright © 1999–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: SN65LVDS1 SN65LVDS2 SN65LVDT2 5 SN65LVDS1, SN65LVDS2, SN65LVDT2 SLLS373L – JULY 1999 – REVISED DECEMBER 2014 www.ti.com 7.6 Receiver Electrical Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER VITH+ TEST CONDITIONS Positive-going differential input voltage threshold VOH High-level output voltage VOL Low-level output voltage IOL = 8 mA ICC Supply current No load, Steady state UNIT mV –100 IOH = –8 mA, VCC = 2.4 V 1.9 IOH = –8 mA, VCC = 3 V 2.4 VI = 0 V, other input = 1.2 V Input current (A or B inputs) MAX 100 Negative-going differential input voltage threshold II TYP (2) See Figure 11 VITH– LVDS2 MIN (1) 0.25 4 –20 VI = 2.2 V, other input = 1.2 V, VCC = 3.0 V VI = 0 V, other input open LVDT2 VI = 2.2 V, other input open, VCC = 3.0 V LVDS2 VIA = 2.4 V, VIB = 2.3 V V 0.4 7 V mA –2 –3 –40 –1.2 μA -4 –6 –2.4 IID Differential input current (IIA – IIB) II(OFF) Power-off input current (A or B LVDS2 inputs) LVDT2 VCC = 0 V, VIA = VIB = 2.4 V 20 VCC = 0 V, VIA = VIB = 2.4 V 40 RT Differential input resistance VIA = 2.4 V, VIB = 2.2 V CI Input capacitance VI = 0.4sin(4E6πt) + 0.5 V 5.8 pF CO Output capacitance VI = 0.4sin(4E6πt) + 0.5 V 3.4 pF (1) (2) LVDT2 –2 90 μA 2 111 μA Ω 132 The algebraic convention, in which the least positive (most negative) limit is designated as a minimum, is used in this data sheet. All typical values are at 25°C and with a 2.7-V supply. 7.7 Driver Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT tPLH Propagation delay time, low-to-high-level output 1.5 3.1 ns tPHL Propagation delay time, high-to-low-level output 1.8 3.1 ns tr Differential output signal rise time 0.6 1 ns tf Differential output signal fall time 0.7 1 ns tsk(p) Pulse skew (|tPHL – tPLH|) (2) 0.3 (1) (2) 6 RL = 100 Ω, CL = 10 pF, See Figure 13 ns All typical values are at 25°C and with a 3.3-V supply. tsk(p) is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output. Submit Documentation Feedback Copyright © 1999–2014, Texas Instruments Incorporated Product Folder Links: SN65LVDS1 SN65LVDS2 SN65LVDT2 SN65LVDS1, SN65LVDS2, SN65LVDT2 www.ti.com SLLS373L – JULY 1999 – REVISED DECEMBER 2014 7.8 Receiver Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX 1.4 2.6 3.6 ns 1.4 2.5 3.6 ns UNIT tPLH Propagation delay time, low-to-highlevel output tPHL Propagation delay time, high-to-lowlevel output tsk(p) Pulse skew (|tpHL – tpLH|) (2) 0.1 0.6 ns tr Output signal rise time 0.8 1.4 ns tf Output signal fall time 0.8 1.4 ns tr(slew) Output slew rate (rising) CL = 10 pF, See Figure 14 CL = 10 pF tf(slew) (1) (2) Output slew rate (falling) VCC = 3.0 V – 3.6 V 2.2 3 5.5 V/ns VCC = 2.4 V – 2.7 V 1.5 1.9 2.9 V/ns VCC = 3.0 V – 3.6 V 2.7 3.8 6 V/ns VCC = 2.4 V – 2.7 V 2.1 2.3 3.9 V/ns All typical values are at 25°C and with a 2.7-V supply. tsk(p) is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output. Copyright © 1999–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: SN65LVDS1 SN65LVDS2 SN65LVDT2 7 SN65LVDS1, SN65LVDS2, SN65LVDT2 SLLS373L – JULY 1999 – REVISED DECEMBER 2014 www.ti.com 7.9 Typical Characteristics 1.9 2.6 2.4 t PLH − Driver High-to-Low Propagation Delay Times − ns t PHL − Driver High-to-Low Propagation Delay Times − ns VCC = 2.4 V VCC = 3 V 2.2 2 VCC = 2.7 V 1.8 VCC = 3.3 V 1.6 VCC = 3.6 V 1.4 1.2 1 −40 −20 0 20 40 60 80 VCC = 2.4 V 1.8 1.7 VCC = 2.7 V 1.6 VCC = 3.6 V 1.5 1.4 1.3 1.2 1.1 1 −40 100 −20 TA − Free-Air Temperature − °C VOL− Receiver Low-Level Output Voltage − V VOH − Receiver High-Level Output Voltage − V 3 2.5 VCC = 3.3 V 2 1.5 VCC = 2.7 V 1 0.5 80 100 3 2.5 VCC = 2.7 V 2 1.5 VCC = 3.3 V 1 0.5 0 −60 −50 −40 −30 −20 −10 0 0 2.9 2.85 VCC = 2.4 V 2.8 2.75 VCC = 3.6 V 2.7 VCC = 3.3 V 2.6 VCC = 3 V 2.55 2.5 VCC = 2.7 V 2.45 −20 0 20 40 60 80 TA − Free-Air Temperature − °C Figure 5. Receiver High-to-Low Level Propagation Delay Times vs Free-Air Temperature Submit Documentation Feedback 10 20 30 40 50 60 70 IOL − Low-Level Output Current − mA Figure 4. Receiver Low-Level Output Voltage vs Low-Level Output Current t PLH − Receiver Low-to-High Level Propagation Delay time s − ns Figure 3. Receiver High-Level Output Voltage vs High-Level Output Current t PHL − Receiver High-to-Low level Propagation Delay Times − ns 60 3.5 IOH − High-Level Output Current − mA 8 40 4 3.5 2.4 −40 20 Figure 2. Driver Low-to-High Level Propagation Delay Times vs Free-Air Temperature 4 2.65 0 TA − Free-Air Temperature − °C Figure 1. Driver High-to-Low Level Propagation Delay Times vs Free-Air Temperature 0 −70 VCC = 3.3 V VCC = 3 V 3 VCC = 2.4 V 2.9 2.8 2.7 VCC = 3.3 V VCC = 3.6 V 2.6 2.5 2.4 VCC = 3 V VCC = 2.7 V 2.3 2.2 −40 −20 0 20 40 60 80 100 TA − Free-Air Temperature − °C Figure 6. Receiver Low-to-High Level Propagation Delay Times vs Free-Air Temperature Copyright © 1999–2014, Texas Instruments Incorporated Product Folder Links: SN65LVDS1 SN65LVDS2 SN65LVDT2 SN65LVDS1, SN65LVDS2, SN65LVDT2 www.ti.com SLLS373L – JULY 1999 – REVISED DECEMBER 2014 Typical Characteristics (continued) 1200 1400 VCC = 2.5 V VCC = 3.3 V 1000 1000 tr, tf − Rise/Fall Time − ps tr, tf − Rise/Fall Time − ps 1200 Rise Time 800 Fall Time 600 400 Rise Time 800 600 Fall Time 400 200 200 0 0 0 5 10 15 20 25 CL − Capacitive Load − pF Figure 7. Rise or Fall Time vs Capacitive Load Copyright © 1999–2014, Texas Instruments Incorporated 0 5 10 15 20 25 CL − Capacitive Load − pF Figure 8. Rise or Fall Time vs Capacitive Load Submit Documentation Feedback Product Folder Links: SN65LVDS1 SN65LVDS2 SN65LVDT2 9 SN65LVDS1, SN65LVDS2, SN65LVDT2 SLLS373L – JULY 1999 – REVISED DECEMBER 2014 www.ti.com 8 Parameter Measurement Information IOY Y II D IOZ VOD V VOY Z VI OY )V OZ 2 VOC VOZ Figure 9. Driver Voltage and Current Definitions 49.9 Ω, ±1% (2 Places) Y Input Z 50 pF VI 1.4 V VI 1V VOC VOC(PP) VOC(SS) VOC A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0.06 mm of the device under test. The measurement of VOC(PP) is made on test equipment with a –3dB bandwidth of at least 300 MHz. Figure 10. Driver Test Circuit and Definitions for the Driver Common-Mode Output Voltage IIA V IA )V A IO IB 2 VIA VIC IIB VID B R VO VIB Figure 11. Receiver Voltage and Current Definitions 10 Submit Documentation Feedback Copyright © 1999–2014, Texas Instruments Incorporated Product Folder Links: SN65LVDS1 SN65LVDS2 SN65LVDT2 SN65LVDS1, SN65LVDS2, SN65LVDT2 www.ti.com SLLS373L – JULY 1999 – REVISED DECEMBER 2014 Parameter Measurement Information (continued) 1000 Ω 100 Ω 1000 Ω VIC + − 100 Ω† VID 10 pF, 2 Places VO 15 pF † Remove for testing LVDT device. NOTE: Input signal of 3 Mpps, duration of 167 ns, and transition time of < 1 ns. VIT+ 0V VID −100 mV VO 100 mV VID 0V VIT− VO NOTE: Input signal of 3 Mpps, duration of 167 ns, and transition time of