SN65LVDS20DRFTG4

SN65LVDS20 SN65LVP20 www.ti.com SLLS620A – JUNE 2004 – REVISED SEPTEMBER 2005 LVPECL AND LVDS REPEATER/TRANSLATOR WITH ENABLE FEATURES • • Low-Voltage PECL Input and Low-Voltage PECL or LVDS Outputs Signaling Rates to 4 Gbps or Clock Rates to 2 GHz – 120-ps Output Transition Times – Less than 45 ps Total Jitter – Less than 630 ps Propagation Delay Times • • 2.5-V or 3.3-V Supply Operation 2-mm x 2-mm Small-Outline No-Lead Package APPLICATIONS • • PECL-to-LVDS Translation Data or Clock Signal Amplification DESCRIPTION The SN65LVDS20 and SN65LVP20 are a high-speed differential receiver and driver connected as a repeater. The receiver accepts low-voltage positive-emitter-coupled logic (PECL) at signaling rates up to 4 Gbps and repeats it as either an LVDS or PECL output signal. The signal path through the device is differential for low radiated emissions and minimal added jitter. The outputs of the SN65LVDS20 are LVDS levels as defined by TIA/EIA-644-A. The outputs of the SN65LVDP20 are compatible with low-voltage PECL levels. A low-level input to EN enables the outputs. A high-level input puts the output into a high-impedance state. Both outputs are designed to drive differential transmission lines with nominally 100-Ω characteristic impedance. Both devices provide a voltage reference (VBB) of typically 1.35 V below VCC for use in receiving single-ended PECL input signals. When not used, VBB should be unconnected or open. All devices are characterized for operation from -40°C to 85°C. FUNCTION DIAGRAM 7 A 6 B VCC IN OUT 4 Y Z Scale = 75 mV/div EN VBB GND 9 Scale = 50 ps/div Figure 1. SN65LVDS20 Output Eye Pattern With 4-Gbps PRBS Input Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2005, Texas Instruments Incorporated SN65LVDS20 SN65LVP20 www.ti.com SLLS620A – JUNE 2004 – REVISED SEPTEMBER 2005 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. AVAILABLE OPTIONS (1) (1) INPUT OUTPUT PART NUMBER PART MARKING Differential LVDS SN65LVDS20 E8 Differential LVPECL SN65LVP20 E7 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT (2) VCC Supply voltage -0.5 V to 4 V VI Input voltage -0.5 V to VCC + 0.5 V VO Output voltage -0.5 V to VCC + 0.5 V IO VBB output current ±0.5 mA HBM electrostatic discharge (3) CDM electrostatic ±3 kV discharge (4) ±1500 V Continuous power dissipation (1) (2) (3) (4) See Power Dissipation Ratings Table Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential voltages, are with respect to network ground (see Figure 2). Tested in accordance with JEDEC Standard 22, Test Method A114-A-7 Tested in accordance with JEDEC Standard 22, Test Method C101 DISSIPATION RATINGS PACKAGE TA < 25°C POWER RATING OPERATING FACTOR ABOVE TA = 25°C TA = 85°C POWER RATING DRF 403 mW 4.0 mW/°C 161 mW RECOMMENDED OPERATING CONDITIONS VCC Supply Voltage VIC Common-mode input voltage (VIA + VIB)/2 |VID| Differential input voltage magnitude, |VIA - VIB| VIH High-level input voltage, EN VIL Low-level input voltage, EN IO Output current to VBB RL Differential load resistance TA Operating free-air temperature (1) 2 MIN NOM MAX 2.375 2.5 or 3.3 3.6 V VCC - (VID/2) V 0.08 1 V 2 VCC V 0 0.8 V -400 (1) 400 µA 90 132 Ω -40 85 °C 1.2 The algebraic convention, where the least positive (more negative) value is designated minimum, is used in this data sheet. UNIT SN65LVDS20 SN65LVP20 www.ti.com SLLS620A – JUNE 2004 – REVISED SEPTEMBER 2005 ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) TYP (1) MAX RL = 100 Ω, EN at 0 V, Other inputs open 35 45 Outputs unloaded, EN at 0 V, Other inputs open 19 24 116 160 63 86 VCC - 1.35 VCC - 1.25 PARAMETER ICC Supply current TEST CONDITIONS MIN mA Device power dissipation, SN65LVDS20 RL = 100 Ω, EN at 0 V, 2-GHz 50%-duty-cycle square-wave input Device power dissipation, SN65LVP20 50 Ω from Y and Z to VCC - 2 V, EN at 0 V, 2-GHz 50%-duty-cycle square-wave input VBB Reference voltage IBB = ±400 µA IIH High-level input current, EN VI = 2 V -20 20 IIAH or IIBH High-level input current, A or B VI = VCC -20 20 IIL Low-level input current, EN VI = 0.8 V -20 20 IIAL or IIBL Low-level input current, A or B VI = GND -20 20 PD UNIT mW VCC - 1.44 V µA SN65LVDS20 OUTPUT CHARACTERISTICS (see Figure 2) |VOD| Differential output voltage magnitude, |VOY - VOZ| ∆|VOD| Change in differential output voltage magnitude between logic states VOC(SS) Steady-state common-mode output voltage (see Figure 3) ∆VOC(SS) Change in steady-state common-mode output voltage between logic states 247 340 454 mV See Figure 2 50 1.125 1.375 -50 50 See Figure 3 V mV VOC(PP) Peak-to-peak common-mode output voltage IOYZ or IOZZ High-impedance output current EN at VCC, VO = 0 V or VCC -1 1 IOYS or IOZS Short-circuit output current EN at 0 V, VOY or VOZ = 0 V -62 62 IOS(D) Differential short-circuit output current, |IOY - IOZ| EN at 0 V, VOY = VOZ -12 12 VCC - 1.05 VCC - 0.82 VCC - 1.83 VCC - 1.57 VCC - 1.88 VCC - 1.57 50 100 µA mA SN65LVP20 OUTPUT CHARACTERISTICS (see Figure 2) VOYH or VOZH High-level output voltage VOYL or VOZL Low-level output voltage VOYL or VOZL Low-level output voltage |VOD| Differential output voltage magnitude, |VOH - VOL| IOYZ or IOZZ High-impedance output current (1) 3.3 V; 50 Ω from Y and Z to VCC - 2 V 2.5 V; 50 Ω from Y and Z to VCC - 2 V V 0.6 EN at VCC, VO = 0 V or VCC -1 0.8 1 1 µA Typical values are at room temperature and with a VCC of 3.3 V. 3 SN65LVDS20 SN65LVP20 www.ti.com SLLS620A – JUNE 2004 – REVISED SEPTEMBER 2005 SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER tPLH Differential propagation delay time, low-to-high-level output tPHL Differential propagation delay time, high-level-to-low-level output tSK(P) Pulse skew, |tPLH - tPHL| tSK(PP) Part-to-part skew tr 20%-to-80% differential signal rise time tf 20%-to-80% differential signal fall time tjit(per) RMS period jitter (3) See Figure 2 and Figure 4 (2) 300 450 630 300 450 630 VCC = 3.3 V 80 VCC = 2.5 V 130 LVDS, See Figure 2 and Figure 4 85 115 LVPECL, See Figure 2 and Figure 4 92 120 LVDS, See Figure 2 and Figure 4 85 115 LVPECL, See Figure 2 and Figure 4 92 120 2 3 13 16 37 45 2-GHz 50%-duty-cycle square-wave input, See Figure 5 (4) Peak cycle-to-cycle jitter tjit(p-p) Peak-to-peak jitter tjit(ph) Intrinsic phase jitter tPHZ Propagation delay time, high-level-to-high-impedance output tPLZ Propagation delay time, low-level-to-high-impedance output LVDS; 4 Gbps PRBS, 223- 1 run length, See Figure 5 Propagation delay time, high-impedance-to-high-level output tPZL Propagation delay time, high-impedance-to-low-level output 155.52 MHz 0.62 622.08 MHz 0.14 ps ps ps ps ps ps ps 30 See Figure 2 and Figure 6 ns 30 30 Typical values are at room temperature and with a VCC of 3.3 V. Part-to-part skew is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. Period jitter is the deviation in cycle time of a signal with respect to the ideal period over a random sample of 100,000 cycles. Cycle-to-cycle jitter is the variation in cycle time of a signal between adjacent cycles, over a random sample of 1,000 adjacent cycle pairs. PARAMETER MEASUREMENT INFORMATION ICC 1 IIA 2 IIB 3 5 II VIA VIB VCC B 8 4 VCC V BB 6 Z D.U.T. 7 Y EN GND NC A IBB 50 I OZ S1 I OY 9 VI 50 + + + + VOY VOZ VBB VOC − − − − (1) CL is the instrumentation and test fixture capacitance. (2) S1 is open for the SN65LVDS20 and closed for the SN65LVP20. CL VCC − 2 V Figure 2. Output Voltage Test Circuit and Voltage and Current Definitions 4 UNIT 30 tPZH (3) (4) MAX 20 tjit(cc) (1) (2) MIN TYP (1) TEST CONDITIONS SN65LVDS20 SN65LVP20 www.ti.com SLLS620A – JUNE 2004 – REVISED SEPTEMBER 2005 PARAMETER MEASUREMENT INFORMATION (continued) INPUT dVOC(SS) VOC(PP) VOC Figure 3. VOC Definitions VCC 1.2 V 1.125 V VIA 1.5 V VIB t PHL t PLH VOY − VOZ 80% 100% 50% tf tr 20% Figure 4. Propagation Delay and Transition Time Test Waveforms 50
Cable, X  Y cm, SMA Coax Connectors, 4 Places HP3104 Pattern Generator Note A TDS Oscilloscope with TJIT3 Analysis Pack Device Under Test 50
50
DC Figure 5. Jitter Measurement Setup 5 SN65LVDS20 SN65LVP20 www.ti.com SLLS620A – JUNE 2004 – REVISED SEPTEMBER 2005 PARAMETER MEASUREMENT INFORMATION (continued) VCC 1.2 V VIA 1.5 V VIB VI to EN 2V 1.4 V t PZH t PZL 0.8 V t PHZ t PLZ 0V VOY − VOZ 80% 50% 20% Figure 6. Enable and Disable Time Test Waveforms DEVICE INFORMATION FUNCTION TABLE (1) B EN Y Z H H L ? ? L H L L H H L L H L L L L ? ? X X H Z Z Open Open L ? ? X X Open ? ? (1) 6 A H = high, L = low, Z = high impedance, ? = indeterminate 100% SN65LVDS20 SN65LVP20 www.ti.com SLLS620A – JUNE 2004 – REVISED SEPTEMBER 2005 TOP VIEW 1 4 9 8 5 BOTTOM VIEW Package Pin Assignments - Numerical Listing PIN SIGNAL PIN 1 NC 6 SIGNAL Z 2 A 7 Y 3 B 8 VCC 4 VBB 9 GND 5 EN Package Pin Assignments - Alphabetical Listing SIGNAL PIN SIGNAL PIN A 2 VBB 4 B 3 VCC 8 EN 5 Y 7 GND 9 Z 6 NC 1 7 SN65LVDS20 SN65LVP20 www.ti.com SLLS620A – JUNE 2004 – REVISED SEPTEMBER 2005 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs FREQUENCY SUPPLY CURRENT vs FREE-AIR TEMPERATURE 60 50 I CC − Supply Current − mA I CC − Supply Current − mA 60 LVP20 = Loaded 40 LVDS20 30 20 50 LVP20 = Loaded LVDS20 40 30 20 10 10 0 400 800 1200 1600 −40 2000 40 60 80 DIFFERENTIAL OUTPUT VOLTAGE vs FREQUENCY LVDS20 RISE/FALL TIME vs FREE-AIR TEMPERATURE 100 105 900 800 LVP20 700 tr/tf − Rise/Fall Time − ps V OD − Differential Output Voltage − mV 20 Figure 8. 600 500 400 LVDS20 300 200 97 89 tr 81 tf 73 100 0 65 −40 500 1000 1500 2000 2500 3000 3500 4000 f − Frequency − MHz 100 Figure 10. LVP20 RISE/FALL TIME vs FREE-AIR TEMPERATURE LVDS20 PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE Propagation Delay Time − ps 500 97 tf 89 tr 81 73 65 −40 −20 0 20 40 60 80 TA − Free−Air Temperature − C Figure 9. 105 tr/tf − Rise/Fall Time − ps 0 Figure 7. 0 −20 0 20 40 60 80 TA − Free−Air Temperature − C Figure 11. 8 −20 TA − Free−Air Temperature − C f − Frequency − MHz 100 476 tPHL 452 tPLH 428 404 380 −40 −20 0 20 40 60 80 TA − Free−Air Temperature − C Figure 12. 100 SN65LVDS20 SN65LVP20 www.ti.com SLLS620A – JUNE 2004 – REVISED SEPTEMBER 2005 TYPICAL CHARACTERISTICS (continued) LVP20 PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE PERIOD JITTER vs FREQUENCY 5 476 4 tPHL Period Jitter − ps Propagation Delay Time − ps 500 452 tPLH 428 3 LVDS20 2 LVP20 1 404 380 −40 0 −20 0 20 40 60 80 0 100 400 1200 1600 Figure 13. Figure 14. PEAK-TO-PEAK JITTER vs FREQUENCY PEAK-TO-PEAK JITTER vs DATA RATE 2000 50 25 40 20 Peak-to-Peak Jitter − ps Peak-to-Peak Jitter − ps 800 f − Frequency − MHz TA − Free−Air Temperature − C LVDS20 15 LVP20 10 5 LVP20 30 20 LVDS20 10 0 0 0 400 800 1200 1600 f − Frequency − MHz 0 2000 1600 2400 3200 4000 Data Rate − Mbps Figure 15. Figure 16. Scale = 175 mV/div Scale = 75 mV/div 800 Scale = 50 ps/div Figure 17. LVDS20 4-Gbps, 223 - 1 PRBS Scale = 50 ps/div Figure 18. LVP20 4-Gbps, 223 - 1 PRBS 9 SN65LVDS20 SN65LVP20 www.ti.com SLLS620A – JUNE 2004 – REVISED SEPTEMBER 2005 TYPICAL CHARACTERISTICS (continued) PHASE NOISE OF SN65LVP20 PHASE NOISE OF SN65LVP20 −40 −40 −50 −60 −50 Blue = Device Green = Source −60 −70 −80 −80 −90 −90 −100 −100 −110 −110 −120 −120 −130 −130 −140 −140 −150 −150 −160 100 1k 10 k 100 k 1M 10 M 100 M Figure 19. Frequency Offset From 155.52 MHz Carrier 10 Blue = Device Green = Source −70 −160 100 1k 10 k 100 k 1M 10 M 100 M Figure 20. Frequency Offset From 622.08 MHz Carrier SN65LVDS20 SN65LVP20 www.ti.com SLLS620A – JUNE 2004 – REVISED SEPTEMBER 2005 EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS OUTPUT LVP20 OUTPUT LVDS20 VCC R VCC VCC VCC VCC R Y VCC Y 7V Z Z 7V 7V 7V ENABLE VCC 400 Ω 300 kΩ 7V INPUT VCC OUTPUT VBB VCC A VCC VCC B VBB VBB 11 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN65LVDS20DRFR ACTIVE WSON DRF 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 E8 Samples SN65LVDS20DRFT ACTIVE WSON DRF 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 E8 Samples SN65LVDS20DRFTG4 ACTIVE WSON DRF 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 E8 Samples SN65LVP20DRFR ACTIVE WSON DRF 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 E7 Samples SN65LVP20DRFT ACTIVE WSON DRF 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 E7 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of