SN65LVDS301
SN65LVDS301
SLLS681E – FEBRUARY 2006 – REVISED
OCTOBER 2020
SLLS681E – FEBRUARY 2006 – REVISED OCTOBER 2020
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SN65LVDS301 Programmable 27-Bit Parallel-to-Serial Transmitter
1 Features
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3 Description
FlatLink™3G
serial interface technology
Compatible with FlatLink3G receivers such as
SN65LVDS302
Input supports 24-bit RGB video mode interface
24-Bit RGB data, 3 control bits, 1 parity bit and 2
reserved bits transmitted over 1, 2 or 3 differential
lines
SubLVDS differential voltage levels
Effective data throughput up to 1755 Mbps
Three operating modes to conserve power
– Active-mode QVGA 17.4 mW (typ)
– Active-mode VGA 28.8 mW (typ)
– Shutdown mode 0.5 μA (typ)
– Standby mode 0.5 μA (typ)
Bus swap for increased PCB layout flexibility
1.8-V supply voltage
ESD rating > 2 kV (HBM)
Pixel clock range of 4 MHz–65 MHz
Failsafe on all CMOS inputs
Packaging: 80 pin 5mm × 5mm nFBGA®
Very low EMI meets SAE J1752/3 'M'-spec
The SN65LVDS301 serializer device converts 27
parallel data inputs to 1, 2, or 3 Sub Low-Voltage
Differential Signaling (SubLVDS) serial outputs. It
loads a shift register with 24 pixel bits and 3 control
bits from the parallel CMOS input interface. In addition
to the 27 data bits, the device adds a parity bit and
two reserved bits into a 30-bit data word. Each word is
latched into the device by the pixel clock (PCLK). The
parity bit (odd parity) allows a receiver to detect single
bit errors. The serial shift register is uploaded at 30,
15, or 10 times the pixel-clock data rate depending on
the number of serial links used. A copy of the pixel
clock is output on a separate differential output.
FPC
cabling
typically
interconnects
the
SN65LVDS301 with the display. Compared to parallel
signaling, the LVDS301 outputs significantly reduce
the EMI of the interconnect by over 20 dB. The
electromagnetic emission of the device itself is very
low and meets the meets SAE J1752/3 'M'-spec. (see
Figure 6-22)
The SN65LVDS301 is characterized for operation
over ambient air temperatures of –40°C to 85°C. All
CMOS inputs offer failsafe features to protect them
from damage during power-up and to avoid current
flow into the device inputs during power-up. An input
voltage of up to 2.165 V can be applied to all CMOS
inputs while VDD is between 0V and 1.65V.
2 Applications
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Wearables (non-medical)
Tablets
Mobile phones
Portable electronics
Gaming
Retail automation & payment
Building automation
Device Information (1)
PART NUMBER
SN65LVDS301
(1)
PACKAGE
nFBGA (80)
BODY SIZE (NOM)
5.00 mm × 5.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
D
LC
Application
Processor
with CMOS
Video Interface
4
S31
LVD or 2
30
DS
LV
LVDS301
or
LVDS311
A
DAT
CLK
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
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and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings (1) ................................... 5
6.2 Thermal Information....................................................5
6.3 Recommended Operating Conditions (1) ................... 6
6.4 Device Electrical Characteristics.................................7
6.5 Output Electrical Characteristics.................................7
6.6 Input Electrical Characteristics....................................8
6.7 Switching Characteristics............................................8
6.8 Timing Characteristics.................................................9
6.9 Device Power Dissipation........................................... 9
6.10 Typical characteristics.............................................10
7 Parameter Measurement Information.......................... 14
8 Detailed Description......................................................22
8.1 Overview................................................................... 22
8.2 Functional Block Diagram......................................... 23
8.3 Feature Description...................................................23
8.4 Device Functional Modes..........................................25
9 Application information................................................ 30
9.1 Application Information............................................. 30
9.2 Preventing Increased Leakage Currents in
Control Inputs.............................................................. 30
9.3 VGA Application........................................................30
9.4 Dual LCD-Display Application...................................31
9.5 Typical Application Frequencies............................... 31
10 Power Supply Design Recommendation...................33
10.1 Decoupling Recommendation.................................33
11 Layout........................................................................... 34
11.1 Layout Guidelines................................................... 34
12 Device and Documentation Support..........................35
12.1 Support Resources................................................. 35
12.2 Trademarks............................................................. 35
12.3 Electrostatic Discharge Caution..............................35
12.4 Glossary..................................................................35
13 Mechanical, Packaging, and Orderable
Information.................................................................... 36
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (August 2012) to Revision E (October 2020)
Page
• NOTE: The device in the MicroStar Jr. BGA packaging were redesigned using a laminate nFBGA package.
This nFBGA package offers datasheet-equivalent electrical performance. It is also footprint equivalent to the
MicroStar Jr. BGA. The new package designator in place of the discontinued package designator will be
updated throughout the datasheet......................................................................................................................1
• Changed u*jr ZQE to nFBGA ZXH..................................................................................................................... 1
• Changed u*jr ZQE to nFBGA ZXH..................................................................................................................... 3
• Changed u*jr ZQE to nFBGA ZXH, updated thermal information.......................................................................5
• Added overview................................................................................................................................................ 22
2
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5 Pin Configuration and Functions
Figure 5-1. 80-Ball ZXH (Top View)
Pin Functions
NAME
PIN
I/O
DESCRIPTION
D0+, D0–
J5, J4
SubLVDS Data Link (active during normal operation)
D1+, D1–
F9, G9
SubLVDS Data Link (active during normal operation when LS0 = high and
LS1 = low, or LS0 = low and LS1=high; high impedance if LS0 = LS1 = low)
D2+, D2–
D9, E9
SubLVDS Data Link (active during normal operation when LS0 = low and
LS1 = high, high-impedance when LS1 = low)
CLK+, CLK–
J7, J6
SubLVDS output Clock; clock polarity is fixed
SubLVDS Out
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Pin Functions (continued)
NAME
PIN
I/O
DESCRIPTION
R0–R7
A5/C2, B6/C1,
A6/D2, B7/D1,
A7/E1, B8/F2,
A8/F1, B9/G2
Red Pixel Data (8); pin assignment depends on SWAP pin setting
G0–G7
B1/B5, B2/A4,
A2/B4, B3/A3,
A3/B3, B4/A2,
A4/B2, B5/B1
Green Pixel Data (8); pin assignment depends on SWAP pin setting
B0–B7
B9/G2, A8/F1,
B8/F2, A7/E1,
B7/D1, A6/D2,
B6/C1, A5/C2
Blue Pixel Data (8); pin assignment depends on SWAP pin setting
HS
H1
Horizontal Sync
VS
H2
DE
J2
PCLK
G1
Input Pixel Clock; rising or falling clock polarity is selected by control input
CPOL
LS0, LS1
C9, D8
Link Select (Determines active SubLVDS Data Links and PLL Range) See
Table 8-2
Vertical Sync
CMOS IN
Data Enable
Disables the CMOS Drivers and Turns Off the PLL, putting device in
shutdown mode
TXEN
J3
CPOL
H9
1 – Transmitter enabled
0 – Transmitter disabled
(Shutdown)
Note: The TXEN input incorporates glitch-suppression logic to avoid device
malfunction on short input spikes. It is necessary to pull TXEN high for
longer than 10 μs to enable the transmitter. It is necessary to pull the TXEN
input low for longer than 10 μs to disable the transmitter. At power up, the
transmitter is enabled immediately if TXEN = 1 and disabled if TXEN = 0
Input Clock Polarity Selection
SWAP
CMOS In
0 – rising edge clocking
1 – falling edge clocking
Bus Swap swaps the bus pins to allow device placement on top or bottom
of pcb. See pinout drawing for pin assignments.
0 – data input from B0...R7
1 – data input from R7...B0
VDD
C4
Supply Voltage
GND
A1, A9, C5, C8, D4,
D5, D6, D7, E2, E4,
E5, E6, E7, F4, F5,
F6, F7, G4, G5, G6,
G7, H3, J1
Supply Ground
VDDLVDS
H5, H8
GNDLVDS
G8, H4
SubLVDS Ground
VDDPLLA
H7
PLL analog supply Voltage
Power Supply(1)
SubLVDS I/O supply Voltage
GNDPLLA
H6
PLL analog GND
VDDPLLD
F8
PLL digital supply Voltage
GNDPLLD
E8
PLL digital GND
(1)
4
J8
CMOS In
For a multilayer pcb, it is recommended to keep one common GND layer underneath the device and connect all ground terminals
directly to this plane.
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6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VDD (2), VDDPLLA, VDDPLLD, VDDLVDS
Voltage range at any input When VDDx > 0 V
or output terminal
When VDDx ≤ 0 V
VALUE
UNIT
-0.3 to 2.175
V
-0.5 to 2.175
V
-0.5 to VDD + 2.175
V
±3
kV
±500
V
Human Body Model(3) (all Pins)
Electrostatic discharge
Charged-Device Mode(4)l (all Pins)
Machine
Model(5)
(all pins)
Continuous power dissipation
(1)
(2)
(3)
(4)
(5)
±200
See Dissipation Rating Table
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the GND terminals.
In accordance with JEDEC Standard 22, Test Method A114-A.
In accordance with JEDEC Standard 22, Test Method C101.
In accordance with JEDEC Standard 22, Test Method A115-A
6.2 Thermal Information
SN65LVDS301
THERMAL METRIC(1)
ZXH
(nFBGA)
UNIT
80 PINS
RθJA
Junction-to-ambient thermal resistance
47.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
33.1
°C/W
RθJB
Junction-to-board thermal resistance
30.1
°C/W
ψJT
Junction-to-top characterization parameter
0.7
°C/W
ψJB
Junction-to-board characterization parameter
30.0
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.3 Recommended Operating Conditions (1)
VDD
VDDPLLA
VDDPLLD
VDDLVDS
Supply voltages
VDDn(PP)
MIN
NOM
MAX
UNIT
1.65
1.8
1.95
V
Test set-up see Figure 7-5
Supply voltage noise
magnitude (all supplies)
f(PCLK) ≤ 50 MHz; f(noise) = 1 Hz to 2 GHz
100
f(PCLK) > 50 MHz; f(noise) = 1 Hz to 1 MHz
100
f(PCLK) > 50 MHz; f(noise) > 1 MHz
1-Channel transmit mode, see Figure 8-4
fPCLK
Pixel clock frequency
40
4
15
2-Channel transmit mode, see Figure 8-5
8
30
3-Channel transmit mode, see Figure 8-6
20
65
Frequency threshold Standby mode to active
mode(2), see Figure 7-9
0.5
3
tH x fPCLK
PCLK input duty cycle
0.33
0.67
TA
Operating free-air
temperature
–40
85
tjit(per)PCLK
PCLK RMS period jitter(3)
tjit(TJ)PCLK
PCLK total jitter
tjit(CC)PCLK
PCLK peak
cycle-to-cycle jitter(4)
mV
MHz
°C
5 ps-rms
Measured on PCLK input
0.05/fPCLK
s
0.02/fPCLK
s
VDD
V
PCLK, R[0:7], G[0:7], B[0:7], VS, HS, DE, PCLK, LS[1:0], CPOL, TXEN, SWAP
VIH
VIL
Low-level input voltage
tDS
Data set up time prior to
PCLK transition
tDH
Data hold time after PCLK
transition
(1)
(2)
(3)
(4)
6
High-level input voltage
0.7×VDD
0.3×VDD
f (PCLK) = 65 MHz; see Figure 7-1
V
2.0
ns
2.0
ns
Unused single-ended inputs must be held high or low to prevent them from floating.
PCLK input frequencies lower than 500 kHz force the SN65LVDS301into standby mode. Input frequencies between 500 kHz and 3
MHz may or may not activate the SN65LVDS301. Input frequencies beyond 3 MHz activate the SN65LVDS301.
Period jitter is the deviation in cycle time of a signal with respect to the ideal period over a random sample of 100,000 cycles.
Cycle-to-cycle jitter is the variation in cycle time of a signal between adjacent cycles; over a random sample of 1,000 adjacent cycle
pairs.
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6.4 Device Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAM
ETER
TEST CONDITIONS
1ChM
IDD
3ChM
MAX
fPCLK = 4 MHz
9.0
11.4
fPCLK = 6 MHz
10.6
12.6
fPCLK = 15 MHz
16
18.8
VDD =VDDPLLA=VDDPLLD=VDDLVDS, RL(PCLK)=R
L(D0)=100 Ω, VIH=VDD, VIL=0 V, TXEN at VDD,
typical power test pattern (see Table 7-2)
fPCLK = 4 MHz
8.0
UNIT
mA
fPCLK = 6 MHz
8.9
fPCLK = 15 MHz
14.0
VDD =VDDPLLA=VDDPLLD=VDDLVDS, RL(CLK)=R
Ω, VIH=VDD, VIL=0 V, TXEN at VDD,
alternating 1010 serial bit pattern;
fPCLK = 8 MHz
13.7
15.9
fPCLK = 22 MHz
18.4
22.0
fPCLK = 30 MHz
21.4
25.8
VDD =VDDPLLA=VDDPLLD=VDDLVDS, RL(PCLK)=R
L(D0)=100 Ω, VIH=VDD, VIL=0 V, TXEN at VDD,
typical power test pattern (see Table 7-3)
fPCLK = 8 MHz
11.5
fPCLK = 22 MHz
16.0
fPCLK = 30 MHz
19.1
VDD =VDDPLLA=VDDPLLD=VDDLVDS, RL(PCLK)=R
L(D0)=100 Ω, VIH=VDD, VIL=0 V, TXEN at VDD,
alternating 1010 serial bit pattern
fPCLK = 20 MHz
20.0
22.5
fPCLK = 65 MHz
29.1
36.8
VDD =VDDPLLA=VDDPLLD=VDDLVDS, RL(PCLK)=R
L(D0)=100 Ω, VIH=VDD, VIL=0 V, TXEN at VDD,
typical power test pattern (see Table 7-4)
fPCLK = 20 MHz
15.9
fPCLK = 65 MHz
24.7
VDD = VDDPLLA = VDDPLLD
= VDDLVDS, RL(PCLK)=R
L(D0)=100 Ω, VIH=VDD, V
IL=0 V, all inputs held static
high or static low
0.61
10
μA
0.55
10
μA
MAX
UNIT
Standby Mode
Shutdown Mode
(1)
TYP(1)
VDD =VDDPLLA=VDDPLLD=VDDLVDS, RL(CLK)=R
L(D0)=100 Ω, VIH=VDD, VIL=0 V, TXEN at VDD,
alternating 1010 serial bit pattern
L(Dx)=100
2ChM
MIN
mA
mA
mA
mA
mA
All typical values are at 25°C and with 1.8 V supply unless otherwise noted.
6.5 Output Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1)
subLVDS output (D0+, D0–, D1+, D1–, D2+, D1–, CLK+, and CLK–)
VOCM(SS)
Steady-state common-mode output voltage
VOCM(SS)
Change in steady-state common-mode output voltage
VOCM(PP)
Peak-to-peak common mode output voltage
|VOD|
Differential output voltage magnitude
|VDx+ – VDx– |, |VCLK+ – VCLK– |
Output load see Figure 7-3
0.9
–10
100
Δ|VOD|
Change in differential output voltage between logic states
ZOD(CLK)
Differential small-signal output impedance
TXEN at VDD
IOSD
Differential short-circuit output current
VOD = 0 V, fPCLK = 28 MHz
IOS
Short circuit output current(2)
VO = 0 V or VDD
IOZ
High-impedance state output current
VO = 0 V or VDD(max),
TXEN at GND
(1)
(2)
0.8
150
–10
1.0
10
mV
75
mV
200
10
210
mV
mV
Ω
10
5
–3
V
3
mA
μA
All typical values are at 25°C and with 1.8 V supply unless otherwise noted.
All SN65LVDS301 outputs tolerate shorts to GND or VDD without permanent device damage.
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6.6 Input Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
PCLK, R[0:7], G[0:7], B[0:7], VS, HS, DE, PCLK, LS[1:0], CPOL, TXEN, SWAP
IIH
High-level input current
VIN = 0.7 × VDD
–200
200
IIL
Low-level input current
VIN = 0.3 × VDD
–200
200
CIN
Input capacitance
(1)
1.5
nA
pF
All typical values are at 25°C and with 1.8 V supply unless otherwise noted.
6.7 Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
TYP(1)
MAX
tr
20%-to-80% differential
output signal rise time
See Figure 7-2 and Figure 7-3
250
500
tf
20%-to-80% differential
output signal fall time
See Figure 7-2 and Figure 7-3
250
500
PLL bandwidth (3dB cutoff
frequency)
fBW
tpd(L)
Propagation delay time,
input to serial output (data
latency Figure 7-4)
Tested from PCLK input to
CLK output, See Figure 6-1
(3)
TXEN at VDD, VIH=VDD, V
IL=GND, RL=100 Ω
fPCLK = 22 MHz
0.082 × fPCLK
fPCLK = 65 MHz
0.07 × fPCLK
1-channel mode
0.8/fPCLK
1/fPCLK
1.2/fPCLK
2-channel mode
1.0/fPCLK
1.21/fPCLK
1.5/fPCLK
3-channel mode
1.1/fPCLK
1.31/fPCLK
1.6/fPCLK
1-channel and 3-channel
mode
0.45
0.50
0.55
2-channel mode
0.49
0.53
0.58
tH × fCLK0
Output CLK duty cycle
tGS
TXEN Glitch suppression
pulse width(2)
VIH=VDD, VIL=GND, TXEN toggles between VIL and VIH,
see Figure 7-7 and Figure 7-8
tpwrup
Enable time from power
down (↑TXEN)
Time from TXEN pulled high to CLK and Dx outputs
enabled and transmit valid data; see Figure 7-8
tpwrdn
Disable time from active
mode (↓TXEN)
TXEN is pulled low during transmit mode; time
measurement until output is disabled and PLL is
Shutdown; see Figure 7-8
twakup
Enable time from Standby
(↕PCLK)
TXEN at VDD; device in standby; time measurement from
PCLK starts switching to CLK and Dx outputs enabled
and transmit valid data; see Figure 7-8
0.23
tsleep
Disable time from Active
mode (PCLK stopping)
TXEN at VDD; device is transmitting; time measurement
from PCLK input signal stops until CLK + Dx outputs are
disabled and PLL is disabled; see Figure 7-8
0.4
(1)
(2)
(3)
8
TEST CONDITIONS
3.8
10
0.24
2
0.5
11
UNIT
ps
MHz
s
μs
ms
μs
2
ms
100
μs
All typical values are at 25°C and with 1.8 V supply unless otherwise noted.
The TXEN input incorporates glitch-suppression circuitry to disregard short input pulses. tGS is the duration of either a high-to-low or
low-to-high transition that is suppressed.
The Maximum Limit is based on statistical analysis of the device performance over process, voltage, and temp ranges. This parameter
is functionality tested only on Automatic Test Equipment (ATE).
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12.0%
9.0
4 MHz: 8 MHz:
8.5%
8.5%
11.0%
20 MHz:
8.3%
RX PLL BW
10.0%
9%
9.0%
8.5%
8.0%
7.5%
7.0%
7%
6.0%
PLL BANDWIDTH - %
PLL BW [% of PCLK Frequency]
8.5
Spec Limit
1ChM
8.0
7.5
Spec
Limit
2ChM
30 MHz:
7.6%
15 MHz:
7.6%
Spec Limit 3ChM
7.0
65 MHz:
7.0%
TX PLL BW
6.5
5.0%
6.0
4.0%
0
100
200
300
400
500
600
700
0
10
PLL frequency − MHz
20
30
40
50
60
70
PCLK FREQUENCY - MHz
Figure 6-1. LVDS301 PLL Bandwidth (also showing the LVDS302 PLL bandwidth)
6.8 Timing Characteristics
PARAMETER
TEST CONDITIONS
MIN
1ChM: x=0..29, fPCLK=15 MHz; TXEN at
VDD, VIH=VDD, VIL=GND, RL=100 Ω, test
pattern as in Table 7-7 (3)
x
- 330 ps
30 × fPCLK
x
+ 330 ps
30 × fPCLK
x – 0.1845
30 × fPCLK
x + 0.1845
30 × fPCLK
x
- 330 ps
15 × fPCLK
x
+ 330 ps
15 × fPCLK
x – 0.1845
15 × fPCLK
x + 0.1845
15 × fPCLK
x
- 210 ps
10 × fPCLK
x
+ 210 ps
10 × fPCLK
x - 0.153
10 × fPCLK
x + 0.153
10 × fPCLK
1ChM: x=0..29,
fPCLK=4 MHz to 15 MHz (4)
tPPOSX
Output Pulse Position,
⇅serial data to ↑CLK; see (1)
(2)and Figure 7-6
2ChM: x = 0..14, fPCLK = 30 MHz
TXEN at VDD, VIH=VDD, VIL=GND, R
(3)
L=100 Ω, test pattern as in Table 7-8
2ChM: x=0..14,
fPCLK= 8 MHz to 30 MHz (4)
3ChM: x=0..9, fPCLK=65 MHz,
TXEN at VDD, VIH=VDD, VIL=GND, R
(3)
L=100 Ω, test pattern as in Table 7-9
3ChM: x=0..9,
fPCLK=20 MHz to 65 MHz (4)
(1)
(2)
(3)
(4)
TYP
MAX
UNIT
ps
This number also includes the high-frequency random and deterministic PLL clock jitter that is not traceable by the SN65LVDS302
receiver PLL; tPPosx represents the total timing uncertainty of the transmitter necessary to calculate the jitter budget when combined
with the SN65LVDS302 receiver;
The pulse position min/max variation is given with a bit error rate target of 10–12; The measurement estimates the random jitter
contribution to the total jitter contribution by multiplying the random RMS jitter by the factor 14; Measurements of the total jitter are
taken over a sample amount of > 10–12 samples.
The Minimum and Maximum Limits are based on statistical analysis of the device performance over process, voltage, and temp
ranges. This parameter is functionality tested only on Automatic Test Equipment (ATE).
These Minimum and Maximum Limits are simulated only.
6.9 Device Power Dissipation
PARAMETER
PD
Device Power
Dissipation
TEST CONDITIONS
VDDx = 1.8 V, TA = 25°C
VDDx = 1.95 V, TA = –40°C
TYP
fCLK = 4 MHz
14.4
fCLK = 65 MHz
44.5
MAX
UNIT
mW
fCLK = 4 MHz
22.3
fCLK = 65 MHz
71.8
mW
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6.10 Typical characteristics
1.0
20
2-Channel Mode, 22 MHz (VGA)
IDD - mA
IDDQ - mA
15
Standby Current
2-Channel Mode, 11 MHz (HVGA)
10
Power-Down Current
5
0.1
-50
-30
-10
10
30
50
Temperature - °C
70
0
-50
90
Figure 6-2. Powerdown, Standby Supply Current
vs Temperature
-30
-10
10
30
50
Temperature - °C
70
90
Figure 6-3. Supply Current IDD vs Temperature
200
30
Differential Output Swing VOD - mV
85°C
3-Channel Mode
25
2-Channel Mode
IDD - mA
20
15
10
1-Channel Mode
5
0
10
20
30
40
50
FREQUENCY - MHz
60
9.0
25°C
180
170
–40°C
160
150
140
130
120
110
100
0
70
Figure 6-4. Supply Current vs PCLK Frequency
190
10
20
30
40
50
FREQUENCY - MHz
60
70
Figure 6-5. Differential Output Swing vs PCLK
Frequency
500
Spec Limit 1ChM, 4 MHz: 8.5%
Spec Limit 2ChM 8 MHz: 8.5%
8.5
Spec Limit 3ChM 20 MHz: 8.3%
400
7.0
Spec Limit 1ChM,
15 MHz: 7.6%
Spec Limit 2ChM
30 MHz: 7.6%
Spec Limit 3ChM
65 MHz: 7.0%
6.5
6.0
3-ChM
2-ChM
5.5
CC JITTER - ps
PLL BANDWIDTH - %
8.0
7.5
300
200
100
5.0
4.5
4.0
0
1-Channel Mode
10
20
30
40
50
FREQUENCY - MHz
60
Figure 6-6. PLL Bandwidth
10
3-Channel Mode
70
0
0
10
20
2-Channel Mode
30
40
50
FREQUENCY - MHz
60
70
Figure 6-7. Cycle-to-cycle Output Jitter vs PCLK
Frequency
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200
2-Channel Mode,
f(PCLK) = 11 MHz
150
CC JITTER - ps
OUTPUT PULSE POSITION (tPPOS) - PS
120
100
2-Channel Mode,
f(PCLK) = 22 MHz
50
0
-50
-25
0
25
50
Temperature - °C
75
100
250
175
2-Channel Mode,
f(PCLK) = 22 MHz
0
–175
–250
100
80
60
40
20
0
-50
0
25
50
TEMPERATURE - °C
75
100
190
3-Channel Mode,
f(PCLK) = 65 MHz
0
–190
–250
200 ps/div
Figure 6-10. Data Eye Pattern, 2-channel Mode
Figure 6-11. Data Eye Pattern, 3-channel Mode
249
250
190
190
Output Voltage Amplitude - mV
Output Voltage Amplitude - mV
-25
250
500 ps/div
0
2-Channel Mode,
22 MHz (HVGA)
Figure 6-9. Output Pulse Position vs Temperature
OUTPPUT VOLTAGE AMPLITUDE ONN D1+, D1–
OUTPPUT VOLTAGE AMPLITUDE ONN D1+, D1–
Figure 6-8. Cycle-to-cycle Output Jitter vs
Temperature
2-Channel Mode,
11 MHz (VGA)
1-Channel Mode,
f(PCLK) = 5.5 MHz
–190
0
2-Channel Mode,
f(PCLK) = 22 MHz
–190
–251
–250
1 ns/div
Response Over 80-inch of FR-4 + 1m Coax Cable
Figure 6-12. QVGA Output Waveform
500 ps/div
Response Over 8-inch FR-4 + 1m Coax Cable
Figure 6-13. VGA 2-channel Output Waveform
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249
249
190
190
Output Voltage Amplitude - mV
Output Voltage Amplitude - mV
SLLS681E – FEBRUARY 2006 – REVISED OCTOBER 2020
2-Channel Mode,
f(PCLK) = 22 MHz
0
3-Channel Mode,
f(PCLK) = 22 MHz
0
–190
–190
–251
–251
1 ns/div
Response Over 80-inch FR-4 + 1m Coax Cable
500 ps/div
Response Over 80-inch FR-4 + 1m Coax Cable
Figure 6-14. VGA 2-channel Output Waveform
Figure 6-15. VGA 3-channel Output Waveform
249
Output Voltage Amplitude - mV
400 mV/div
Output Voltage Amplitude - mV
190
0
–190
3-Channel Mode,
f(PCLK) = 56 MHz
3-Channel Mode,
f(PCLK) = 56 MHz
–251
300 ps/div
Response Over 80-inch FR-4 + 1m Coax Cable
3.5 ns/div
Response With 10-pF Load
Figure 6-16. XGA 3-channel Output Waveform
Figure 6-17. XGA 3-channel Output Waveform on
the SN65LVDS302 when driven by the
SN65LVDS301
-50
0
-60
-70
OUTPUT RETURN LOSS - dB
-80
-90
dBc/Hz
-100
f(PCLK) = 65 MHz
-110
-120
-130
-140
-150
-160
–5
CLK
–10
D0
D1
D2
-170
–15
-180
1
10
100
1k
10k
100k
1M
10M
0
FREQUENCY - Hz
1000
1500
2000
FREQUENCY - Hz
Figure 6-18. PLL Phase Noise
12
500
Figure 6-19. Output Return Loss
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0
-20
–5
D0
CLK
-40
ISOLATION - dB
COMMON MODE NOISE REJECTION - dB
0
–10
D1
D2
–15
D0 to D1
-60
D0 to D2
-80
-100
–20
0
500
1000
1500
0
2000
500
FREQUENCY - MHz
1000
1500
FREQUENCY - MHz
2000
Figure 6-21. Crosstalk
Figure 6-20. Output Common Mode Noise
Rejection
20
RADIATED EMISSION - dBmV
f(PCLK)=65MHz
2-ChM, f(PCLK)=22MHz
320MHz; 16dBuV
3-ChM, f(PCLK)=65MHz,
988MHz, 12dBuV
15
2-ChM, f(PCLK)=22MHz
683MHz; 12dBuV
3-ChM, f(PCLK)=65MHz,
282MHz
3-ChM, f(PCLK)=65MHz
777MHz; 11dBuV
10
1-ChM f(PCLK)=5MHz,
960MHz; 8dBuV
3-ChM, f(PCLK)=65MHz
113MHz; 6dBuV
5
0
0
200
400
600
800
1000
FREQUENCY - MHz
Figure 6-22. GTEM SAE J1752/3 EMI Test
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7 Parameter Measurement Information
t DS
VIH
R[7:0], G[7:0], B[7:0];
VS, HS, DE, LS0, LS1,
TXEN, SWAP, CPOL
VIL
t DH
VIH
PCLK
(CPOL=low)
VIL
tR
Figure 7-1. Setup/Hold Time
VOD
tf
tr
150mV (nom)
80%
0V
20%
−150mV (nom)
Figure 7-2. Rise and Fall Time Definitions
R1 = 49.9
CLK+, Dx+
VDx+ or V CLK+
975mV (nom)
VDx− or V CLK−
825mV (nom)
VOD
CLK−, Dx−
R2 = 49.9
VOCM
VOCM
SN65LVDS301
C1 = 1 pF
C2 = 1 pF
VOCM (pp)
VOCM (ss)
NOTES:
A. 20 MHz output test pattern on all differental outputs (CLK, D0, D1, and D2):
this is achieved by: 1. Device is set to 3-channel-mode;
2. fPCLK = 20 MHz
3. Inputs R[7:3] = B[7:3] connected to VDD, all other data inputs set to GND.
B. C1, C2 and C3 includes instrumentation and fixture capacitance; tolerance± 20%; C, R1 and R2 tolerance± 1%.
C. The measurement of VOCM (pp) and VOC (ss) are taken with test equipment bandwidth >1 GHz.
Figure 7-3. Driver Output Voltage Test Circuit and Definitions
14
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CMOS
Data In
pixel (n)
pixel (n+1)
R7(n−1)
R7(n)
R7(n+1)
R6(n−1)
R6(n)
R6(n+1)
VDD /2
PCLK
t PROP
CLK−
CLK+
D0+
CP R7 R6
CP R7 R6
pixel (n−1)
pixel (n−2)
R6(n−1)
R7(n−1)
R7(n)
R6(n)
Figure 7-4. tpd(L) Propagation Delay Input to Output (LS0 = LS1 = 0; CPOL = 0)
1
Noise
Generator
100 mV
SN65LVDS301
VDDPLLD
V DDPLLA
2
1
V DD
10 mF
VDDLVDS
GND
Note: The generator regulates the
noise amplitude at point
1 to the
target amplitude given under the table
Recommended Operating Conditions
1.6 H
1.8 V
supply
Figure 7-5. Power Supply Noise Test Set-Up
tCLK+
CLK−
CLK+
Next Cycle
Current Cycle
D[0:m]+
Bit 0
Bit1
Bit2
Bitx
Bit0
Bit1
tPPOS0
Note:
1−channel mode: x=0..29; m=0
2−channel mode: x=0..14; m=1
3−channel mode: x=0....9; m=2
tPPOS1
tPPOS2
tPPOSx
Figure 7-6. tSK(0) SubLVDS Output Pulse Position Measurement
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VDD/2
TXEN
t GS
PCLK
PLL Approaches Lock
VCO Internal Signal
t pwrup
CLK
D0, D1, D2
Figure 7-7. Transmitter Behavior While Approaching Sync
10 ms
Shutdown
Mode
TXEN High > 10 ms
TXEN Low
> 10 ms
TXEN Low
> 10 ms
Transmit
Mode
Standby
Mode
PCLK
Stops or Lost
PCLK
Stops or Lost
PCLK
Active
PLL Achieved Lock
Power Up
TXEN = 1
CLK Active
Acquire
Mode
Figure 8-7. Status Detect and Operating Modes Flow Diagram
28
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Table 8-3. Status Detect and Operating Modes Descriptions
Mode
Characteristics
Conditions
Shutdown Mode
Least amount of power consumption(1) (most circuitry turned
off); All outputs are high-impedance
Standby Mode
Low power consumption (only clock activity circuit active; PLL TXEN is high; PCLK input signal is missing or
is disabled to conserve power); All outputs are highinactive(2)
impedance
Acquire Mode
PLL tries to achieve lock; All outputs are high-impedance
TXEN is high; PCLK input monitor detected input
activity
Transmit Mode
Data transfer (normal operation); Transmitter serializes data
and transmits data on serial output; unused outputs remain
high-impedance
TXEN is high and PLL is locked to incoming clock
(1)
(2)
TXEN is low(1) (2)
In Shutdown Mode, all SN65LVDS301 internal switching circuits (e.g., PLL, serializer, etc.) are turned off to minimize power
consumption. The input stage of any input pin remains active.
Leaving inputs unconnected can cause random noise to toggle the input stage and potentially harm the device. All inputs must be tied
to a valid logic level VIL or VIH during Shutdown or Standby Mode.
Table 8-4. Operating Mode Transitions
MODE TRANSITION
Shutdown → Standby
USE CASE
TRANSITION SPECIFICS
Drive TXEN high to enable
transmitter
1. TXEN high > 10 μs
2. Transmitter enters standby mode
a. All outputs are high-impedance
b. Transmitter turns on clock input monitor
Standby → Acquire
Transmitter activity detected
1. PCLK input monitor detects clock input activity;
2. Outputs remain high-impedance;
3. PLL circuit is enabled
Acquire → Transmit
Link is ready to transfer data
1. PLL is active and approaches lock
2. PLL achieved lock within 2 ms
3. Parallel Data input latches into shift register
4. CLK output turns on
5. selected Data outputs turn on and send out first serial data bit
Transmit → Standby
Request Transmitter to enter
Standby mode by stopping
PCLK
1. PCLK Input monitor detects missing PCLK
2. Transmitter indicates standby, putting all outputs into high-impedance;
3. PLL shuts down;
4. PCLK activity input monitor remains active
Transmit/Standby →
Shutdown
Turn off Transmitter
1. TXEN pulled low for longer than 10us
2. Transmitter indicates standby, putting output CLK+ and CLK– into highimpedance state;
3. Transmitter puts all other outputs into high-impedance state
4. Most IC circuitry is shut down for least power consumption
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9 Application information
9.1 Application Information
General application guidelines and hints for LVDS drivers and receivers may be found in the LVDS application
notes and design guides.
9.2 Preventing Increased Leakage Currents in Control Inputs
A floating (left open) CMOS input allows leakage currents to flow from V DD to GND. Do not leave any CMOS
Input unconnected or floating. Every input must be connected to a valid logic level V IH or V OL while power is
supplied to VDD. This also minimizes the power consumption of standby and power down mode.
9.3 VGA Application
Figure 9-1 shows a possible implementation of a VGA display. The LVDS301 interfaces to the SN65LVDS302,
which is the corresponding receiver device to deserialize the data and drive the display driver. The pixel clock
rate of 22 MHz assumes ~10% blanking overhead and 60 Hz display refresh rate. The application assumes 24bit color resolution. It is also shown, how the application processor provides a powerdown (reset) signal for both
serializer and the display driver. The signal count over the FPC could be further decreased by using the standby
option on the SN65LVDS302 and pulling RXEN high with a 30 kΩ resistor to VDD.
GND
22MHz
27
22MHz
D0+
D0D1+
D1-
PCLK
R[7:0]
G[7:0]
B[7:0]
HS,VS,DE
330Mbps
330Mbps
CLK+
CLKD0+
D0D1+
D1-
22MHz
27
SN65LVDS302
LS0
TXEN
LS1
LS0
RESET
SPI
SN65LVDS301
PCLK
R[7:0]
G[7:0]
B[7:0]
HS,VS,DE
Video Mode Display
Driver
1.8V
LCD with VGA
resolution
GND
2x0.01uF
SPI
1.8V
GND
2.7V
1.8V
ENABLE
Pixel CLK
D[7:0]
D[15:8]
D[23:16]
HS,VS,DE
2.7V
CLK+
CLK-
2x0.1uF
GND
RXEN
Application
Processor
(e.g. OMAP)
GND
VDDx
2x0.01uF
FPC
VDDx
GND
LS1
2x0.1uF
1.8V
If FPC wire count is critical , replace this
connection with a pull -up resistor at RXEN
Serial port interface
(3-wire IF)
3
Figure 9-1. Typical VGA Display Application
30
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9.4 Dual LCD-Display Application
The example in Figure 9-2 shows a possible application setup driving two video mode displays from one
application processor. The data rate of 330 Mbps at a pixel clock rate of 5.5 MHz corresponds to QVGA
resolution at 60 Hz refresh rate and 10% blanking overhead.
CLK+
CLK-
PCLK
330Mbps
Display Driver1
21
CLK+
CLKD0+
D0-
PCLK
R[5:0]
G[5:0]
B[5:0]
HS,VS,DE
PCLK
EN
SIN
SOUT
SCLK
SN65LVDS302
LS0
TXEN
LS0
LS1
SN65LVDS301
SCLK
SIN
SOUT
SEL2
SEL1
GND
5.5MHz
D0+
D0-
R[5:0]
G[5:0]
B[5:0]
HS,VS,DE
2x0.01uF
Display Driver2
PCLK
1.8V
LCD with QVGA
resolution
1.8V
EN
SIN
SOUT
SCLK
1.8V
LCD with QVGA
resolution
18+3
1.8V
RXEN
D[5:0]
D[11:6]
D[17:12]
HS,VS,DE
5.5MHz
2.7V
GND
2x0.1uF
GND
LS1
Pixel CLK
GND
VDDx
2x0.01uF
Application
Processor
(e.g. OMAP)
FPC
GND
GND
2.7V
VDDx
2x0.1uF
Figure 9-2. Example Dual-QVGA Display Application
9.5 Typical Application Frequencies
The SN65LVDS301 supports pixel clock frequencies from 4 MHz to 65 MHz over 1, 2, or 3 data lanes. Table 9-1
provides a few typical display resolution examples and shows the number of data lanes necessary to connect
the LVDS301 with the display. The blanking overhead is assumed to be 20%. Often, blanking overhead is
smaller, resulting in a lower data rate. Furthermore, the examples in the table assumes a display frame refresh
rate of 60 Hz or 90 Hz. The actual refresh rate may differ depending on the application-processor clock
implementation.
Table 9-1. Typical Application Data Rates & Serial Lane Usage
Display Screen
Resolution
176x220 (QCIF+)
Visible Pixel
Count
Blanking
Overhead
Display
Refresh
Rate
Pixel Clock Frequency
[MHz]
Serial Data Rate Per Lane
38,720
20%
90 Hz
4.2 MHz
125 Mbps
60 Hz
1-ChM
2-ChM
240x320 (QVGA)
76,800
5.5 MHz
166 Mbps
640x200
128,000
9.2 MHz
276 Mbps
138 Mbps
3-ChM
352x416 (CIF+)
146,432
10.5 MHz
316 Mbps
158 Mbps
352x440
154,880
11.2 MHz
335 Mbps
167 Mbps
320x480 (HVGA)
153,600
11.1 MHz
332 Mbps
166 Mbps
800x250
200,000
14.4 MHz
432 Mbps
216 Mbps
640x320
204,800
14.7 MHz
442 Mbps
221 Mbps
640x480 (VGA)
307,200
22.1 MHz
332 Mbps
221 Mbps
1024x320
327,680
23.6 MHz
354 Mbps
236 Mbps
854x480 (WVGA)
409,920
29.5 MHz
443 Mbps
295 Mbps
800x600 (SVGA)
480,000
34.6 MHz
346 Mbps
1024x768 (XGA)
786,432
56.6 MHz
566 Mbps
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9.5.1 Calculation Example: HVGA Display
Display Resolution:
480 x 320
Frame Refresh Rate:
58.4 Hz
Horizontal Visible Pixel:
480 columns
Horizontal Front Porch:
20 columns
Horizontal Sync:
5 columns
Horizontal Back Porch:
3 columns
Vertical Visible Pixel:
320 lines
Vertical Front Porch:
10 lines
Vertical Sync:
5 lines
Vertical Back Porch:
3 lines
Hsync = 5
HBP
This example calculation shows a typical Half-VGA display with these parameters:
Visible area = 480 column
HFP = 20
Vsync = 5
VBP = 3
Visible area
= 320 lines
VFP = 10
Visible area
Entire display
Figure 9-3. HVGA Display Parameters
Calculation of the total number of pixel and Blanking overhead:
Visible Area Pixel Count:
480 × 320 = 153600 pixel
Total Frame Pixel Count:
(480+20+5+3) × (320+10+5+3) = 171704 pixel
Blanking Overhead:
(171704-153600) ÷ 153600 = 11.8 %
The application requires following serial-link parameters:
Pixel Clk Frequency:
171704 × 58.4 Hz = 10.0 MHz
Serial Data Rate:
1-channel mode: 10.0 MHz × 30 bit/channel = 300 Mbps
2-channel mode: 10.0 MHz × 15 bit/channel = 150 Mbps
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10 Power Supply Design Recommendation
For a multilayer pcb, it is recommended to keep one common GND layer underneath the device and connect all
ground terminals directly to this plane.
10.1 Decoupling Recommendation
The SN65LVDS301 was designed to operate reliably in a constricted environment with other digital switching
ICs. In many designs, the SN65LVDS301 often shares a power supply with the application processor. The
SN65LVDS301 can operate with power supply noise as specified in Recommend Device Operating Conditions.
To minimize the power supply noise floor, provide good decoupling near the SN65LVDS301 power pins. The use
of four ceramic capacitors (2×0.01 μF and 2×0.1 μF) provides good performance. At the very least, it is
recommended to install one 0.1 μF and one 0.01 μF capacitor near the SN65LVDS301. To avoid large current
loops and trace inductance, the trace length between decoupling capacitor and IC power inputs pins must be
minimized. Placing the capacitor underneath the SN65LVDS301 on the bottom of the pcb is often a good choice.
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11 Layout
11.1 Layout Guidelines
Use chamfered corners (45° bends) instead of right-angle (90°) bends. Right-angle bends increase the effective
trace width, which changes the differential trace impedance creating large discontinuities. A 45° bend is seen as
a smaller discontinuity.
When routing traces next to a via or between an array of vias, make sure that the via clearance section does not
interrupt the path of the return current on the ground plane below.
Avoid metal layers and traces underneath or between the pads of the LVDS connectors for better impedance
matching. Otherwise they cause the differential impedance to drop below 75 Ω and fail the board during TDR
testing.
Use solid power and ground planes for 100 Ω impedance control and minimum power noise.
For a multilayer PCB, TI recommends keeping one common GND layer underneath the device and connect all
ground terminals directly to this plane. For 100 Ω differential impedance, use the smallest trace spacing
possible, which is usually specified by the PCB vendor.
Keep the trace length as short as possible to minimize attenuation.
Place bulk capacitors (10 μF) close to power sources, such as voltage regulators or where the power is supplied
to the PCB.
34
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12 Device and Documentation Support
12.1 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.2 Trademarks
FlatLink™ is a trademark of Texas Instruments.
TI E2E™ is a trademark of Texas Instruments.
nFBGA® is a registered trademark of Tessera, Inc..
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.4 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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26-May-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN65LVDS301ZXH
ACTIVE
NFBGA
ZXH
80
576
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 85
LVDS301
SN65LVDS301ZXHR
ACTIVE
NFBGA
ZXH
80
2500
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 85
LVDS301
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
