SN65LVDS311
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SLLSE31B – MAY 2010 – REVISED MARCH 2013
PROGRAMMABLE 27-BIT DISPLAY SERIAL INTERFACE TRANSMITTER
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FEATURES
1
•
•
•
•
•
•
•
•
•
2.8 × 2.8mm package size
1.8V input signal swing
24-Bit RGB Data, 3 Control Bits, 1 Parity Bit
and 2 Reserved Bits Transmitted over 1, 2 or 3
Differential Lines
SubLVDS Differential Voltage Levels
Three Operating Modes to Conserve Power
– Active-Mode QVGA 17.4mW (typ)
– Active-Mode VGA 28.8mW (typ)
– Shutdown Mode ≈ 0.5μA (typ)
– Standby Mode ≈ 0.5μA (typ)
ESD Rating > 3kV (HBM)
Pixel Clock Range of 4MHz–65MHz
Failsafe on all CMOS Inputs
Typical Application: Cameras, Embedded
Computers
When transmitting, the PLL locks to the incoming
pixel clock PCLK and generates an internal highspeed clock at the line rate of the data lines. The
parallel data is latched on the rising edge of PCLK.
The serialized data is presented on the serial outputs
D0, D1, D2 with a recreation of the Pixel clock PCLK
generated from the internal high-speed clock and
output on the CLK output. If the input clock PCLK
stops, the device enters a standby mode to conserve
power.
Two Link-Select lines LS0 and LS1 control whether 1,
2 or 3 serial links are used. The TXEN input may be
used to put the SN65LVDS311 in a shutdown mode.
The SN65LVDS311 enters an active Standby mode if
the input clock PCLK stops. This minimizes power
consumption without the need for controlling an
external pin. The SN65LVDS311 is characterized for
operation over ambient air temperatures of -40°C to
85°C. All CMOS inputs offer failsafe to protect the
input from damage during power-up and to avoid
current flow into the device inputs during power-up.
DESCRIPTION
The SN65LVDS311 serializer transmits 27 parallel
input data over 1, 2, or 3 serial output links. The
device pinout is optimized to interface with the
OMAP3630 application processor. The device loads a
shift register with the 24 pixel bits and 3 control bits
from the parallel CMOS input interface. The data are
latched into the device by the pixel clock, PCLK. In
addition to the 27 bits, the device adds a parity bit
and two reserved bits for a total number of 30 serial
bits. The parity bit allows a receiver to detect singlebit errors. Odd parity is implemented.
The serial shift register is uploaded through 1, 2, or 3
serial outputs at 30, 15, or 10 times the pixel clock
data rate. A copy of the pixel clock is output on an
additional differential output. The serial data and
clock are transmitted via Sub Low-Voltage Differential
Signaling (SubLVDS) lines. The SN65LVDS311
supports three power modes (Shutdown, Standby
and Active) to conserve power.
D
LC
Application
Processor
with CMOS
Video Interface
4
S31
LVD or 2
30
DS
V
L
LVDS301
or
LVDS311
A
DAT
CLK
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2013, Texas Instruments Incorporated
SN65LVDS311
SLLSE31B – MAY 2010 – REVISED MARCH 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Functional Block Diagram
Parity
Calculation
D0+
SubLVDS
D0-
8
R[0:7]
3x10, 2x15, or 1x30-bit parallel to serial conversion
Bit 29
Bit 28 = 0
Bit 27 = 0
G[0:7]
8
B[0:7]
8
[0..26]
HS
VS
D1+
SubLVDS
D1D2+
SubLVDS
D2-
CLK+
SubLVDS
DE
CLKiPCLK
PCLK
x10, x15, x30
x1
PLL
Multiplier
LS0
LS1
TXEN
Control /
Standby Monitor
Glitch
Suppression
PINOUT
SN65LVDS311 Top view
1
2
3
4
5
SN65LVDS311 Bottom view
6
7
A
6
5
4
3
2
1
PCLK
DE
R4
B7
G1
R2
R3
HS
VS
B6
G0
R0
R1
R5
D2P
LS0
LS1
GND
G3
G6
B0
D2N
GND
V DDPLLD
VDD
R7
R6
B1
D1P
GND
TXEN
GND
B2
G2
B4
D1N
VDDPLLA
GND
GND
B3
B5
G5
V DDLVDS
CLKP
CLKN
D0P
D0N
G7
G4
A
R3
R2
G1
B7
R4
DE
PCLK
B
B
R5
R1
R0
G0
B6
VS
HS
C
C
B0
G6
G3
GND
LS1
LS0
D2P
D
D
B1
R6
R7
VDD
V DDPLLD
GND
D2N
E
E
B4
G2
B2
GND
TXEN
GND
D1P
F
F
G5
B5
B3
GND
GND
VDDPLLA
D1N
G
G
G4
2
7
G7
D0N
D0P
CLKN
CLKP
V DDLVDS
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SLLSE31B – MAY 2010 – REVISED MARCH 2013
Table 1. SIGNAL LIST
SIGNAL
PIN
SIGNAL
SIGNAL
PIN
R0
B3
PIN
G0
SIGNAL
B4
B0
C1
PIN
PCLK
A7
R1
B2
G1
A3
B1
D1
HS
B7
R2
A2
G2
E2
B2
E3
VS
B6
R3
A1
G3
C3
B3
F3
DE
A6
R4
A5
G4
G1
B4
E1
TXEN
E5
R5
B1
G5
F1
B5
F2
LS0
C6
R6
D2
G6
C2
B6
B5
LS1
C5
R7
D3
G7
G2
B7
A4
D0P
G4
D1P
E7
D2P
C7
CLKP
G6
D0N
G3
D1N
F7
D2N
D7
CLKN
G5
VDD
D4
VDDPLLD
D5
VDDPLLA
F6
VDDLVDS
G7
GND
C4, D6, E6, E4, F4, F5
Table 2. TERMINAL FUNCTIONS
NAME
I/O
DESCRIPTION
D0+, D0–
SubLVDS Data Link (active during normal operation)
D1+, D1–
SubLVDS Data Link (active during normal operation when LS0 = high and LS1 = low, or
LS0 = low and LS1=high; high impedance if LS0 = LS1 = low)
SubLVDS Out
D2+, D2–
SubLVDS Data Link (active during normal operation when LS0 = low and LS1 = high,
high-impedance when LS1 = low)
CLK+, CLK–
SubLVDS output Clock; clock polarity is fixed
R0–R7
Red Pixel Data (8); pin assignment depends on SWAP pin setting
G0–G7
Green Pixel Data (8); pin assignment depends on SWAP pin setting
B0–B7
Blue Pixel Data (8); pin assignment depends on SWAP pin setting
HS
Horizontal Sync
VS
Vertical Sync
DE
Data Enable
PCLK
LS0, LS1
Input Pixel Clock; data are latched on rising input clock edge
CMOS IN
Link Select (Determines active SubLVDS Data Links and PLL Range) See Table 3
Disables the CMOS Drivers and Turns Off the PLL, putting device in shutdown mode
1 – Transmitter enabled
0 – Transmitter disabled
(Shutdown)
TXEN
Note: The TXEN input incorporates glitch-suppression logic to avoid device malfunction
on short input spikes. It is necessary to pull TXEN high for longer than 10 μs to enable
the transmitter. It is necessary to pull the TXEN input low for longer than 10 μs to disable
the transmitter. At power up, the transmitter is enabled immediately if TXEN = 1 and
disabled if TXEN = 0
VDD
Supply Voltage
GND
Supply Ground
VDDLVDS
SubLVDS I/O supply Voltage
GNDLVDS
VDDPLLA
Power Supply (1)
SubLVDS Ground
PLL analog supply Voltage
GNDPLLA
PLL analog GND
VDDPLLD
PLL digital supply Voltage
GNDPLLD
PLL digital GND
(1)
For a multilayer pcb, it is recommended to keep one common GND layer underneath the device and connect all ground terminals
directly to this plane.
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FUNCTIONAL DESCRIPTION
Serialization Modes
The SN65LVDS311 transmitter has three modes of operation controlled by link-select pins LS0 and LS1. Table 3
shows the serializer modes of operation.
Table 3. Logic Table: Link Select Operating Modes
LS1
LS0
Mode of Operation
Data Links Status
0
0
1ChM
1-channel mode (30-bit serialization rate)
D0 active;
D1, D2 high-impedance
0
1
2ChM
2-channel mode (15-bit serialization rate)
D0, D1 active;
D2 high-impedance
1
0
3ChM
3-channel mode (10-bit serialization rate)
D0, D1, D2 active
1
1
Reserved
Reserved
1-Channel Mode
While LS0 and LS1 are held low, the SN65LVDS311 transmits payload data over a single SubLVDS data pair,
D0. The PLL locks to PCLK and internally multiplies the clock by a factor of 30. The internal high-speed clock is
used to serialize (shift out) the data payload on D0. Two reserved bits and the parity bit are added to the data
frame. Figure 1 illustrates the timing and the mapping of the data payload into the 30-bit frame. The internal highspeed clock is divided by a factor of 30 to recreate the pixel clock, and presented on the SubLVDS CLK output.
While in this mode, the PLL can lock to a clock that is in the range of 4MHz through 15MHz. This mode is
intended for smaller video display formats (e.g. QVGA to HVGA) that do not require the full bandwidth
capabilities of the SN65LVDS311.
CLK–
CLK+
D0 +/– CHANNEL
0 CP R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0 VS HS DE 0
0
0 CP R7 R6
Figure 1. Data and Clock Output in 1-Channel Mode (LS0 and LS1 = low).
2-Channel Mode
While LS0 is held high and LS1 is held low, the SN65LVDS311 transmits payload data over two SubLVDS data
pairs, D0 and D1. The PLL locks to PCLK and internally multiplies it by a factor of 15. The internal high-speed
clock is used to serialize the data payload on D0, and D1. Two reserved bits and the parity bit are added to the
data frame. Figure 2 illustrates the timing and the mapping of the data payload into the 30-bit frame and how the
frame becomes split into the two output channels. The internal high-speed clock is divided by 15 to recreate the
pixel clock, and presented on SubLVDS CLK. The PLL can lock to a clock that is in the range of 8MHz through
30MHz in this mode. Typical applications for using the 2-channel mode are HVGA and VGA displays.
CLK–
CLK +
D0 +/– Channel CP R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 VS 0 CP R7 R6
D1 +/– Channel
0 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0 HS DE 0 G3 G2
Figure 2. Data and Clock Output in 2-Channel Mode (LS0 = high; LS1 = low).
4
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3-Channel Mode
While LS0 is held low and LS1 is held high, the SN65LVDS311 transmits payload data over three SubLVDS data
pairs D0, D1, and D2. The PLL locks to PCLK, and internally multiplies it by 10. The internal high-speed clock is
used to serialize the data payload on D0, D1, and D2. Two reserved bits and the parity bit are added to the data
frame. Figure 3 illustrates the timing and the mapping of the data payload into the 30-bit frame and how the
frame becomes split over the three output channels. The internal high speed clock is divided back down by a
factor of 10 to recreate the pixel clock and presented on SubLVDS CLK output. While in this mode, the PLL can
lock to a clock in the range of 20MHz through 65MHz. The 3-channel mode supports applications with very large
display resolutions such as VGA or XGA.
CLK CLK +
D0 +/- CHANNEL CP R7 R6 R5 R4 R3 R2 R1 R0 VS CP R7 R6
D1 +/- CHANNEL
0 G7 G6 G5 G4 G3 G2 G1 G0 HS 0 G7 G6
D2 +/- CHANNEL
0 B7 B6 B5 B4 B3 B2 B1 B0 DE 0 B7 B6
Figure 3. Data and Clock Output in 3-Channel Mode (LS0 = low; LS1 = high).
Powerdown Modes
The SN65LVDS311 Transmitter has two powerdown modes to facilitate efficient power management.
Shutdown Mode
The SN65LVDS311 enters Shutdown mode when the TXEN pin is asserted low. This turns off all transmitter
circuitry, including the CMOS input, PLL, serializer, and SubLVDS transmitter output stage. All outputs are highimpedance. Current consumption in Shutdown mode is nearly zero.
Standby Mode
The SN65LVDS311 enters the Standby mode if TXEN is high and the PCLK input frequency is less than 500kHz.
All circuitry except the PCLK input monitor is shut down, and all outputs enter high-impedance mode. The current
consumption in Standby mode is very low. When the PCLK input signal is completely stopped, the IDD current
consumption is less than 10 μA. The PCLK input must not be left floating.
NOTE
A floating (left open) CMOS input allows leakage currents to flow from VDD to GND. To
prevent large leakage current, a CMOS gate must be kept at a valid logic level, either VIH
or VIL. This can be achieved by applying an external voltage of VIH or VIL to all
SN65LVDS311 inputs.
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Active Modes
When TXEN is high and the PCLK input clock signal is faster than 3MHz, the SN65LVDS311 enters Active
mode. Current consumption in Active mode depends on operating frequency and the number of data transitions
in the data payload.
Acquire Mode (PLL approaches lock)
The PLL is enabled and attempts to lock to the input Clock. All outputs remain in high-impedance mode. When
the PLL monitor detects stable PLL operation, the device switches from Acquire to Transmit mode. For proper
device operation, the pixel clock frequency must fall within the valid fPCLK range specified under recommended
operating conditions. If the pixel clock frequency is larger than 3MHz but smaller than fPCLK(min), the
SN65LVDS311 PLL is enabled. Under such conditions, it is possible for the PLL to lock temporarily to the pixel
clock, causing the PLL monitor to release the device into transmit mode. If this happens, the PLL may or may not
be properly locked to the pixel clock input, potentially causing data errors, frequency oscillation, and PLL
deadlock (loss of VCO oscillation).
Transmit Mode
After the PLL achieves lock, the device enters the normal transmit mode. The CLK pin outputs a copy of PCLK.
Based on the selected mode of operation, the D0, D1, and D2 outputs carry the serialized data. In 1-channel
mode, outputs D1 and D2 remain high-impedance. In the 2-channel mode, output D2 remains high-impedance.
Parity Bit Generation
The SN65LVDS311 transmitter calculates the parity of the transmit data word and sets the parity bit accordingly.
The parity bit covers the 27 bit data payload consisting of 24 bits of pixel data plus VS, HS and DE. The two
reserved bits are not included in the parity generation. ODD Parity bit signaling is used. The transmitter sets the
Parity bit if the sum of the 27 data bits result in an even number of ones. The Parity bit is cleared otherwise. This
allows the receiver to verify Parity and detect single bit errors.
Status Detect and Operating Modes Flow diagram
The SN65LVDS311 switches between the power saving and active modes in the following way:
Power Up
TXEN = 0
Power Up
TXEN = 1
CLK Inactive
TXEN Low
> 10 ms
Shutdown
Mode
TXEN High > 10 ms
TXEN Low
> 10 ms
TXEN Low
> 10 ms
Transmit
Mode
Standby
Mode
PCLK
Stops or Lost
PCLK
Stops or Lost
PCLK
Active
PLL Achieved Lock
Power Up
TXEN = 1
CLK Active
Acquire
Mode
Figure 4. Status Detect and Operating Modes Flow Diagram
6
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Table 4. Status Detect and Operating Modes Descriptions
Mode
Characteristics
Conditions
Shutdown Mode
Least amount of power consumption (1) (most circuitry turned
off); All outputs are high-impedance
Standby Mode
Low power consumption (only clock activity circuit active; PLL TXEN is high; PCLK input signal is missing or
is disabled to conserve power); All outputs are highinactive (2)
impedance
Acquire Mode
PLL tries to achieve lock; All outputs are high-impedance
TXEN is high; PCLK input monitor detected input
activity
Transmit Mode
Data transfer (normal operation); Transmitter serializes data
and transmits data on serial output; unused outputs remain
high-impedance
TXEN is high and PLL is locked to incoming clock
(1)
(2)
TXEN is low (1)
(2)
In Shutdown Mode, all SN65LVDS311 internal switching circuits (e.g., PLL, serializer, etc.) are turned off to minimize power
consumption. The input stage of any input pin remains active.
Leaving inputs unconnected can cause random noise to toggle the input stage and potentially harm the device. All inputs must be tied to
a valid logic level VIL or VIH during Shutdown or Standmby Mode.
Table 5. Operating Mode Transitions
MODE TRANSITION
Shutdown → Standby
USE CASE
TRANSITION SPECIFICS
Drive TXEN high to enable
transmitter
1. TXEN high > 10 μs
2. Transmitter enters standby mode
a. All outputs are high-impedance
b. Transmitter turns on clock input monitor
Standby → Acquire
Transmitter activity detected
1. PCLK input monitor detects clock input activity;
2. Outputs remain high-impedance;
3. PLL circuit is enabled
Acquire → Transmit
Link is ready to transfer data
1. PLL is active and approaches lock
2. PLL achieved lock within 2 ms
3. Parallel Data input latches into shift register
4. CLK output turns on
5. selected Data outputs turn on and send out first serial data bit
Transmit → Standby
Request Transmitter to enter
Standby mode by stopping
PCLK
1. PCLK Input monitor detects missing PCLK
2. Transmitter indicates standby, putting all outputs into high-impedance;
3. PLL shuts down;
4. PCLK activity input monitor remains active
Transmit/Standby →
Shutdown
Turn off Transmitter
1. TXEN pulled low for longer than 10us
2. Transmitter indicates standby, putting output CLK+ and CLK– into highimpedance state;
3. Transmitter puts all other outputs into high-impedance state
4. Most IC circuitry is shut down for least power consumption
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ORDERING INFORMATION (1)
PART NUMBER
PACKAGE
SN65LVDS311YFF
Tray
YFF
SN65LVDS311YFFR
(1)
SHIPPING METHOD
Reel
Updated odering information is found in the orderable addendum at the end of this document.
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VDD
(2)
, VDDPLLA, VDDPLLD, VDDLVDS
Voltage range at any input When VDDx > 0 V
or output terminal
When VDDx ≤ 0 V
Machine Model
(2)
(3)
(4)
(5)
V
V
kV
±500
V
(all pins)
±200
Continuous power dissipation
(1)
V
-0.5 to 2.175
±3
Charged-Device Mode (4)l (all Pins)
(5)
UNIT
-0.5 to VDD + 2.175
Human Body Model (3) (all Pins)
Electrostatic discharge
VALUE
-0.3 to 2.175
See Dissipation Rating Table
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the GND terminals.
In accordance with JEDEC Standard 22, Test Method A114-A.
In accordance with JEDEC Standard 22, Test Method C101.
In accordance with JEDEC Standard 22, Test Method A115-A
DISSIPATION RATINGS
(1)
(2)
PACKAGE
CIRCUIT
BOARD MODEL
θJA < 25°C
DERATING FACTOR (1)
ABOVE TA = 25°C
TA = 85°C
POWER RATING
YFF
Low-K (2)
692mW
7.69 mW/°C
148 mW
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
In accordance with the Low-K thermal metric definitions of EIA/JESD51-2.
THERMAL CHARACTERISTICS
PARAMETER
PD
8
TEST CONDITIONS
Typical
VDDx = 1.8 V, TA = 25°C
Maximum
VDDx = 1.95 V, TA = –40°C
Device Power Dissipation
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VALUE
PCLK at 4MHz
14.4
PCLK at 65MHz
44.5
PCLK at 4MHz
22.3
PCLK=65MHz
71.8
UNIT
mW
mW
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RECOMMENDED OPERATING CONDITIONS (1)
VDD
VDDPLLA
VDDPLLD
VDDLVDS
Supply voltages
VDDn(PP)
MIN
NOM
MAX
UNIT
1.65
1.8
1.95
V
Test set-up see Figure 10
Supply voltage noise
magnitude (all supplies)
f(PCLK) ≤ 50MHz; f(noise) = 1 Hz to 2 GHz
100
f(PCLK) > 50MHz; f(noise) = 1 Hz to 1MHz
100
f(PCLK) > 50MHz; f(noise) > 1MHz
fPCLK
Pixel clock frequency
mV
40
1-Channel transmit mode, see Figure 1
4
15
2-Channel transmit mode, see Figure 2
8
30
3-Channel transmit mode, see Figure 3
20
65
Frequency threshold Standby mode to active
mode (2), see Figure 14
0.5
3
MHz
tH x fPCLK
PCLK input duty cycle
0.33
0.67
TA
Operating free-air
temperature
–40
85
°C
tjit(per)PCLK
PCLK RMS period jitter (3)
5
ps-rms
tjit(TJ)PCLK
PCLK total jitter
tjit(CC)PCLK
PCLK peak
cycle-to-cycle jitter (4)
Measured on PCLK input
0.05/fPCLK
s
0.02/fPCLK
s
VDD
V
PCLK, R[0:7], G[0:7], B[0:7], VS, HS, DE, PCLK, LS[1:0], TXEN, SWAP
VIH
High-level input voltage
VIL
Low-level input voltage
tDS
Data set up time prior to
PCLK transition
tDH
Data hold time after PCLK
transition
(1)
(2)
(3)
(4)
0.7×VDD
0.3×VDD
f (PCLK) = 65MHz; see Figure 6
V
2.0
ns
2.0
ns
Unused single-ended inputs must be held high or low to prevent them from floating.
PCLK input frequencies lower than 500kHz force the SN65LVDS311into standby mode. Input frequencies between 500kHz and 3MHz
may or may not activate the SN65LVDS311. Input frequencies beyond 3MHz activate the SN65LVDS311.
Period jitter is the deviation in cycle time of a signal with respect to the ideal period over a random sample of 100,000 cycles.
Cycle-to-cycle jitter is the variation in cycle time of a signal between adjacent cycles; over a random sample of 1,000 adjacent cycle
pairs.
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DEVICE ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAM
ETER
TEST CONDITIONS
1ChM
2ChM
IDD
3ChM
TYP (1)
MAX
VDD =VDDPLLA=VDDPLLD=VDDLVDS,
RL(PCLK)=RL(D0)=100 Ω, VIH=VDD, VIL=0 V,
TXEN at VDD,
alternating 1010 serial bit pattern
fPCLK = 4MHz
9.0
11.4
fPCLK = 6MHz
10.6
12.6
fPCLK = 15MHz
16
18.8
VDD =VDDPLLA=VDDPLLD=VDDLVDS,
RL(PCLK)=RL(D0)=100 Ω, VIH=VDD, VIL=0 V,
TXEN at VDD,
typical power test pattern (see Table 7)
fPCLK = 4MHz
8.0
fPCLK = 6MHz
8.9
fPCLK = 15MHz
14.0
VDD =VDDPLLA=VDDPLLD=VDDLVDS,
RL(PCLK)=RL(Dx)=100 Ω, VIH=VDD, VIL=0 V,
TXEN at VDD,
alternating 1010 serial bit pattern;
fPCLK = 8MHz
13.7
15.9
fPCLK = 22MHz
18.4
22.0
fPCLK = 30MHz
21.4
25.8
VDD =VDDPLLA=VDDPLLD=VDDLVDS,
RL(PCLK)=RL(D0)=100 Ω, VIH=VDD, VIL=0 V,
TXEN at VDD,
typical power test pattern (see Table 8)
fPCLK = 8MHz
11.5
fPCLK = 22MHz
16.0
fPCLK = 30MHz
19.1
VDD =VDDPLLA=VDDPLLD=VDDLVDS,
RL(PCLK)=RL(D0)=100 Ω, VIH=VDD, VIL=0 V,
TXEN at VDD,
alternating 1010 serial bit pattern
fPCLK = 20MHz
20.0
22.5
29.1
36.8
VDD =VDDPLLA=VDDPLLD=VDDLVDS,
RL(PCLK)=RL(D0)=100 Ω, VIH=VDD, VIL=0 V,
TXEN at VDD,
typical power test pattern (see Table 9)
fPCLK = 20MHz
Standby Mode
fPCLK = 65MHz
UNIT
mA
mA
mA
mA
mA
15.9
fPCLK = 65MHz
mA
24.7
VDD = VDDPLLA = VDDPLLD
= VDDLVDS,
RL(PCLK)=RL(D0)=100 Ω,
VIH=VDD, VIL=0 V, all
inputs held static high or
static low
Shutdown Mode
(1)
MIN
0.61
10
μA
0.55
10
μA
MAX
UNIT
All typical values are at 25°C and with 1.8 V supply unless otherwise noted.
OUTPUT ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP (1)
subLVDS output (D0+, D0–, D1+, D1–, D2+, D1–, CLK+, and CLK–)
VOCM(SS)
Steady-state common-mode output voltage
VOCM(SS)
Change in steady-state common-mode output voltage
VOCM(PP)
Peak-to-peak common mode output voltage
|VOD|
Differential output voltage magnitude
|VDx+ – VDx– |, |VCLK+ – VCLK– |
100
Δ|VOD|
Change in differential output voltage between logic states
–10
ZOD(CLK)
Differential small-signal output impedance
TXEN at VDD
IOSD
Differential short-circuit output current
VOD = 0 V, fPCLK = 28MHz
IOS
Short circuit output current (2)
VO = 0 V or VDD
IOZ
High-impedance state output current
VO = 0 V or VDD(max),
TXEN at GND
(1)
(2)
10
Output load see Figure 8
0.8
0.9
–10
150
1.0
V
10
mV
75
mV
200
10
mV
Ω
210
10
5
–3
mV
3
mA
μA
All typical values are at 25°C and with 1.8 V supply unless otherwise noted.
All SN65LVDS311 outputs tolerate shorts to GND or VDD without permanent device damage.
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INPUT ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1) MAX
UNIT
PCLK, R[0:7], G[0:7], B[0:7], VS, HS, DE, PCLK, LS[1:0], TXEN, SWAP
IIH
High-level input current
VIN = 0.7 × VDD
–200
200
IIL
Low-level input current
VIN = 0.3 × VDD
–200
200
CIN
Input capacitance
(1)
nA
1.5
pF
All typical values are at 25°C and with 1.8 V supply unless otherwise noted.
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
tr
20%-to-80% differential
output signal rise time
See Figure 7 and Figure 8
250
500
tf
20%-to-80% differential
output signal fall time
See Figure 7 and Figure 8
250
500
PLL bandwidth (3dB cutoff
frequency)
Tested from PCLK input to
CLK output, See Figure 5 (2)
fPCLK = 22MHz
0.082 × fPCLK
fPCLK = 65MHz
0.07 × fPCLK
Propagation delay time,
input to serial output (data
latency Figure 9)
TXEN at VDD, VIH=VDD,
VIL=GND, RL=100 Ω
1-channel mode
0.8/fPCLK
1/fPCLK
1.2/fPCLK
2-channel mode
1.0/fPCLK
1.21/fPCLK
1.5/fPCLK
3-channel mode
1.1/fPCLK
1.31/fPCLK
1.6/fPCLK
1-channel and 3-channel
mode
0.45
0.50
0.55
2-channel mode
0.49
0.53
0.58
fBW
tpd(L)
tH × fCLK0
Output CLK duty cycle
tGS
TXEN Glitch suppression
pulse width (3)
VIH=VDD, VIL=GND, TXEN toggles between VIL and VIH,
see Figure 12 and Figure 13
tpwrup
Enable time from power
down (↑TXEN)
Time from TXEN pulled high to CLK and Dx outputs
enabled and transmit valid data; see Figure 13
tpwrdn
Disable time from active
mode (↓TXEN)
twakup
tsleep
(1)
(2)
(3)
3.8
10
0.24
2
TXEN is pulled low during transmit mode; time
measurement until output is disabled and PLL is Shutdown;
see Figure 13
0.5
11
Enable time from Standby
(↕PCLK)
TXEN at VDD; device in standby; time measurement from
PCLK starts switching to CLK and Dx outputs enabled and
transmit valid data; see Figure 13
0.23
Disable time from Active
mode (PCLK stopping)
TXEN at VDD; device is transmitting; time measurement
from PCLK input signal stops until CLK + Dx outputs are
disabled and PLL is disabled; see Figure 13
UNIT
ps
MHz
s
μs
ms
μs
2
ms
0.4
100
μs
All typical values are at 25°C and with 1.8 V supply unless otherwise noted.
The Maximum Limit is based on statistical analysis of the device performance over process, voltage, and temp ranges. This parameter
is functionality tested only on Automatic Test Equipment (ATE).
The TXEN input incorporates glitch-suppression circuitry to disregard short input pulses. tGS is the duration of either a high-to-low or lowto-high transition that is suppressed.
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12.0%
9.0
4 MHz: 8 MHz:
8.5%
8.5%
11.0%
20 MHz:
8.3%
RX PLL BW
10.0%
9%
9.0%
8.5%
8.0%
7.5%
7.0%
7%
6.0%
PLL BANDWIDTH - %
PLL BW [% of PCLK Frequency]
8.5
Spec Limit
1ChM
8.0
7.5
Spec
Limit
2ChM
30 MHz:
7.6%
15 MHz:
7.6%
Spec Limit 3ChM
7.0
65 MHz:
7.0%
TX PLL BW
6.5
5.0%
6.0
4.0%
0
100
200
300
400
500
600
700
0
10
20
PLL frequency − MHz
30
40
50
60
70
PCLK FREQUENCY - MHz
Figure 5. LVDS311 PLL Bandwidth (also showing the LVDS302 PLL bandwidth)
TIMING CHARACTERISTICS
PARAMETER
TEST CONDITIONS
MIN
1ChM: x=0..29, fPCLK=15MHz; TXEN at
VDD, VIH=VDD, VIL=GND, RL=100 Ω, test
pattern as in Table 12 (3)
x
- 330 ps
30 × fPCLK
x
+ 330 ps
30 × fPCLK
x – 0.1845
30 × fPCLK
x + 0.1845
30 × fPCLK
x
- 330 ps
15 × fPCLK
x
+ 330 ps
15 × fPCLK
x – 0.1845
15 × fPCLK
x + 0.1845
15 × fPCLK
x
- 210 ps
10 × fPCLK
x
+ 210 ps
10 × fPCLK
x - 0.153
10 × fPCLK
x + 0.153
10 × fPCLK
1ChM: x=0..29,
fPCLK=4MHz to 15MHz
tPPOSX
Output Pulse Position,
⇅serial data to ↑CLK; see
(1) (2)
and Figure 11
(4)
2ChM: x = 0..14, fPCLK = 30MHz
TXEN at VDD, VIH=VDD, VIL=GND,
RL=100 Ω, test pattern as in Table 13
2ChM: x=0..14,
fPCLK= 8MHz to 30MHz
(4)
3ChM: x=0..9, fPCLK=65MHz,
TXEN at VDD, VIH=VDD, VIL=GND,
RL=100 Ω, test pattern as in Table 14
3ChM: x=0..9,
fPCLK=20MHz to 65MHz
(1)
(2)
(3)
(4)
12
(3)
(4)
(3)
TYP
MAX
UNIT
ps
This number also includes the high-frequency random and deterministic PLL clock jitter that is not traceable by the SN65LVDS302
receiver PLL; tPPosx represents the total timing uncertainty of the transmitter necessary to calculate the jitter budget when combined
with the SN65LVDS302 receiver;
The pulse position min/max variation is given with a bit error rate target of 10–12; The measurement estimates the random jitter
contribution to the total jitter contribution by multiplying the random RMS jitter by the factor 14; Measurements of the total jitter are taken
over a sample amount of > 10–12 samples.
The Minimum and Maximum Limits are based on statistical analysis of the device performance over process, voltage, and temp ranges.
This parameter is functionality tested only on Automatic Test Equipment (ATE).
These Minimum and Maximum Limits are simulated only.
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PARAMETER MEASUREMENT INFORMATION
t DS
VIH
R[7:0], G[7:0], B[7:0];
VS, HS, DE, LS0, LS1,
TXEN, SWAP
VIL
t DH
VIH
PCLK
VIL
tR
Figure 6. Setup/Hold Time
VOD
tf
tr
150mV (nom)
80%
0V
20%
−150mV (nom)
Figure 7. Rise and Fall Time Definitions
R1 = 49.9
CLK+, Dx+
VDx+ or V CLK+
975mV (nom)
VDx− or V CLK−
825mV (nom)
VOD
CLK−, Dx−
R2 = 49.9
VOCM
VOCM
SN65LVDS311
C1 = 1 pF
C2 = 1 pF
VOCM (pp)
VOCM (ss)
NOTES:
A. 20 MHz output test pattern on all differental outputs (CLK, D0, D1, and D2):
this is achieved by: 1. Device is set to 3-channel-mode;
2. fPCLK = 20 MHz
3. Inputs R[7:3] = B[7:3] connected to VDD, all other data inputs set to GND.
B. C1, C2 and C3 includes instrumentation and fixture capacitance; tolerance± 20%; C, R1 and R2 tolerance± 1%.
C. The measurement of VOCM (pp) and VOC (ss) are taken with test equipment bandwidth >1 GHz.
Figure 8. Driver Output Voltage Test Circuit and Definitions
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CMOS
Data In
pixel (n)
pixel (n+1)
R7(n−1)
R7(n)
R7(n+1)
R6(n−1)
R6(n)
R6(n+1)
VDD /2
PCLK
t PROP
CLK−
CLK+
D0+
CP R7 R6
CP R7 R6
pixel (n−1)
pixel (n−2)
R6(n−1)
R7(n−1)
R7(n)
R6(n)
Figure 9. tpd(L) Propagation Delay Input to Output (LS0 = LS1 = 0)
1
Noise
Generator
100mV
SN65LVDS311
VDDPLLD
V DDPLLA
V DD
2
1
10mF
VDDLVDS
GND
Note: The generator regulates the
noise amplitude at point 1 to the
target amplitude given under the table
Recommended Operating Conditions
1.6mH
1.8V
supply
Figure 10. Power Supply Noise Test Set-Up
tCLK+
CLK−
CLK+
Next Cycle
Current Cycle
D[0:m]+
Bit 0
Bit1
Bit2
Bitx
Bit0
Bit1
tPPOS0
Note:
1−channel mode: x=0..29; m=0
2−channel mode: x=0..14; m=1
3−channel mode: x=0....9; m=2
tPPOS1
tPPOS2
tPPOSx
Figure 11. tSK(0) SubLVDS Output Pulse Position Measurement
14
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SLLSE31B – MAY 2010 – REVISED MARCH 2013
VDD/2
TXEN
t GS
PCLK
PLL Approaches Lock
VCO Internal Signal
t pwrup
CLK
D0, D1, D2
Figure 12. Transmitter Behavior While Approaching Sync
