SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS448A – SEPTEMBER 2000 – REVISED MAY 2001
D
D
D
D
D
D
D
D
D
D
D
Eight Line Receivers Meet or Exceed the
Requirements of ANSI TIA/EIA-644
Standard
Integrated 110-Ω Line Termination
Resistors on LVDT Products
Designed for Signaling Rates† Up To
630 Mbps
SN65 Version’s Bus-Terminal ESD Exceeds
15 kV
Operates From a Single 3.3-V Supply
Propagation Delay Time of 2.6 ns (Typ)
Output Skew 100 ps (Typ)
Part-To-Part Skew Is Less Than 1 ns
LVTTL Levels Are 5-V Tolerant
Open-Circuit Fail Safe
Flow-Through Pin Out
Packaged in Thin Shrink Small-Outline
Package With 20-mil Terminal Pitch
NOT RECOMMENDED FOR NEW DESIGNS
For Replacement Use ’LVDx388A
’LVDS388, ’LVDT388
DBT PACKAGE
(TOP VIEW)
A1A
A1B
A2A
A2B
NC
B1A
B1B
B2A
B2B
NC
C1A
C1B
C2A
C2B
NC
D1A
D1B
D2A
D2B
description
The ‘LVDS388 and ‘LVDT388 (T designates
integrated termination) are eight differential line
receivers that implement the electrical characteristics of low-voltage differential signaling (LVDS).
This signaling technique lowers the output voltage
levels of 5-V differential standard levels (such as
EIA/TIA-422B) to reduce the power, increase the
switching speeds, and allow operation with a 3-V
supply rail. Any of the eight differential receivers
will provide a valid logical output state with a
+100-mV differential input voltage within the input
common-mode voltage range. The input
common-mode voltage range allows 1 V of
ground potential difference between two LVDS
nodes. Additionally, the high-speed switching of
LVDS signals always require the use of a line
impedance matching resistor at the receiving end
of the cable or transmission media. The LVDT
product eliminates this external resistor by
integrating it with the receiver.
1
38
2
37
3
36
4
35
5
34
6
33
7
32
8
31
9
30
10
29
11
28
12
27
13
26
14
25
15
24
16
23
17
22
18
21
19
20
GND
VCC
ENA
A1Y
A2Y
ENB
B1Y
B2Y
GND
VCC
GND
C1Y
C2Y
ENC
D1Y
D2Y
END
VCC
GND
logic diagram (positive logic)
’LVDx388
’LVDT388 ONLY
1A
1Y
1B
EN
2A
2Y
2B
(1/4 of ’LVDx388 shown)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
† Signaling rate, 1/t, where t is the minimum unit interval and is expressed in the units bits/s (bits per second)
Copyright 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS448A – SEPTEMBER 2000 – REVISED MAY 2001
description (continued)
The intended application of this device and signaling technique is for point-to-point baseband data transmission
over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board
traces, backplanes, or cables. The large number of drivers integrated into the same substrate along with the
low pulse skew of balanced signaling, allows extremely precise timing alignment of clock and data for
synchronous parallel data transfers. When used with its companion, 8-channel driver, the SN65LVDS389 over
150 million data transfers per second in single-edge clocked systems are possible with very little power. Note:
The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media,
the noise coupling to the environment, and other system characteristics.
The SN65LVDS388 and SN65LVDT388 is characterized for operation from –40°C to 85°C. The SN75LVDS388
and SN75LVDT388 is characterized for operation from 0°C to 70°C.
AVAILABLE OPTIONS
PART NUMBER
TEMPERATURE
RANGE
NUMBER OF
RECEIVERS
BUS-PIN ESD
SN65LVDS388DBT
–40°C to 85°C
8
15 kV
SN65LVDT388DBT
–40°C to 85°C
8
15 kV
SN75LVDS388DBT
0°C to 70°C
8
4 kV
SN75LVDT388DBT
0°C to 70°C
8
4 kV
Function Table
SNx5LVD388 and SNx5LVDT388
DIFFERENTIAL INPUT
ENABLES
OUTPUT
A-B
EN
Y
VID ≥ 100 mV
-100 mV < VID ≤ 100 mV
H
H
H
?
VID ≤ -100 mV
X
H
L
L
Z
Open
H
H
H = high level, L = low level, X = irrelevant,
Z = high impedance (off), ? = indeterminate
equivalent input and output schematic diagrams
VCC
VCC
300 kΩ
VCC
300 kΩ
400 Ω
5Ω
EN
Y Output
A Input
B Input
7V
7V
300 kΩ
7V
7V
110 Ω
’LVDT Devices Only
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS448A – SEPTEMBER 2000 – REVISED MAY 2001
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4 V
Voltage range:
Enables or Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 6 V
A or B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4 V
Electrostatic discharge: (see Note 2)
SN65’ (A, B, and GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3, A:15 kV, B: 700 V
SN75’ (A, B, and GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2, A:4 kV, B: 400 V
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 in) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
2. Tested in accordance with MIL-STD-883C Method 3015.7.
PACKAGE
DISSIPATION RATING TABLE
DERATING FACTOR‡
ABOVE TA = 25°C
TA ≤ 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
DBT
1071 mW
8.5 mW/°C
688 mW
‡ This is the inverse of the junction-to-ambient thermal resistance when board-mounted (low-k) and with no air flow.
556 mW
recommended operating conditions
MIN
NOM
3
3.3
Supply voltage, VCC
High-level input voltage, VIH
Enables
Low-level input voltage, VIL
Enables
MAX
3.6
2
Magnitude of differential input voltage, VID
ID
2
Operating
O
erating free-air tem
temperature
erature, TA
POST OFFICE BOX 655303
|
2.4
0.8
V
0.6
V
* |V2ID|
V
°C
°C
SN75’
0
VCC – 0.8
70
SN65’
– 40
85
• DALLAS, TEXAS 75265
V
V
0.1
|V
Common-mode input voltage, VIC (see Figure 4)
UNIT
3
SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS448A – SEPTEMBER 2000 – REVISED MAY 2001
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
VIT+
VIT–
VOH
VOL
ICC
II
TEST CONDITIONS
Positive-going differential input voltage threshold
See Figure 1 and Table 1
Negative-going differential input voltage threshold
High-level output voltage
IOH = –8 mA
IOL = 8 mA
Low-level output voltage
Enabled,
Supply current
MIN
TYP†
No load
’LVDT
VI = 0 V, other input open
VI = 2.4 V, other input open
VIB = 0.1 V,
VIB = 2.3 V
Input current (A or B inputs)
mV
IID
Differential input current |IIA – IIB|
‘LVDS
IID
Differential input current (IIA – IIB)
‘LVDT
VIA = 0.2 V,
VIA = 2.4 V,
VIB = 0 V,
VIB = 2.2 V
II(OFF)
II(OFF)
Power-off input current (A or B inputs)
‘LVDS
VI = 2.4 V
Power-off input current (A or B inputs)
‘LVDT
VCC = 0 V,
VCC = 0 V,
IIH
IIL
High-level input current (enables)
0.4
V
50
70
mA
3
mA
IOZ
High impedance output current
High-impedance
CIN
Input capacitance, A or B input to GND
–40
1.5
12
±2
µA
2.2
mA
±20
µA
±40
µA
10
µA
10
µA
±1
VO = 0 V
VO = 3.6 V
Z(t)
Termination impedance
† All typical values are at 25°C and with a 3.3-V supply.
µA
–2.4
VI = 2.4 V
VID = 0.4 sin 2.5E09 t V
VID = 0.4 sin 2.5E09 t V
–20
–3
VIH = 2 V
VIL = 0.8 V
Low-level input current (enables)
V
0.2
–13
–1.2
VIA = 0 V,
VIA = 2.4 V,
mV
3
Disabled
VI = 0 V
VI = 2.4 V
UNIT
100
–100
2.4
’LVDS
MAX
10
5
88
µA
pF
132
Ω
switching characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP†
MAX
UNIT
tPLH
tPHL
Propagation delay time, low-to-high-level output
1
2.6
4
ns
Propagation delay time, high-to-low-level output
1
2.5
4
ns
tr
tf
Output signal rise time
500
800
1200
ps
500
800
1200
ps
tsk(p)
Pulse skew (|tPHL – tPLH|)
150
600
ps
tsk(o)
tsk(pp)
Output skew‡
100
400
ps
1
ns
tPZH
tPZL
Propagation delay time, high-impedance-to-high-level output
7
15
ns
7
15
ns
tPHZ
tPLZ
Propagation delay time, high-level-to-high-impedance output
7
15
ns
7
15
ns
Output signal fall time
See Figure
2
g
Part-to-part skew§
Propagation delay time, high-impedance-to-low-level output
See Figure 3
Propagation delay time, low-level-to-high-impedance output
† All typical values are at 25°C and with a 3.3-V supply.
‡ tsk(o) is the magnitude of the time difference between the tPLH or tPHL of all drivers of a single device with all of their inputs connected together.
§ tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of any two devices characterized in this data
sheet when both devices operate with the same supply voltage, at the same temperature, and have the same test circuits.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS448A – SEPTEMBER 2000 – REVISED MAY 2001
PARAMETER MEASUREMENT INFORMATION
A
V
IA
) VIB
VID
2
R
VIA
B
VIC
VO
VIB
Figure 1. Voltage Definitions
Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages
APPLIED VOLTAGES
RESULTING DIFFERENTIAL
INPUT VOLTAGE
RESULTING COMMONMODE INPUT VOLTAGE
VIA
1.25 V
VIB
1.15 V
VID
100 mV
VIC
1.2 V
1.15 V
1.25 V
–100 mV
1.2 V
2.4 V
2.3 V
100 mV
2.35 V
2.3 V
2.4 V
–100 mV
2.35 V
0.1 V
0V
100 mV
0.05 V
0V
0.1 V
–100 mV
0.05 V
1.5 V
0.9 V
600 mV
1.2 V
0.9 V
1.5 V
–600 mV
1.2 V
2.4 V
1.8 V
600 mV
2.1 V
1.8 V
2.4 V
–600 mV
2.1 V
0.6 V
0V
600 mV
0.3 V
0V
0.6 V
–600 mV
0.3 V
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS448A – SEPTEMBER 2000 – REVISED MAY 2001
PARAMETER MEASUREMENT INFORMATION
VID
VIA
VIB
CL
10 pF
VO
VIA
1.4 V
VIB
1V
VID
0.4 V
0V
– 0.4 V
tPHL
VO
tPLH
VOH
80%
1.5 V
20%
VOL
tf
tr
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse
width = 10 ± 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
Figure 2. Timing Test Circuit and Wave Forms
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS448A – SEPTEMBER 2000 – REVISED MAY 2001
PARAMETER MEASUREMENT INFORMATION
1.2 V
B
500 Ω
A
Inputs
EN
CL
10 pF
+
–
VO
VTEST
NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,
pulse width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
2.5 V
VTEST
A
1V
2V
1.4 V
EN
0.8 V
tPZL
tPLZ
2.5 V
1.4 V
Y
VOL +0.5 V
VOL
0V
VTEST
A
1.4 V
2V
EN
1.4 V
0.8 V
tPZH
Y
tPHZ
VOH
1.4 V
VOH –0.5 V
0V
Figure 3. Enable/Disable Time Test Circuit and Wave Forms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS448A – SEPTEMBER 2000 – REVISED MAY 2001
TYPICAL CHARACTERISTICS
LVDx388
SUPPLY CURRENT
vs
SWITCHING FREQUENCY
COMMON-MODE INPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
200
2.5
180
Max at VCC = 3 V
2.0
160
I CC – Supply Current – mA
VIC – Common-Mode Input Voltage – V
Max at VCC > 3.15 V
1.5
1.0
VCC = 3.6 V
140
120
VCC = 3 V
100
80
VCC = 3.3 V
60
40
0.5
Minimum
20
0
0
0
0.1
0.2
0.3
0.4
0.5
0
0.6
20
40
60
Figure 4
Figure 5
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
4.0
5.0
3.5
4.5
VOL – Low-Level Output Voltage – V
VOH – High-Level Output Voltage – V
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
3.0
2.5
2.0
1.5
1.0
0.5
0
–70
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
–60
–50
–40
–30
–20
–10
0
IOH – High-Level Output Current – mA
0
0
10
20
30
40
Figure 7
POST OFFICE BOX 655303
50
60
IOL – Low-Level Output Current – mA
Figure 6
8
80 100 120 140 160 180 200
f – Switching Frequency – MHz
|VID| – Differential Input Voltage – V
• DALLAS, TEXAS 75265
70
80
SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS448A – SEPTEMBER 2000 – REVISED MAY 2001
TYPICAL CHARACTERISTICS
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
3.0
t PHL – High-To-Low Propagation Delay Time – ns
t PLH – Low-To-High Propagation Delay Time – ns
LOW-TO-HIGH PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
2.9
2.8
VCC = 3 V
2.7
2.6
VCC = 3.6 V
2.5
2.4
VCC = 3.3 V
2.3
2.2
2.1
2
–50
–30
–10
10
30
50
70
90
Ta – Free-Air Temperature – °C
3.0
2.9
2.8
2.7
2.6
2.5
VCC = 3 V
VCC = 3.6 V
2.4
2.3
2.2
VCC = 3.3 V
2.1
2
–50
–30
–10
10
30
50
70
90
TA – Free-Air Temperature – °C
Figure 8
Figure 9
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS448A – SEPTEMBER 2000 – REVISED MAY 2001
APPLICATION INFORMATION
Host
Host
Controller
Power
Balanced Interconnect
Power
Target
T
DBn
DBn
Target
Controller
T
DBn–1
DBn–1
T
DBn–2
DBn–2
T
DBn–3
DBn–3
T
DB2
DB2
T
DB1
DB1
T
DB0
DB0
T
TX Clock
RX Clock
LVDx386, LVDx388,
LVDx388A, or LVDx390
LVDS Drivers
Indicates twisting of the
conductors.
Figure 10. Typical Application Schematic
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
Indicates the line termination
T circuit.
SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS448A – SEPTEMBER 2000 – REVISED MAY 2001
APPLICATION INFORMATION
fail safe
One of the most common problems with differential signaling applications is how the system responds when
no differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in
that its output logic state can be indeterminate when the differential input voltage is between –100 mV and
100 mV and within its recommended input common-mode voltage range. TI’s LVDS receiver is different in how
it handles the open-input circuit situation, however.
Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be
when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver
will pull each line of the signal pair to near VCC through 300-kΩ resistors as shown in Figure 10. The fail-safe
feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the
output to a high-level regardless of the differential input voltage.
VCC
300 kΩ
300 kΩ
A
Rt = 100 Ω (Typ)
Y
B
VIT ≈ 2.3 V
Figure 11. Open-Circuit Fail Safe of the LVDS Receiver
It is only under these conditions that the output of the receiver will be valid with less than a 100-mV differential
input voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as
long as it is connected as shown in the figure. Other termination circuits may allow a dc current to ground that
could defeat the pullup currents from the receiver and the fail-safe feature.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS448A – SEPTEMBER 2000 – REVISED MAY 2001
MECHANICAL DATA
DBT (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
30 PINS SHOWN
0,50
0,27
0,17
30
16
0,08 M
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
15
0°– 8°
0,75
0,50
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
28
30
38
44
50
A MAX
7,90
7,90
9,80
11,10
12,60
A MIN
7,70
7,70
9,60
10,90
12,40
DIM
4073252/D 09/97
NOTES: A.
B.
C.
D.
12
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
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PACKAGE OPTION ADDENDUM
www.ti.com
28-Aug-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN65LVDS388DBT
NRND
TSSOP
DBT
38
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
SN65LVDT388DBT
OBSOLETE
TSSOP
DBT
38
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
SN65LVDT388DBTG4
OBSOLETE
TSSOP
DBT
38
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
SN65LVDT388DBTR
OBSOLETE
TSSOP
DBT
38
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN65LVDT388DBTR
Package Package Pins
Type Drawing
TSSOP
DBT
38
SPQ
0
Reel
Reel
Diameter Width
(mm) W1 (mm)
330.0
16.4
Pack Materials-Page 1
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
6.9
10.2
1.8
12.0
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN65LVDT388DBTR
TSSOP
DBT
38
0
346.0
346.0
33.0
Pack Materials-Page 2
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