SN65LVDS4RSET

Product Folder Sample & Buy Technical Documents Support & Community Tools & Software SN65LVDS4 SLLSE15A – JULY 2011 – REVISED NOVEMBER 2015 SN65LVDS4 1.8-V High-Speed Differential Line Receiver 1 Features 2 Applications • • • • 1 (1) • • • • • • • • • Designed for Signaling Rates up to: – 500-Mbps Receiver The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second) Operates From a 1.8-V or 2.5-V Core Supply Available in 1.5-mm × 2-mm UQFN Package Bus-Terminal ESD Exceeds 2 kV (HBM) Low-Voltage Differential Signaling With Typical Output Voltages of 350 mV Into a 100-Ω Load Propagation Delay Times – 2.1 ns Typical Receiver Power Dissipation at 250 MHz – 40 mW Typical Requires External Failsafe Differential Input Voltage Threshold Less Than 50 mV Can Provide Output Voltage Logic Level (3.3-V LVTTL, 2.5-V LVCMOS, 1.8-V LVCMOS) Based on External VDD Pin, Thus Eliminating External Level Translation Clock Distribution Wireless Base Stations Network Routers 3 Description The SN65LVDS4 is a single, low-voltage, differential line receiver in a small-outline UQFN package. Device Information(1) PART NUMBER SN65LVDS4 PACKAGE UQFN (10) BODY SIZE (NOM) 1.50 mm × 2.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Typical Application Circuits 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN65LVDS4 SLLSE15A – JULY 2011 – REVISED NOVEMBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 3 4 4 4 5 5 6 6 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Receiver Electrical Characteristics: VCC = 2.5 V ...... Receiver Electrical Characteristics: VCC = 1.8 V ...... Receiver Switching Characteristics: VCC = 2.5 V...... Receiver Switching Characteristics: VCC = 1.8 V...... Typical Characteristics .............................................. Parameter Measurement Information ................ 10 Detailed Description ............................................ 12 8.1 8.2 8.3 8.4 9 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 12 12 12 13 Application and Implementation ........................ 14 9.1 Application Information............................................ 14 9.2 Typical Application .................................................. 15 10 Power Supply Recommendations ..................... 19 11 Layout................................................................... 20 11.1 Layout Guidelines ................................................. 20 11.2 Layout Example .................................................... 23 12 Device and Documentation Support ................. 24 12.1 12.2 12.3 12.4 Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 24 24 24 24 13 Mechanical, Packaging, and Orderable Information ........................................................... 24 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (July 2011) to Revision A • 2 Page Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: SN65LVDS4 SN65LVDS4 www.ti.com SLLSE15A – JULY 2011 – REVISED NOVEMBER 2015 5 Pin Configuration and Functions RSE Package 10-Pin UQFN (Bottom View) (Top View) VDD VDD 10 10 NC 9 1 GND GND 1 9 NC R R 8 2 A A 2 8 GND 7 3 B B 3 7 GND NC 6 4 NC NC 4 6 NC 5 5 VCC VCC Pin Functions PIN NAME I/O NO. DESCRIPTION A 2 I LVDS input, positive B 3 I LVDS input, negative GND 1, 7 – Ground 4, 6, 9 – No connect 8 O 1.8/2.5 LVCMOS/3.3 LVTTL output VCC 5 – Core supply voltage VDD 10 – Output drive voltage NC R 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) Supply voltage range, VCC (2) MIN MAX UNIT –0.5 4 V Receiver output voltage logic level and driver input voltage logic level supply, VDD –0.5 4 V Input voltage range, VI (A or B) –0.5 VCC + 0.3 V Output voltage, VO (R) –0.5 VDD + 0.3 V 1 V 12 mA Differential input voltage magnitude, |VID| Receiver output current, IO –12 Continuous total power dissipation, PD See Thermal Information Storage temperature (non operating) –65 (1) (2) 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: SN65LVDS4 3 SN65LVDS4 SLLSE15A – JULY 2011 – REVISED NOVEMBER 2015 www.ti.com 6.2 ESD Ratings VALUE Electrostatic discharge V(ESD) (1) (2) Human body model (HBM), per ANSI/ESDA/JEDEC JS001 (1) All pins 2000 Bus pins (A, B, Y, Z) 2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) UNIT V 500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions MIN NOM MAX UNIT VCC1.8 Core supply voltage 1.62 1.8 1.98 V VCC2.5 Core supply voltage 2.25 2.5 2.75 V VDD1.8 Output drive voltage 1.62 1.8 1.98 V VDD2.5 Output drive voltage 2.25 2.5 2.75 V VDD3.3 Output drive voltage 3 3.3 3.6 V TA Operating free-air temperature –40 85 °C |VID| Magnitude of differential input voltage 0.15 0.6 V fop Operating frequency range 10 250 MHz |VINMAX| Input voltage (any combination of input or common-mode voltage) See (1) Maximum Input Voltage, VIN(max). 0 VCC V (1) Any combination of input or common-mode voltage should not be below 0 V or above VCC. 6.4 Thermal Information SN65LVDS4 THERMAL METRIC (1) RSE (UQFN) UNIT 10 PINS RθJA Junction-to-ambient thermal resistance 171.2 °C/W RθJC(top) Junction-to-case (top) thermal resistance 60.7 °C/W RθJB Junction-to-board thermal resistance 71.4 °C/W ψJT Junction-to-top characterization parameter 0.8 °C/W ψJB Junction-to-board characterization parameter 64.7 °C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: SN65LVDS4 SN65LVDS4 www.ti.com SLLSE15A – JULY 2011 – REVISED NOVEMBER 2015 6.5 Receiver Electrical Characteristics: VCC = 2.5 V over recommended operating conditions, VCC = 2.5 V, VID = 150 mV–600 mV, VCM = VID/2 to VCC – VID/2 V, 10 pF load (unless otherwise noted) PARAMETER VITH+ Positive-going differential input voltage threshold See Figure 17, VCC1.8 , VCC2.5 VITH– Negative-going differential input voltage threshold See Figure 17, VCC1.8 , VCC2.5 VOH High-level output voltage VOL MIN (1) TYP (2) MAX TEST CONDITIONS Low-level output voltage 50 –50 VDD = 3.3 V, IOH = –8 mA VDD – 0.25 VDD = 2.5 V, IOH = –6 mA VDD – 0.25 VDD = 1.8 V, IOH = –4 mA VDD – 0.25 UNIT mV mV V VDD = 3.3 V, IOL = 8 mA 0.25 VDD = 2.5 V, IOL = 6 mA 0.25 VDD = 1.8 V, IOL = 4 mA 0.25 No load, steady state, VDD = 3.3 V, VID+ 22 28 No load, steady state, VDD = 2.5 V, VID+ 20 25 V Pstatic Static power CI Input capacitance VI = 0.4 sin(4E6πt) + 0.5 V 4 pF CO Output capacitance VI = 0.4 sin(4E6πt) + 0.5 V 4 pF (1) (2) mW The algebraic convention, in which the least positive (most negative) limit is designated as a minimum, is used in this data sheet. All typical values are at 25°C . 6.6 Receiver Electrical Characteristics: VCC = 1.8 V over recommended operating conditions, VCC = 1.8 V, VID = 150 mV–600 mV, VCM = VID/2 to VCC – VID/2 V, 10 pF load (unless otherwise noted) PARAMETER VITH+ Positive-going differential input voltage threshold VITH– Negative-going differential input voltage threshold See Figure 17, VCC1.8 , VCC2.5 VOH High-level output voltage VOL Low-level output voltage Pstatic Static power MIN (1) TEST CONDITIONS TYP (2) See Figure 17, VCC1.8 , VCC2.5 MAX 50 –50 VDD = 3.3 V, IOH = –8 mA VDD – 0.25 VDD = 2.5 V, IOH = –6 mA VDD – 0.25 VDD = 1.8 V, IOH = –4 mA VDD – 0.25 UNIT mV mV V VDD = 3.3 V, IOL = 8 mA 0.25 VDD = 2.5 V, IOL = 6 mA 0.25 VDD = 1.8 V, IOL = 4 mA 0.25 No load, steady state, VDD = 3.3 V, VID+ 18 21 No load, steady state, VDD = 2.5 V, VID+ 16 19 No load, steady state, VDD = 1.8 V, VID+ 13 16 V mW CI Input capacitance VI = 0.4 sin(4E6πt) + 0.5 V 4 pF CO Output capacitance VI = 0.4 sin(4E6πt) + 0.5 V 4 pF (1) (2) The algebraic convention, in which the least positive (most negative) limit is designated as a minimum, is used in this data sheet. All typical values are at 25°C . Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: SN65LVDS4 5 SN65LVDS4 SLLSE15A – JULY 2011 – REVISED NOVEMBER 2015 www.ti.com 6.7 Receiver Switching Characteristics: VCC = 2.5 V over recommended operating conditions, VCC = 2.5 V, VID = 150 mV–600 mV, VCM = VID/2 to VCC – VID/2 V, 10 pF load (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX tPLH Propagation delay time, low-to-high-level output 2.5 tPHL Propagation delay time, high-to-low-level output 2.5 tsk(p) Pulse skew (|tpHL – tpLH|) (2) tr Output signal rise time tf Output signal fall time tjit (1) (2) CL = 10 pF, See Figure 19 Residual jitter added ns 3.3 ns 240 ps VDD = 3.3 V 550 VDD = 2.5 V 600 VDD = 3.3 V 550 VDD = 2.5 V 600 Carrier frequency = 122.8 MHz, input signal amplitude = 500 mVpp sine wave, integration bandwidth for rms jitter = 20 khz-20 MHz, VDD = 2.5 V UNIT 3.3 370 ps ps fs All typical values are at 25°C. tsk(p) is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output. 6.8 Receiver Switching Characteristics: VCC = 1.8 V over recommended operating conditions, VCC = 1.8 V, VID = 150 mV–600 mV, VCM = VID/2 to VCC – VID/2 V, 10 pF load (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT tPLH Propagation delay time, low-to-high-level output 3.2 3.8 ns tPHL Propagation delay time, high-to-low-level output 3.2 3.8 ns tsk(p) Pulse skew (|tpHL – tpLH|) (2) 240 ps tr Output signal rise time tf tjit (1) (2) 6 CL = 10 pF, See Figure 19 Output signal fall time Residual jitter added VDD = 3.3 V 550 VDD = 2.5 V 600 VDD = 1.8 V 750 VDD = 3.3 V 550 VDD = 2.5 V 600 VDD = 1.8 V 750 Carrier frequency = 122.8 MHz, input signal amplitude = 500 mVpp sine wave, integration bandwidth for rms jitter = 20 khz-20 MHz, VDD = 1.8 V 370 ps ps fs All typical values are at 25°C. tsk(p) is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output. Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: SN65LVDS4 SN65LVDS4 www.ti.com SLLSE15A – JULY 2011 – REVISED NOVEMBER 2015 6.9 Typical Characteristics 3.5 1.25 3 1 Low-Level Output Voltage (V) High-Level Output Voltage (V) VICM = 1.2 V, VID = 300 mV, CL = 10 pF, input rise time and fall time = 1 ns, input frequency = 250 MHz, 50% duty cycle, TA = 25°C, unless otherwise noted 2.5 2 1.5 1 VCC = 1.8 V, VCC = 1.8 V, VCC = 1.8 V, VCC = 2.5 V, VCC = 2.5 V, 0.5 0 0 1 VDD = 1.8 V VDD = 2.5 V VDD = 3.3 V VDD = 2.5 V VDD = 3.3 V 2 3 4 5 6 High-Level Output Current (mA) 7 VCC = 1.8 V, VCC = 1.8 V, VCC = 1.8 V, VCC = 2.5 V, VCC = 2.5 V, VDD = 1.8 V VDD = 2.5 V VDD = 3.3 V VDD = 2.5 V VDD = 3.3 V 0.75 0.5 0.25 0 −0.25 −0.5 8 0 1 2 3 4 5 6 Low-Level Output Current (mA) 7 8 G001 Figure 1. High-Level Output Voltage vs. High-Level Output Current G002 Figure 2. Low-Level Output Voltage vs. Low-Level Output Current 2.7 VCC = 1.8 V, VCC = 1.8 V, VCC = 1.8 V, VCC = 2.5 V, VCC = 2.5 V, 2.8 2.7 VDD = 1.8 V VDD = 2.5 V VDD = 3.3 V VDD = 2.5 V VDD = 3.3 V VCC = 1.8 V, VCC = 1.8 V, VCC = 1.8 V, VCC = 2.5 V, VCC = 2.5 V, 2.65 Low-to-High Level Propagation Delay Time (dB) High-to-Low Level Propagation Delay Time (ns) 2.9 2.6 2.5 2.4 2.3 2.2 2.1 2 2.6 2.55 VDD = 1.8 V VDD = 2.5 V VDD = 3.3 V VDD = 2.5 V VDD = 3.3 V 2.5 2.45 2.4 2.35 2.3 2.25 2.2 2.15 2.1 2.05 1.9 −40 −20 0 20 40 Free-Air Temperature (°C) 60 2 −40 80 −20 0 20 40 Free-Air Temperature (°C) 60 G003 Figure 3. High- to Low-Level Propagation Delay Time vs. Free-Air Temperature G004 Figure 4. Low- to High-Level Propagation Delay Time vs. Free-Air Temperature 800 800 VCC = 1.8 V, VCC = 1.8 V, VCC = 1.8 V, VCC = 2.5 V, VCC = 2.5 V, 700 VDD = 1.8 V VDD = 2.5 V VDD = 3.3 V VDD = 2.5 V VDD = 3.3 V VDD = 1.8 V VDD = 2.5 V VDD = 3.3 V VDD = 2.5 V VDD = 3.3 V 600 Fall Time (ps) Rise Time (ps) VCC = 1.8 V, VCC = 1.8 V, VCC = 1.8 V, VCC = 2.5 V, VCC = 2.5 V, 700 600 500 400 500 400 300 300 200 200 100 80 5 7 9 11 13 15 17 Capacitive Load (pF) 19 21 22 100 G005 Figure 5. Rise Time vs. Capacitive Load 5 7 9 11 13 15 17 Capacitive Load (pF) 19 21 22 G006 Figure 6. Fall Time vs. Capacitive Load Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: SN65LVDS4 7 SN65LVDS4 SLLSE15A – JULY 2011 – REVISED NOVEMBER 2015 www.ti.com Typical Characteristics (continued) VICM = 1.2 V, VID = 300 mV, CL = 10 pF, input rise time and fall time = 1 ns, input frequency = 250 MHz, 50% duty cycle, TA = 25°C, unless otherwise noted 35 50 30 Supply Current (mA) 25 20 VCC = 1.8 V, VCC = 1.8 V, VCC = 1.8 V, VCC = 2.5 V, VCC = 2.5 V, VCC = 1.8 V, VCC = 1.8 V, VCC = 1.8 V, VCC = 2.5 V, VCC = 2.5 V, VDD = 1.8 V VDD = 2.5 V VDD = 3.3 V VDD = 2.5 V VDD = 3.3 V VDD = 1.8 V VDD = 2.5 V VDD = 3.3 V VDD = 2.5 V VDD = 3.3 V ICC, ICC, ICC, ICC, ICC, IDD, IDD, IDD, IDD, IDD, 45 40 35 Supply Current (mA) ICC, ICC, ICC, ICC, ICC, IDD, IDD, IDD, IDD, IDD, 15 30 VCC = 1.8 V, VCC = 1.8 V, VCC = 1.8 V, VCC = 2.5 V, VCC = 2.5 V, VCC = 1.8 V, VCC = 1.8 V, VCC = 1.8 V, VCC = 2.5 V, VCC = 2.5 V, VDD = 1.8 V VDD = 2.5 V VDD = 3.3 V VDD = 2.5 V VDD = 3.3 V VDD = 1.8 V VDD = 2.5 V VDD = 3.3 V VDD = 2.5 V VDD = 3.3 V 25 20 15 10 10 5 5 0 0 50 100 150 Frequency (MHz) 200 0 −40 250 −20 0 20 40 Free-Air Temperature (°C) 60 80 G007 G008 Figure 7. Supply Current vs. Frequency Figure 8. Supply Current vs. Temperature 180 160 VCC = 1.8 V, VCC = 1.8 V, VCC = 1.8 V, VCC = 2.5 V, VCC = 2.5 V, 140 120 VDD = 1.8 V VDD = 2.5 V VDD = 3.3 V VDD = 2.5 V VDD = 3.3 V 140 Pulse Skew (ps) Pulse Skew (ps) VDD = 1.8 V VDD = 2.5 V VDD = 3.3 V VDD = 2.5 V VDD = 3.3 V 120 100 80 60 40 20 100 80 60 40 20 0 0 −20 −20 −40 −40 VCC = 1.8 V, VCC = 1.8 V, VCC = 1.8 V, VCC = 2.5 V, VCC = 2.5 V, 160 −20 0 20 40 Free-Air Temperature (°C) 60 −40 0.15 80 0.45 0.75 1.05 1.35 Common-Mode Input Voltage (V) 1.65 G009 Figure 9. Pulse Skew vs. Temperature G010 Figure 10. Pulse Skew vs. Common-Mode Voltage 3.1 160 120 VDD = 1.8 V VDD = 2.5 V VDD = 3.3 V VDD = 2.5 V VDD = 3.3 V Low-to-High Level Propagation Delay Time (ns) VCC = 1.8 V, VCC = 1.8 V, VCC = 1.8 V, VCC = 2.5 V, VCC = 2.5 V, 140 Pulse Skew (ns) 100 80 60 40 20 0 −20 −40 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Differential Input Voltage (V) 0.55 0.6 2.9 8 VDD = 1.8 V VDD = 2.5 V VDD = 3.3 V VDD = 2.5 V VDD = 3.3 V 2.7 2.5 2.3 2.1 1.9 0.15 G011 Figure 11. Pulse Skew vs. Differential Input Voltage VCC = 1.8 V, VCC = 1.8 V, VCC = 1.8 V, VCC = 2.5 V, VCC = 2.5 V, 0.45 0.75 1.05 1.35 Common-Mode Input Voltage (V) 1.65 G012 Figure 12. Propagation Delay, Low-to-High vs. CommonMode Voltage Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: SN65LVDS4 SN65LVDS4 www.ti.com SLLSE15A – JULY 2011 – REVISED NOVEMBER 2015 Typical Characteristics (continued) VICM = 1.2 V, VID = 300 mV, CL = 10 pF, input rise time and fall time = 1 ns, input frequency = 250 MHz, 50% duty cycle, TA = 25°C, unless otherwise noted 3.3 VCC = 1.8 V, VCC = 1.8 V, VCC = 1.8 V, VCC = 2.5 V, VCC = 2.5 V, 2.6 2.5 VDD = 1.8 V VDD = 2.5 V VDD = 3.3 V VDD = 2.5 V VDD = 3.3 V High-to-Low Level Propagation Delay Time (ns) Low-to-High Level Propagation Delay Time (ns) 2.7 2.4 2.3 2.2 2.1 2 1.9 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Differential Input Voltage (V) 0.55 VCC = 1.8 V, VCC = 1.8 V, VCC = 1.8 V, VCC = 2.5 V, VCC = 2.5 V, 3.1 2.9 2.7 2.5 2.3 2.1 1.9 0.15 0.6 VDD = 1.8 V VDD = 2.5 V VDD = 3.3 V VDD = 2.5 V VDD = 3.3 V 0.45 0.75 1.05 1.35 Common-Mode Input Voltage (V) G013 Figure 13. Propagation Delay, Low-to-High vs. Differential Input Voltage G014 Figure 14. Propagation Delay, High-to-Low vs. CommonMode Voltage 90 VCC = 1.8 V, VCC = 1.8 V, VCC = 1.8 V, VCC = 2.5 V, VCC = 2.5 V, 2.7 2.6 VDD = 1.8 V VDD = 2.5 V VDD = 3.3 V VDD = 2.5 V VDD = 3.3 V VCC = 1.8 V, VDD = 2.5 V VCC = 2.5 V, VDD = 3.3 V 80 70 2.5 60 Power (mW) High-to-Low Level Propagation Delay Time (ns) 2.8 2.4 2.3 50 40 2.2 30 2.1 20 2 10 1.9 0.15 1.65 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Differential Input Voltage (V) 0.55 0.6 0 0 50 100 150 Frequency (MHz) 200 G015 Figure 15. Propagation Delay, High-to-Low vs. Differential Input Voltage 250 G016 Figure 16. Power vs. Frequency Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: SN65LVDS4 9 SN65LVDS4 SLLSE15A – JULY 2011 – REVISED NOVEMBER 2015 www.ti.com 7 Parameter Measurement Information IIA A V IA IO + VIB VID 2 R IIB VIA B VIC VO VIB Figure 17. Receiver Voltage and Current Definitions 1000 Ω 100 Ω 1000 Ω VIC + -- 100 Ω † VID 10 pF, 2 Places VO 10 pF † Remove for testing LVDT device. NOTE: Input signal of 3 Mpps, duration of 167 ns, and transition time of 2 H T @ · ln ¨ ¨ >0.8 W T @ ¸¸ © ¹ Edge-Coupled S S H H Differential Microstrip Zdiff § 2 u Z0 u ¨ 1 0.48 u e ¨ © Differential Stripline 0.96 u s H · ¸ ¸ ¹ Zdiff Co-Planar Coupled Microstrips W G 2.9 u s H · ¸ ¸ ¹ Broad-Side Coupled Striplines W S § 2 u Z0 u ¨ 1 0.347e ¨ © W G S H H Figure 25. Controlled-Impedance Transmission Lines Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: SN65LVDS4 17 SN65LVDS4 SLLSE15A – JULY 2011 – REVISED NOVEMBER 2015 www.ti.com 9.2.2.5 Termination Resistor An LVDS communication channel employs a current source driving a transmission line which is terminated with a resistive load. This load serves to convert the transmitted current into a voltage at the receiver input. To ensure incident wave switching (which is necessary to operate the channel at the highest signaling rate), the termination resistance should be matched to the characteristic impedance of the transmission line. The designer should ensure that the termination resistance is within 10% of the nominal media characteristic impedance. If the transmission line is targeted for 100-Ω impedance, the termination resistance should be between 90 and 110 Ω. The line termination resistance should be located as close as possible to the receiver, thereby minimizing the stub length from the resistor to the receiver. The limiting case would be to incorporate the termination resistor into the receiver. While we talk in this section about point-to-point communications, a word of caution is useful when a multidrop topology is used. In such topologies, line termination resistors are to be located only at the end(s) of the transmission line. 9.2.3 Application Curves Figure 26. SN65LVDS4 Operating at 500 Mbps 18 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: SN65LVDS4 SN65LVDS4 www.ti.com SLLSE15A – JULY 2011 – REVISED NOVEMBER 2015 10 Power Supply Recommendations There are two power supplies in SN65LVDS4, VCC which is the core power supply and VDD which is the output drive power supply. For proper device operation it is recommended that VCC should be powered up first and then VDD or VCC applied at the same time as VDD (VCC and VDD tied together). It is also recommended that VCC should be equal to or less than VDD as shown in Table 3. Table 3. Power Supply Acceptable Combinations VCC (V) VDD (V) Recommended 1.8 1.8 yes 1.8 2.5 yes 1.8 3.3 yes 2.5 1.8 no 2.5 2.5 yes 2.5 3.3 yes Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: SN65LVDS4 19 SN65LVDS4 SLLSE15A – JULY 2011 – REVISED NOVEMBER 2015 www.ti.com 11 Layout 11.1 Layout Guidelines 11.1.1 Microstrip vs. Stripline Topologies As per SLLD009, printed-circuit boards usually offer designers two transmission line options: Microstrip and stripline. Microstrips are traces on the outer layer of a PCB, as shown in Figure 27. Figure 27. Microstrip Topology On the other hand, striplines are traces between two ground planes. Striplines are less prone to emissions and susceptibility problems because the reference planes effectively shield the embedded traces. However, from the standpoint of high-speed transmission, juxtaposing two planes creates additional capacitance. TI recommends routing LVDS signals on microstrip transmission lines, if possible. The PCB traces allow designers to specify the necessary tolerances for ZO based on the overall noise budget and reflection allowances. Footnotes 1 (1), 2 (2), and 3 (3) provide formulas for ZO and tPD for differential and single-ended traces. (1) (2) (3) Figure 28. Stripline Topology 11.1.2 Dielectric Type and Board Construction The speeds at which signals travel across the board dictates the choice of dielectric. FR-4, or equivalent, usually provides adequate performance for use with LVDS signals. If rise or fall times of TTL/CMOS signals are less than 500 ps, empirical results indicate that a material with a dielectric constant near 3.4, such as Rogers™ 4350 or Nelco N4000-13 is better suited. Once the designer chooses the dielectric, there are several parameters pertaining to the board construction that can affect performance. The following set of guidelines were developed experimentally through several designs involving LVDS devices: • Copper weight: 15 g or 1/2 oz start, plated to 30 g or 1 oz • All exposed circuitry should be solder-plated (60/40) to 7.62 μm or 0.0003 in (minimum). • Copper plating should be 25.4 μm or 0.001 in (minimum) in plated-through-holes. • Solder mask over bare copper with solder hot-air leveling 11.1.3 Recommended Stack Layout Following the choice of dielectrics and design specifications, you must decide how many levels to use in the stack. To reduce the TTL/CMOS to LVDS crosstalk, it is a good practice to have at least two separate signal planes as shown in Figure 29. (1) (2) (3) 20 Howard Johnson & Martin Graham.1993. High Speed Digital Design – A Handbook of Black Magic. Prentice Hall PRT. ISBN number 013395724. Mark I. Montrose. 1996. Printed Circuit Board Design Techniques for EMC Compliance. IEEE Press. ISBN number 0780311310. Clyde F. Coombs, Jr. Ed, Printed Circuits Handbook, McGraw Hill, ISBN number 0070127549. Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: SN65LVDS4 SN65LVDS4 www.ti.com SLLSE15A – JULY 2011 – REVISED NOVEMBER 2015 Layout Guidelines (continued) Layer 1: Routed Plane (LVDS Signals) Layer 2: Ground Plane Layer 3: Power Plane Layer 4: Routed Plane (TTL/CMOS Signals) Figure 29. Four-Layer PCB Board NOTE The separation between layers 2 and 3 should be 127 μm (0.005 in). By keeping the power and ground planes tightly coupled, the increased capacitance acts as a bypass for transients. One of the most common stack configurations is the six-layer board, as shown in Figure 30. Layer 1: Routed Plane (LVDS Signals) Layer 2: Ground Plane Layer 3: Power Plane Layer 4: Ground Plane Layer 5: Ground Plane Layer 4: Routed Plane (TTL Signals) Figure 30. Six-Layer PCB Board In this particular configuration, it is possible to isolate each signal layer from the power plane by at least one ground plane. The result is improved signal integrity; however, fabrication is more expensive. Using the 6-layer board is preferable, because it offers the layout designer more flexibility in varying the distance between signal layers and referenced planes, in addition to ensuring reference to a ground plane for signal layers 1 and 6. 11.1.4 Separation Between Traces The separation between traces depends on several factors; however, the amount of coupling that can be tolerated usually dictates the actual separation. Low noise coupling requires close coupling between the differential pair of an LVDS link to benefit from the electromagnetic field cancellation. The traces should be 100-Ω differential and thus coupled in the manner that best fits this requirement. In addition, differential pairs should have the same electrical length to ensure that they are balanced, thus minimizing problems with skew and signal reflection. In the case of two adjacent single-ended traces, one should use the 3-W rule, which stipulates that the distance between two traces must be greater than two times the width of a single trace, or three times its width measured from trace center to trace center. This increased separation effectively reduces the potential for crosstalk. The same rule should be applied to the separation between adjacent LVDS differential pairs, whether the traces are edge-coupled or broad-side-coupled. W Differential Traces LVDS Pair S= Minimum spacing as defined by PCB vendor W t2W Single-Ended Traces TTL/CMOS Trace W Figure 31. 3-W Rule for Single-Ended and Differential Traces (Top View) You should exercise caution when using autorouters, because they do not always account for all factors affecting crosstalk and signal reflection. For instance, it is best to avoid sharp 90° turns to prevent discontinuities in the signal path. Using successive 45° turns tends to minimize reflections. Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: SN65LVDS4 21 SN65LVDS4 SLLSE15A – JULY 2011 – REVISED NOVEMBER 2015 www.ti.com Layout Guidelines (continued) 11.1.5 Crosstalk and Ground Bounce Minimization To reduce crosstalk, it is important to provide a return path to high-frequency currents that is as close as possible to its originating trace. A ground plane usually achieves this. Because the returning currents always choose the path of lowest inductance, they are most likely to return directly under the original trace, thus minimizing crosstalk. Lowering the area of the current loop lowers the potential for crosstalk. Traces kept as short as possible with an uninterrupted ground plane running beneath them emit the minimum amount of electromagnetic field strength. Discontinuities in the ground plane increase the return path inductance and should be avoided. 11.1.6 Decoupling Each power or ground lead of a high-speed device should be connected to the PCB through a low inductance path. For best results, one or more vias are used to connect a power or ground pin to the nearby plane. Ideally, via placement is immediately adjacent to the pin to avoid adding trace inductance. Placing a power plane closer to the top of the board reduces the effective via length and its associated inductance. VCC Via GND Via 4 mil 6 mil TOP signal layer + GND fill VDD 1 plane Buried capacitor GND plane Signal layer > Board thickness approximately 100 mil 2 mil GND plane Signal layers VCC plane 4 mil 6 mil Signal layer GND plane Buried capacitor VDD 2 plane BOTTOM signal layer + GND fill > Typical 12-Layer PCB Figure 32. Low Inductance, High-Capacitance Power Connection Bypass capacitors should be placed close to VDD pins. They can be placed conveniently near the underneath the package to minimize the loop area. This extends the useful frequency range of capacitance. Small-physical-size capacitors, such as 0402 or even 0201, or X7R surface-mount should be used to minimize body inductance of capacitors. Each bypass capacitor is connected to the ground plane through vias tangent to the pads of the capacitor as shown in Figure 33(a). corners or the added capacitors power and An X7R surface-mount capacitor of size 0402 has about 0.5 nH of body inductance. At frequencies above 30 MHz or so, X7R capacitors behave as low-impedance inductors. To extend the operating frequency range to a few hundred MHz, an array of different capacitor values like 100 pF, 1 nF, 0.03 μF, and 0.1 μF are commonly used in parallel. The most effective bypass capacitor can be built using sandwiched layers of power and ground at a separation of 2 to 3 mils. With a 2-mil FR4 dielectric, there is approximately 500 pF per square inch of PCB. Refer back to Figure 5-1 for some examples. Many high-speed devices provide a low-inductance GND connection on the backside of the package. This center pad must be connected to a ground plane through an array of vias. The via array reduces the effective inductance to ground and enhances the thermal performance of the small Surface Mount Technology (SMT) package. Placing vias around the perimeter of the pad connection ensures proper heat spreading and the lowest possible die temperature. Placing high-performance devices on opposing sides of the PCB using two GND planes (as shown in Figure 25) creates multiple paths for heat transfer. Often thermal PCB issues are the result of one device adding heat to another, resulting in a very high local temperature. Multiple paths for heat transfer minimize this possibility. In many cases the GND pad that is so important for heat dissipation makes the optimal decoupling layout impossible to achieve due to insufficient padto-pad spacing as shown in Figure 33(b). When this occurs, placing the decoupling capacitor on the backside of the board keeps the extra inductance to a minimum. It is important to place the VDD via as close to the device pin as possible while still allowing for sufficient solder mask coverage. If the via is left open, solder may flow from the pad and into the via barrel. This will result in a poor solder connection. 22 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: SN65LVDS4 SN65LVDS4 www.ti.com SLLSE15A – JULY 2011 – REVISED NOVEMBER 2015 Layout Guidelines (continued) VDD IN± 0402 IN+ 0402 (a) (b) Figure 33. Typical Decoupling Capacitor Layouts 11.2 Layout Example At least two or three times the width of an individual trace should separate single-ended traces and differential pairs to minimize the potential for crosstalk. Single-ended traces that run in parallel for less than the wavelength of the rise or fall times usually have negligible crosstalk. Increase the spacing between signal paths for long parallel runs to reduce crosstalk. Boards with limited real estate can benefit from the staggered trace layout, as shown in Figure 34. Layer 1 Layer 6 Figure 34. Staggered Trace Layout This configuration lays out alternating signal traces on different layers; thus, the horizontal separation between traces can be less than 2 or 3 times the width of individual traces. To ensure continuity in the ground signal path, TI recommends having an adjacent ground via for every signal via, as shown in Figure 35. Note that vias create additional capacitance. For example, a typical via has a lumped capacitance effect of 1/2 pF to 1 pF in FR4. Signal Via Signal Trace Uninterrupted Ground Plane Signal Trace Uninterrupted Ground Plane Ground Via Figure 35. Ground Via Location (Side View) Short and low-impedance connection of the device ground pins to the PCB ground plane reduces ground bounce. Holes and cutouts in the ground planes can adversely affect current return paths if they create discontinuities that increase returning current loop areas. To minimize EMI problems, TI recommends avoiding discontinuities below a trace (for example, holes, slits, and so on) and keeping traces as short as possible. Zoning the board wisely by placing all similar functions in the same area, as opposed to mixing them together, helps reduce susceptibility issues. Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: SN65LVDS4 23 SN65LVDS4 SLLSE15A – JULY 2011 – REVISED NOVEMBER 2015 www.ti.com 12 Device and Documentation Support 12.1 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.2 Trademarks E2E is a trademark of Texas Instruments. Rogers is a trademark of Rogers Corporation. All other trademarks are the property of their respective owners. 12.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 24 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: SN65LVDS4 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN65LVDS4RSER ACTIVE UQFN RSE 10 3000 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 85 QXB SN65LVDS4RSET ACTIVE UQFN RSE 10 250 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 85 QXB (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of