SN75LVDS84A, SN65LVDS84AQ
FLATLINK TRANSMITTER
SLLS354E – MAY 1999 – REVISED JANUARY 2001
D
D
D
D
D
D
D
D
D
D
D
D
D
21:3 Data Channel Compression at up to
196 Million Bytes per Second Throughput
Suited for SVGA, XGA, or SXGA Data
Transmission From Controller to Display
With Very Low EMI
21 Data Channels Plus Clock In
Low-Voltage TTL Inputs and 3 Data
Channels Plus Clock Out Low-Voltage
Differential Signaling (LVDS) Outputs
Operates From a Single 3.3-V Supply and
89 mW (Typ)
Ultralow-Power 3.3-V CMOS Version of the
SN75LVDS84. Power Consumption About
One Third of the ’LVDS84
Packaged in Thin Shrink Small-Outline
Package (TSSOP) With 20 Mil Terminal
Pitch
Consumes Less Than 0.54 mW When
Disabled
Wide Phase-Lock Input Frequency Range:
31 MHz to 75 MHz
No External Components Required for PLL
Outputs Meet or Exceed the Requirements
of ANSI EIA/TIA-644 Standard
SSC Tracking Capability of 3% Center
Spread at 50-kHz Modulation Frequency
Improved Replacement for SN75LVDS84
and NSC’s DS90CF363A 3-V Device
Available in Q-Temp Automotive
High Reliability Automotive Applications
Configuration Control / Print Support
Qualification to Automotive Standards
DGG PACKAGE
(TOP VIEW)
D4
VCC
D5
D6
GND
D7
D8
VCC
D9
D10
GND
D11
D12
NC
D13
D14
GND
D15
D16
D17
VCC
D18
D19
GND
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
D3
D2
GND
D1
D0
NC
LVDSGND
Y0M
Y0P
Y1M
Y1P
LVDSVCC
LVDSGND
Y2M
Y2P
CLKOUTM
CLKOUTP
LVDSGND
PLLGND
PLLVCC
PLLGND
SHTDN
CLKIN
D20
NC – Not Connected
description
The SN75LVDS84A and SN65LVDS84AQ FlatLink transmitters contains three 7-bit parallel-load serial-out shift
registers, and four low-voltage differential signaling (LVDS) line drivers in a single integrated circuit. These
functions allow 21 bits of single-ended LVTTL data to be synchronously transmitted over 3 balanced-pair
conductors for receipt by a compatible receiver, such as the SN75LVDS82 or SN75LVDS86/86A.
When transmitting, data bits D0 – D20 are each loaded into registers of the ’LVDS84A upon the falling edge.
The internal PLL is frequency-locked to CLKIN and then used to unload the data registers in 7-bit slices. The
three serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency
of CLKOUT is the same as the input clock, CLKIN.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FlatLink is a trademark of Texas Instruments.
Copyright 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN75LVDS84A, SN65LVDS84AQ
FLATLINK TRANSMITTER
SLLS354E – MAY 1999 – REVISED JANUARY 2001
description (continued)
The ’LVDS84A requires no external components and little or no control. The data bus appears the same at the
input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only
user intervention is the possible use of the shutdown/clear (SHTDN) active-low input to inhibit the clock and shut
off the LVDS output drivers for lower power consumption. A low-level on this signal clears all internal registers
to a low level.
The SN75LVDS84A is characterized for operation over ambient free-air temperatures of 0°C to 70°C. The
SN65LVDS84AQ is characterized for operation over the full Automotive temperature range of – 40°C to 125°C.
functional block diagram
7
D0 – D6
Parallel-Load 7-Bit
Shift Register
A,B, ...G
SHIFT/LOAD
Y0P
Y0M
CLK
7
Parallel-Load 7-Bit
Shift Register
Y1P
A,B, ...G
D7 – D13
SHIFT/LOAD
Y1M
CLK
7
D14 – D20
Parallel-Load 7-Bit
Shift Register
Y2P
A,B, ...G
SHIFT/LOAD
Y2M
CLK
Control Logic
SHTDN
PLL
CLKOUTP
CLKIN
CLKOUTM
CLK
CLKINH
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN75LVDS84A, SN65LVDS84AQ
FLATLINK TRANSMITTER
SLLS354E – MAY 1999 – REVISED JANUARY 2001
schematics of input and output
EQUIVALENT OF EACH INPUT
EQUIVALENT OF EACH OUTPUT
VCC
VCC
7V
180 Ω
D or
SHTDN
YnP or YnM
5V
7V
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V
Input and output voltage ranges, VI, VO (all terminals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 150°C
Electrostatic discharge: ESD machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 V
ESD human-body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6000 V
ESD charged-device model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500 V
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to the GND terminals.
PACKAGE
TA ≤ 25°C
POWER RATING
DISSIPATION RATING TABLE
DERATING FACTOR‡
TA = 70°C
POWER RATING
ABOVE TA = 25°C
TA = 125°C
POWER RATING
DGG
1637 mW
13.1 mW/°C
1048 mW
327 mW
‡ This is the inverse of the junction-to-ambient thermal resistance when board mounted and with no air flow.
recommended operating conditions
MIN
NOM
Supply voltage, VCC
3
3.3
High-level input voltage, VIH
2
Low-level input voltage, VIL
Differential load impedance, ZL
SN75LVDS84A
Operating free-air
free air temperature,
temperature TA
SN65LVDS84AQ
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MAX
UNIT
3.6
V
V
0.8
V
90
132
Ω
0
70
–40
125
°C
3
SN75LVDS84A, SN65LVDS84AQ
FLATLINK TRANSMITTER
SLLS354E – MAY 1999 – REVISED JANUARY 2001
timing requirements
tc
tw
Input clock period
tt
tsu
Transition time, input signal
th
Hold time, data, D0 – D20 valid after CLKIN↓ (see Figure 2)
Pulse duration, high-level input clock
MIN
NOM
MAX
UNIT
13.3
tc
32.4
ns
0.6 tc
ns
5
ns
0.4 tc
Setup time, data, D0 – D20 valid before CLKIN↓ (see Figure 2)
3
ns
1.5
ns
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT
Input threshold voltage
|VOD|
Differential steady-state output voltage
magnitude
∆|VOD|
Change in the steady-state differential output
voltage magnitude between opposite binary
states
RL = 100 Ω,
IIH
High level input current
High-level
VIH = VCC
IIL
Low-level input current
VIL = 0
VO(Yn) = 0
Peak-to-peak common-mode output voltage
IOZ
High-impedance output current
ICC(AVG)
See Figure 3
RL = 100 Ω, See Figure 3
Steady-state common-mode output voltage
Short circuit output current
Short-circuit
MAX
1.125
UNIT
V
454
mV
50
mV
1.375
150
SN75LVDS84A
20
SN65LVDS84AQ
25
V
mV
µA
±10
µA
–6
±24
mA
–6
±12
mA
±10
µA
Disabled,,
All inputs at GND
SN75LVDS84A
15
150
SN65LVDS84AQ
15
170
Enabled,
RL = 100 Ω (4
( places))
Gray-scale pattern
(see Figure 4)
f = 65 MHz
27
35
f = 75 MHz
30
38
Enabled,
RL = 100 Ω,, (4
( places))
Worst-case pattern
(see Figure 5)
f = 65 MHz
28
36
f = 75 MHz
31
39
VOD = 0
VO = 0 to VCC
Quiescent supply current (average)
247
80
POST OFFICE BOX 655303
µA
mA
CI
Input capacitance
† All typical values are at VCC = 3.3 V, TA = 25°C.
4
TYP†
1.4
VOC(SS)
VOC(PP)
IOS
MIN
2
• DALLAS, TEXAS 75265
pF
SN75LVDS84A, SN65LVDS84AQ
FLATLINK TRANSMITTER
SLLS354E – MAY 1999 – REVISED JANUARY 2001
switching characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP†
MAX
td0
Delay time, CLKOUT↑ to serial bit
position 0
td1
Delay time, CLKOUT↑ to serial bit
position 1
1t
7 c
* 0.2
1t
7 c
) 0.2
td2
Delay time, CLKOUT↑ to serial bit
position 2
2t
7 c
* 0.2
2t
7 c
) 0.2
td3
Delay time, CLKOUT↑ to serial bit
position 3
3t
7 c
) 0.2
td4
Delay time, CLKOUT↑ to serial bit
position 4
* 0.2
4 t * 0.2
7 c
td5
Delay time, CLKOUT↑ to serial bit
position 5
5t
7 c
td6
Delay time, CLKOUT↑ to serial bit
position 6
tsk(o)
Output skew, t n
td7
– 0.2
tc = 15.38 ns (± 0.2%),
|Input clock jitter| < 50 ps‡, See Figure 6
0.2
3t
7 c
) 0.2
5 t ) 0.2
7 c
6t
7 c
– 0.2
tc = 15.38 ns (± 0.2%),
|Input clock jitter| < 50 ps‡, See Figure 6
time CLKIN↓ to CLKOUT↑
Delay time,
tc = 13.33 ns ~ 32.25 ns (± 0.2%),
|Input clock jitter| < 50 ps‡, See Figure 6
∆ tc(o)
C cle time,
time output
o tp t clock jitter§
( ) Cycle
ns
4t
7 c
* 0.2
6 t * 0.2
7 c
* n7 tc
UNIT
) 0.2
0.2
ns
2.7
ns
1
4.5
tc = 15.38 + 0.308 sin (2π500E3t) ± 0.05 ns,
See Figure 7
± 62
tc = 15.38 + 0.308 sin (2π3E6t) ± 0.05 ns,
See Figure 7
± 121
ps
4t
7 c
tw
Pulse duration, high-level output clock
ns
tt
Transition time, differential output voltage
(tr or tf)
See Figure 3
700
ten
Enable time, SHTDN↑ to phase lock (Yn
valid)
See Figure 8
1
ms
tdis
Disable time, SHTDN↓ to off state
(CLKOUT low)
See Figure 9
6.5
ns
1500
ps
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ |Input clock jitter| is the magnitude of the change in the input clock period.
§ Output clock jitter is the change in the output clock period from one cycle to the next cycle observed over 15 000 cycles.
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5
SN75LVDS84A, SN65LVDS84AQ
FLATLINK TRANSMITTER
SLLS354E – MAY 1999 – REVISED JANUARY 2001
D0
CLKIN
ÏÏÏ
ÏÏÏ
ÏÏÏ
PARAMETER MEASUREMENT INFORMATION
ÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏ
ÏÏ
ÏÏ
CLKOUT
ÎÎÎ
ÎÎÎ
ÏÏ
ÏÏ
Previous Cycle
ÎÎ
ÎÎ
Current Cycle
Y0
D0–1
D6
D5
D4
D3
D2
D1
D0
D6+1
Y1
D7–1
D13
D12
D11
D10
D9
D8
D7
D13+1
Y2
D14–1
D20
D19
D18
D17
D16
D15
D14
D20+1
Figure 1. Typical Load and Shift Sequences
Dn
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
tsu
th
ÏÏÏÏ
ÏÏÏÏ
CLKIN
NOTE A: All input timing is defined at 1.4 V on an input signal with a 10%-to-90% rise or fall time of less than 5 ns.
Figure 2. Setup and Hold Time Definition
6
Next
Cycle
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN75LVDS84A, SN65LVDS84AQ
FLATLINK TRANSMITTER
SLLS354E – MAY 1999 – REVISED JANUARY 2001
49.9 Ω ± 1% (2 Places)
YP
VOD
VOC
YM
CL = 10 pF Max
(2 Places)
NOTE A: The lumped instrumentation capacitance for any single-ended voltage measurement is less than or equal to 10 pF. When making
measurements at YP or YM, the complementary output is similarly loaded.
(a) SCHEMATIC
100%
80%
VOD(H)
0V
VOD(L)
20%
0%
tf
tr
VOC(PP)
VOC(SS)
VOC(SS)
0V
(b) WAVEFORMS
Figure 3. Test Load and Voltage Definitions for LVDS Outputs
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7
SN75LVDS84A, SN65LVDS84AQ
FLATLINK TRANSMITTER
SLLS354E – MAY 1999 – REVISED JANUARY 2001
PARAMETER MEASUREMENT INFORMATION
CLKIN
D0, 6, 12
D1, 7, 13
D2, 8, 14
D3, 9, 15
D18, 19, 20
All others
NOTES: A. The 16-grayscale test-pattern test device power consumption for a typical display pattern.
B. VIH = 2 V and VIL = 0.8 V
Figure 4. 16-Grayscale Test-Pattern Waveforms
tc
CLKIN
Even Dn
Odd Dn
NOTES: A. The worst-case test pattern produces nearly the maximum switching frequency for all of the LVDS outputs.
B. VIH = 2 V and VIL = 0.8 V
Figure 5. Worst-Case Test-Pattern Waveforms
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN75LVDS84A, SN65LVDS84AQ
FLATLINK TRANSMITTER
SLLS354E – MAY 1999 – REVISED JANUARY 2001
PARAMETER MEASUREMENT INFORMATION
td7
CLKIN
ÏÏ
ÏÏ
ÏÏ ÏÏ
ÏÏ ÏÏ
CLKOUT
ÎÎ
ÏÏÏ
ÎÎ
ÏÏÏ
ÏÏ ÏÏ ÏÏ ÏÏ ÏÏ ÏÏ
ÏÏ ÏÏ ÏÏ ÏÏ ÏÏ ÏÏ
td0
Yn
td1
td2
td3
td4
td5
td6
VOD(H)
CLKIN
CLKOUT
or
Yn
1.4 V
0V
VOD(L)
td7
td0 – td6
Figure 6. Timing Definitions
+
Reference
∑
Device
Under
Test
VCO
+
Modulation
V(t) = A sin (2 π f(mod) t)
HP8665A
Synthesized
Signal Generator
0.1 MHz – 4200 MHz
HP8133A
Pulse Generator
OUTPUT
RF Output
Device Under Test
CLKIN
CLKOUT
Tek TDS794D
Digital Scope
Input
Ext. Input
Figure 7. Clock Jitter Test Setup
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9
SN75LVDS84A, SN65LVDS84AQ
FLATLINK TRANSMITTER
SLLS354E – MAY 1999 – REVISED JANUARY 2001
TYPICAL CHARACTERISTICS
CLKIN
Dn
ten
SHTDN
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
Invalid
Yn
Valid
Figure 8. Enable Time Waveforms
CLKIN
tdis
SHTDN
CLKOUT
Figure 9. Disable Time Waveforms
PEAK-TO-PEAK OUTPUT JITTER (NORMALIZED)
vs
MODULATION FREQUENCY
AVERAGE SUPPLY CURRENT
vs
CLOCK FREQUENCY
10
Peak-To-Peak OutpuT Jitter (Normalized)
I CC – Average Supply Current – mA
31
29
VCC = 3.6 V
27
25
VCC = 3.3 V
23
VCC = 3 V
21
19
17
15
30
0.1
0.1
35
40
45
50
55
60
65
70
75
fc – Clock Frequency – MHz
Figure 10. Grayscale Input Pattern
10
1
POST OFFICE BOX 655303
1
f(mod) – Modulation Frequency – MHz
Figure 11. Output Period Jitter vs Modulation
Frequency
• DALLAS, TEXAS 75265
10
SN75LVDS84A, SN65LVDS84AQ
FLATLINK TRANSMITTER
SLLS354E – MAY 1999 – REVISED JANUARY 2001
APPLICATION INFORMATION
Host
Graphics Controller
12-BIT
RED0
RED1
RED2
RED3
NA
NA
GREEN0
GREEN1
GREEN2
GREEN3
NA
NA
BLUE0
BLUE1
BLUE2
BLUE3
NA
NA
H_SYNC
V_SYNC
ENABLE
CLOCK
18-BIT
RED0
RED1
RED2
RED3
RED4
RED5
GREEN0
GREEN1
GREEN2
GREEN3
GREEN4
GREEN5
BLUE0
BLUE1
BLUE2
BLUE3
BLUE4
BLUE5
H_SYNC
V_SYNC
ENABLE
CLOCK
44
45
47
48
1
3
4
6
7
9
10
12
13
15
16
18
19
20
22
23
25
26
SN75LVDS84A/
SN65LVDS84AQ
D0
Y0M
D1
D2
D3
Y0P
D4
D5
D6
Y1M
D7
D8
D9
Y1P
D10
D11
D12
Y2M
D13
D14
D15
Y2P
D16
D17
D18
CLKOUTM
D19
D20
CLKIN
CLKOUTP
Cable
Flat Panel Display
SN75LVDS86/86A
41
8
A0M
100 Ω
40
9
39
10
A0P
A1M
100 Ω
38
11
35
14
A1P
A2M
100 Ω
34
15
33
16
A2P
CLKINM
100 Ω
32
17
CLKINP
NOTES: A. The five 100-Ω terminating resistors are recommended to be 0603 types.
B. NA – not applicable, these unused inputs should be left open.
Figure 12. Color Host to LCD Panel Application
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• DALLAS, TEXAS 75265
11
SN75LVDS84A, SN65LVDS84AQ
FLATLINK TRANSMITTER
SLLS354E – MAY 1999 – REVISED JANUARY 2001
APPLICATION INFORMATION
Host
Graphics Controller
12-BIT
RED0
RED1
RED2
RED3
NA
NA
GREEN0
GREEN1
GREEN2
GREEN3
NA
NA
BLUE0
BLUE1
BLUE2
BLUE3
NA
NA
H_SYNC
V_SYNC
ENABLE
CLOCK
18-BIT
RED0
RED1
RED2
RED3
RED4
RED5
GREEN0
GREEN1
GREEN2
GREEN3
GREEN4
GREEN5
BLUE0
BLUE1
BLUE2
BLUE3
BLUE4
BLUE5
H_SYNC
V_SYNC
ENABLE
CLOCK
44
45
47
48
1
3
4
6
7
9
10
12
13
15
16
18
19
20
22
23
25
26
SN75LVDS84A/
SN65LVDS84AQ
D0
Y0M
D1
D2
D3
Y0P
D4
D5
D6
Y1M
D7
D8
D9
Y1P
D10
D11
D12
Y2M
D13
D14
D15
Y2P
D16
D17
D18
CLKOUTM
D19
D20
CLKIN
CLKOUTP
Cable
Flat Panel Display
SN75LVDS82
41
9
A0M
100 Ω
40
10
39
11
A0P
A1M
100 Ω
38
12
35
15
A1P
A2M
100 Ω
34
16
33
A2P
CLKINM
100 Ω
32
CLKINP
A3M
100 Ω
A3P
NOTES: A. The four 100-Ω terminating resistors are recommended to be 0603 types.
B. NA – not applicable, these unused inputs should be left open.
Figure 13. 18-Bit Color Host to 24-Bit LCD Display Panel Application
12
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PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
Samples
(4/5)
(6)
SN65LVDS84AQDGG
ACTIVE
TSSOP
DGG
48
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
65LVDS84AQ
Samples
SN65LVDS84AQDGGR
ACTIVE
TSSOP
DGG
48
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
65LVDS84AQ
Samples
SN75LVDS84ADGG
ACTIVE
TSSOP
DGG
48
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
SN75LVDS84A
Samples
SN75LVDS84ADGGR
ACTIVE
TSSOP
DGG
48
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
SN75LVDS84A
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of