SN65LVDS93
www.ti.com ................................................................................................................................................................. SLLS302G – MAY 1998 – REVISED MAY 2009
LVDS SERDES TRANSMITTER
FEATURES
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28:4 Data Channel Compression at up to
1.904 Gigabits per Second Throughput
Suited for Point-to-Point Subsystem
Communication With Very Low EMI
28 Data Channels Plus Clock in Low-Voltage
TTL and 4 Data Channels Plus Clock Out
Low-Voltage Differential
Selectable Rising or Falling Clock Edge
Triggered Inputs
Bus Pins Tolerate 6-kV HBM ESD
Operates From a Single 3.3-V Supply and
250 mW (Typ)
5-V Tolerant Data Inputs
Packaged in Thin Shrink Small-Outline
Package With 20 Mil Terminal Pitch
Consumes
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