SN65LVDS95DGGR

SN65LVDS95 SLLS297J – MAY 1998 – REVISED MAY 2011 www.ti.com LVDS SERDES TRANSMITTER Check for Samples: SN65LVDS95 FEATURES 1 • • • • • • • • • • • • • • 3:21 Data Channel Compression at up to 1.428 Gigabits/s Throughput Suited for Point-to-Point Subsystem Communication With Very Low EMI 21 Data Channels Plus Clock in Low-Voltage TTL and 3 Data Channels Plus Clock Out Low-Voltage Differential Operates From a Single 3.3-V Supply and 250 mW (Typ) 5-V Tolerant Data Inputs 'LVDS95 Has Rising Clock Edge Triggered Inputs Bus Pins Tolerate 6-kV HBM ESD Packaged in Thin Shrink Small-Outline Package With 20 Mil Terminal Pitch Consumes