SN65LVDS95DGGREP


  



  SGLS206A − OCTOBER 2003 − REVISED SEPTEMBER 2009 D Controlled Baseline D D D D D D D D D D D D D D D Inputs Meet or Exceed the Requirements of − One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree† 21:3 Data Channel Compression at up to 1.36 Gigabits per Second Throughput Suited for Point-to-Point Subsystem Communication With Very Low EMI 21 Data Channels Plus Clock in Low-Voltage TTL and 3 Data Channels Plus Clock Out Low-Voltage Differential Operates From a Single 3.3-V Supply and 250 mW (Typ) 5-V Tolerant Data Inputs ’LVDS95 Has Rising Clock Edge Triggered Inputs Bus Pins Tolerate 6-kV HBM ESD Packaged in Thin Shrink Small-Outline Package With 20 Mil Terminal Pitch Consumes