SN65LVDS96DGGR

SN65LVDS96 www.ti.com SLLS296H – MAY 1998 – REVISED JULY 2006 LVDS SERDES RECEIVER FEATURES • • • • • • • • • • • • • • 3:21 Data Channel Compression at up to 1.428 Gigabits/s Throughput Suited for Point-to-Point Subsystem Communication With Very Low EMI 3 Data Channels and Clock Low-Voltage Differential Channels in and 21 Data and Clock Low-Voltage TTL Channels Out Operates From a Single 3.3-V Supply and 250 mW (Typ) 5-V Tolerant SHTDN Input Rising Clock Edge Triggered Outputs Bus Pins Tolerate 4-kV HBM ESD Packaged in Thin Shrink Small-Outline Package With 20 Mil Terminal Pitch Consumes