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SN65LVPE502A, SN65LVPE502B
SLLSEB3C – MARCH 2012 – REVISED NOVEMBER 2016
SN65LVPE502x Dual-Channel USB 3.0 Redriver and Equalizer
1 Features
2 Applications
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1
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Single-Lane USB 3.0 Redriver and Equalizer
Selectable Equalization, De-Emphasis and Output
Swing Control
Integrated Termination
Hot-Plug Capable
Low Active Power (U0 state):
– 315 mW (Typical), VCC = 3.3 V
USB 3.0 Low Power Support:
– 7 mW (Typical) When No Connection Detected
– 70 mW (Typical) When Link in U2/U3 Mode
Excellent Jitter and Loss Compensation
Capability:
– >40 in of Total 4 mil Stripline on FR4
Small Footprint, 3 mm × 3 mm and 4 mm × 4 mm,
24-Pin VQFN Packages
High Protection Against ESD Transient:
– HBM: 5,000 V
– CDM: 1,500 V
– MM: 200 V
Notebooks
Desktops
Docking Stations
Backplanes
Active Cables
3 Description
The SN65LVPE502x devices are dual-channel,
single-lane USB 3.0 redriver and signal conditioners
supporting data rates of 5 Gbps. The devices comply
with USB 3.0 specification revision 1.0 supporting
electrical idle condition and low frequency periodic
signals (LFPS) for USB 3.0 power management
modes.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN65LVPE502A
RLL (24)
3.00 mm × 3.00 mm
SN65LVPE502A,
SN65LVPE502B
RGE (24)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application
Main PCB
Redriver
USB Host
USB
Connector
20"
Main PCB
USB Host
Connector
Device PCB
Device
Redriver
20"
3m USB
3.0 Cable
1"-6"
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN65LVPE502A, SN65LVPE502B
SLLSEB3C – MARCH 2012 – REVISED NOVEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
1
1
1
2
3
6
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 7
Electrical Characteristics........................................... 7
Dissipation Ratings ................................................... 8
Typical Characteristics ............................................ 11
7
Parameter Measurement Information ................ 16
8
Detailed Description ............................................ 19
7.1 Typical Eye Diagram and Performance Curves...... 16
8.1 Overview ................................................................. 19
8.2 Functional Block Diagram ....................................... 19
8.3 Feature Description................................................. 19
8.4 Device Functional Modes........................................ 21
9
Application and Implementation ........................ 22
9.1 Application Information............................................ 22
9.2 Typical Application .................................................. 22
10 Power Supply Recommendations ..................... 24
11 Layout................................................................... 24
11.1 Layout Guidelines ................................................. 24
11.2 Layout Example .................................................... 25
12 Device and Documentation Support ................. 26
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
26
26
26
26
13 Mechanical, Packaging, and Orderable
Information ........................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (April 2012) to Revision C
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
•
Added Storage temperature (–65 to 150°C) to the Absolute Maximum Ratings table........................................................... 6
Changes from Revision A (March 2012) to Revision B
Page
•
Added SN65LVPE502B device .............................................................................................................................................. 1
•
Changed Feature From: Small Foot Print – 24 Pin (4mm x 4mm) QFN Package To: Small Foot Print – 3x3mm and
4x4mm 24-pin QFN Packages ............................................................................................................................................... 1
•
Deleted bottom view pinout image ......................................................................................................................................... 3
•
Added RLL package pinout image ......................................................................................................................................... 4
•
Added RLL to Pin Functions table.......................................................................................................................................... 5
•
Added Host- and Device-Side Pins section.......................................................................................................................... 19
Changes from Original (March 2012) to Revision A
•
2
Page
Deleted Ordering Information table; see POA at the end of the data sheet........................................................................... 1
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Copyright © 2012–2016, Texas Instruments Incorporated
Product Folder Links: SN65LVPE502A
SN65LVPE502A, SN65LVPE502B
www.ti.com
SLLSEB3C – MARCH 2012 – REVISED NOVEMBER 2016
5 Pin Configuration and Functions
SN65LVPE502A RGE Package
24-Pin VQFN With Exposed Thermal Pad
Top View
SN65LVPE502B RGE Package
24-Pin VQFN With Exposed Thermal Pad
Top View
GND EN_RXD OS1 DE1 EQ1 VCC
6
NC
NC
1
DE2
NC
24 NC
EQ2
Device_TX1-
Host_RX1-
1
7
24 NC
Device_RX2-
Host_TX2-
CH1
CH2
Host_RX1+
Device_TX1+
Thermal Pad
(must be soldered to GND
Host_TX2Host_TX2+
Device_RX2+
GND
CH2
CH2
CH2
12
19
Host_TX2+
Thermal Pad
(must be soldered to GND
GND
Device_RX2-
Device_TX1-
Device_RX2+
Device_TX1+
GND
Host_RX1-
CH2
CH1
CH2
12
18
13
NC VCC
6
7
GND
NC
19 Host_RX1+
18
13
VCC
VCC RSVD OS2 DE2 EQ2 GND
NC
EQ1 DE1 EN_RXD NC
Pin Functions – RGE Packages
PIN
NAME
SN65LVPE502A
SN65LVPE502B
TYPE (1)
DESCRIPTION
HIGH SPEED DIFFERENTIAL I/O PINS
Host_RX1–
8
20
I
CML, inverting differential input for CH1. This pin is tied to an
internal voltage bias by dual termination resistor circuit. Must
connect to the USB 3.0 host side.
Host_RX1+
9
19
I
CML, noninverting differential input for CH1. This pin is tied to
an internal voltage bias by dual termination resistor circuit.
Must connect to the USB 3.0 host side.
Device_RX2–
20
8
I
CML, inverting differential input for CH2. This pin is tied to an
internal voltage bias by dual termination resistor circuit. Must
connect to the USB 3.0 Device side.
Device_RX2+
19
9
I
CML, noninverting differential input for CH2. This pin is tied to
an internal voltage bias by dual termination resistor circuit.
Must connect to the USB 3.0 Device side.
Device_TX1–
23
11
O
CML, inverting differential output for CH1. This pin is tied to an
internal voltage bias by termination resistors. Must connect to
the USB 3.0 Device side.
Device_TX1+
22
12
O
CML, noninverting differential output for CH1. This pin is tied
to an internal voltage bias by termination resistors. Must
connect to the USB 3.0 Device side.
Host_TX2–
11
23
O
CML, inverting differential output for CH2. This pin is tied to an
internal voltage bias by termination resistors. Must connect to
the USB 3.0 Host side.
Host_TX2+
12
22
O
CML, noninverting differential output for CH2. This pin is tied
to an internal voltage bias by termination resistors. Must
connect to the USB 3.0 Host side.
17
I
LVCMOS, sets device operation modes per Table 4; internally
pulled to VCC.
LVCMOS; RSVD. Can be left as No-Connect.
DEVICE CONTROL PINS
EN_RXD
RSVD
NC
(1)
5
14
—
I
7, 24
2, 3, 4, 6, 14, 18, 24
—
Pads are not internally connected.
I = Input, O = Output, P = Power
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Copyright © 2012–2016, Texas Instruments Incorporated
Product Folder Links: SN65LVPE502A
3
SN65LVPE502A, SN65LVPE502B
SLLSEB3C – MARCH 2012 – REVISED NOVEMBER 2016
www.ti.com
Pin Functions – RGE Packages (continued)
PIN
NAME
SN65LVPE502A
SN65LVPE502B
TYPE (1)
DESCRIPTION
EQ CONTROL PINS (2)
DE1, DE2
3, 16
16, 5
I
LVCMOS, selects de-emphasis settings for CH1 and CH2 per
Table 4; internally tied to VCC/2.
EQ1, EQ2
2, 17
15, 7
I
LVCMOS, selects equalization settings for CH1 and CH2 per
Table 4, internally tied to VCC/2.
OS1, OS2
4, 15
—
I
LVCMOS, selects output amplitude for CH1 and CH2 per
Table 4, internally tied to VCC/2.
GND
6, 10, 18, 21,
Thermal Pad
10, 21, Thermal Pad
P
Supply ground
VCC
1,13
1, 13
P
Positive supply; must be 3.3 V ±10%
POWER PINS (3)
(2)
(3)
Internally biased to VCC/2 with >200 kΩ pullup or pulldown. When pins are left as NC, board leakage at this pin pad must be 200 kΩ pullup or pulldown. When pins are left as NC, board leakage at this pin pad must be
