SN65MLVD047D

SN65MLVD047 www.ti.com SLLS606A – MARCH 2004 – REVISED JULY 2005 MULTIPOINT-LVDS QUAD DIFFERENTIAL LINE DRIVER FEATURES • • • • • DESCRIPTION Differential Line Drivers for 30-Ω to 55-Ω Loads and Data Rates(1) Up to 200 Mbps, Clock Frequencies up to 100 MHz Supports Multipoint Bus Architectures Operates from a Single 3.3-V Supply Characterized for Operation from –40°C to 85°C 16-Pin SOIC (JEDEC MS-012) and 16-Pin TSSOP (JEDEC MS-153) Packaging APPLICATIONS • • • • • • (1) Clock Distribution Backplane or Cabled Multipoint Data Transmission in Telecommunications, Automotive, Industrial, and Other Computer Systems Cellular Base Stations Central-Office and PBX Switching Bridges and Routers Low-Power High-Speed Short-Reach Alternative to TIA/EIA-485 (1) The SN65MLVD047 is a quadruple line driver. The output current of this device has been increased, in comparison to standard LVDS compliant devices, in order to support doubly terminated transmission lines and heavily loaded backplane bus applications. Backplane applications generally require impedance matching termination resistors at both ends of the bus. The effective impedance of a doubly terminated bus can be as low as 30 Ω due to the bus terminations, as well as the capacitive load of bus interface devices. SN65MLVD047 drivers allow for operation with loads as low as 30 Ω. The SN65MLVD047 devices allow for multiple drivers to be present on a single bus. Driver edge rate control is incorporated to support operation. The SN65MLVD047 provides 9-kV ESD protection on all bus pins. The data rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second). LOGIC DIAGRAM (POSITIVE LOGIC) EN EN 1A 2A 3A 4A 1Y 1Z 2Y 2Z 3Y 3Z 4Y 4Z Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2005, Texas Instruments Incorporated SN65MLVD047 www.ti.com SLLS606A – MARCH 2004 – REVISED JULY 2005 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION PART NUMBER PACKAGE MARKING SN65MLVD047D MLVD047 PACKAGE/CARRIER 16-Pin SOIC/Tube SN65MLVD047DR MLVD047 16-Pin SOIC/Tape and Reel SN65MLVD047PW MLVD047 16-Pin TSSOP/Tube SN65MLVD047PWR MLVD047 16-Pin TSSOP/Tape and Reel PACKAGE DISSIPATION RATINGS PACKAGE PCB JEDEC STANDARD TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C (1) TA = 85°C POWER RATING D(16) Low-K (2) 898 mW 7.81 mW/°C 429 mW Low-K (2) 592 mW 5.15 mW/°C 283 mw High-K (3) 945 mW 8.22 mW/°C 452 mw PW(16) (1) (2) (3) This is the inverse of the junction-to-ambient thermal resistance when board mounted and with no air flow. In accordance with the Low-K thermal metric definitions of EIA/JESD51-3. In accordance with the High-K thermal metric definitions of EIA/JESD51-7. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) UNITS range (2) VCC Supply voltage VI Input voltage range A, EN, EN –0.5 V to 4 V –0.5 V to 4 V VO Output voltage range Y, Z –1.8 V to 4 V Human Body Model (3) Electrostatic discharge TJ Junction temperature PD Continuous power dissipation (1) (2) (3) (4) (5) 2 Y and Z ±9 kV All pins ±4 kV Charged-Device Model (4) All pins ±1500 V Machine Model (5) All pins 200 V 140°C See Dissipation Rating Table Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages, are with respect to the circuit ground terminal. Tested in accordance with JEDEC Standard 22, Test Method A114-B. Tested in accordance with JEDEC Standard 22, Test Method C101-A. Tested in accordance with JEDEC Standard 22, Test Method A115-A. SN65MLVD047 www.ti.com SLLS606A – MARCH 2004 – REVISED JULY 2005 RECOMMENDED OPERATING CONDITIONS (see Figure 1) MIN NOM 3.3 MAX UNIT VCC Supply voltage 3 3.6 V VIH High-level input voltage 2 VCC V VIL Low-level input voltage 0 0.8 V –1.4 3.8 V 30 55 Ω 200 Mbps 100 MHz 125 °C Voltage at any bus terminal (separate or common mode) VY or VZ RL Differential load resistance 1/tUI Signaling rate Clock frequency TJ Junction temperature –40 THERMAL CHARACTERISTICS PARAMETER TEST CONDITIONS Low-K board (1), no airflow MIN D Low-K board (1), no airflow θJA Junction-to-ambient thermal resistance Low-K board (1), 150 LFM Low-K board (1), 250 LFM Junction-to-board thermal resistance θJC Junction-to-case thermal resistance PD Device power dissipation (1) (2) High-K board (2) MAX UNIT 128 194.2 PW High-K board (2), no airflow θJB TYP °C/W 146.8 133.1 121.6 D 51.1 PW 85.3 D 45.4 PW 34.7 °C/W °C/W EN = VCC, EN = GND, RL = 50 Ω, Input 100 MHz 50 % duty cycle square wave to 1A:4A, TA = 85°C 288.5 mW MIN (1) TYP (2) MAX UNIT 59 70 2 4 In accordance with the Low-K thermal metric difinitions of EIA/JESD51-3. In accordance with the High-K thermal metric difinitions of EIA/JESD51-7. DEVICE ELECTRICAL CHARACTERISTICS over recommended operating conditions unless otherwise noted PARAMETER ICC (1) (2) Supply current Driver enabled TEST CONDITIONS EN = VCC, EN = GND, RL = 50 Ω, All inputs = VCC or GND Driver disabled EN = GND, EN = VCC, RL = No load, All inputs = VCC or GND mA The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet. All typical values are at 25°C and with a 3.3-V supply voltage. 3 SN65MLVD047 www.ti.com SLLS606A – MARCH 2004 – REVISED JULY 2005 DEVICE ELECTRICAL CHARACTERISTICS over recommended operating conditions unless otherwise noted PARAMETER MIN (1) TYP (2) TEST CONDITIONS MAX UNIT LVTTL (EN, EN, 1A:4A) |IIH| High-level input current VIH = 2 V or VCC 0 |IIL| Low-level input current VIL = GND or 0.8 V 0 Ci Input capacitance VI = 0.4 sin(30E6πt) + 0.5 V (3) 10 µA 10 µA 5 pF M-LVDS (1Y/1Z:4Y/4Z) |VYZ| Differential output voltage magnitude 480 650 mV ∆|VYZ| Change in differential output voltage magnitude See Figure 2 between logic states –50 50 mV VOS(SS) Steady-state common-mode output voltage 0.8 1.2 V ∆VOS(SS) Change in steady-state common-mode output voltage between logic states –50 50 mV VOS(PP) Peak-to-peak common-mode output voltage 150 mV VY(OC) Maximum steady-state open-circuit output voltage 0 2.4 V 0 2.4 V 1.2 VSS V See Figure 3 See Figure 7 VZ(OC) Maximum steady-state open-circuit output voltage VP(H) Voltage overshoot, low-to-high level output VP(L) Voltage overshoot, high-to-low level output |IOS| Differential short-circuit output current magnitude See Figure 4 IOZ High-impedance state output current –1.4 V ≤ (VY or VZ) ≤ 3.8 V, Other output = 1.2 V IO(OFF) Power-off output current –1.4 V ≤ (VY or VZ) ≤ 3.8 V, Other output = 1.2 V, VCC = 0 V See Figure 5 –0.2 VSS Output capacitance VY or VZ = 0.4 sin(30E6πt) + 0.5 Other input at 1.2 V, driver disabled CYZ Differential output capacitance VYZ = 0.4 sin(30E6πt) V, (3) Driver disabled CY/Z Output capacitance balance, (CY/CZ) (1) (2) (3) 4 24 mA –15 10 µA –10 10 µA V, (3) CY or CZ V 3 pF 2.5 0.99 1.01 The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet. All typical values are at 25°C and with a 3.3-V supply voltage. HP4194A impedance analyzer (or equivalent) pF SN65MLVD047 www.ti.com SLLS606A – MARCH 2004 – REVISED JULY 2005 SWITCHING CHARACTERISTICS over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT tPLH Propagation delay time, low-to-high-level output 1 1.5 2.4 ns tPHL Propagation delay time, high-to-low-level output 1 1.5 2.4 ns tr Differential output signal rise time 1 1.9 ns tf Differential output signal fall time 1 1.9 ns tsk(o) Output skew 100 ps tsk(p) Pulse skew (|tpHL - tpLH|) 100 ps tsk(pp) Part-to-part skew (2) 600 ps tjit(per) Period jitter, rms (1 standard deviation) (3) 1 ps 5 36 ps 46 158 ps 7 ns 7 ns 8 ns 8 ns jitter (3) tjit(c-c) Cycle-to-cycle tjit(pp) Peak-to-peak jitter (3) (4) tPZH Enable time, high-impedance-to-high-level output tPZL Enable time, high-impedance-to-low-level output tPHZ Disable time, high-level-to-high-impedance output tPLZ Disable time, low-level-to-high-impedance output (1) (2) (3) (4) See Figure 5 22 All inputs 100 MHz clock input All inputs 100 MHz clock input All inputs 200 Mbps 215-1 PRBS input See Figure 6 See Figure 6 0.2 All typical values are at 25°C and with a 3.3-V supply voltage. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. Stimulus jitter has been subtracted from the measurements. Peak-to-peak jitter includes jitter due to pulse skew (tsk(p)). 5 SN65MLVD047 www.ti.com SLLS606A – MARCH 2004 – REVISED JULY 2005 PARAMETER MEASUREMENT INFORMATION VCC IY Y II D VYZ IZ VY Z VI VOS VZ VY + VZ 2 Figure 1. Driver Voltage and Current Definitions 3.32 kΩ Y + _ 49.9 Ω VYZ D Z -1 V ≤ Vtest ≤ 3.4 V 3.32 kΩ NOTE: All resistors are 1% tolerance. Figure 2. Differential Output Voltage Test Circuit R1 24.9 Ω Y C1 1 pF D ≈ 1.3 V Z ≈ 0.7 V VOS(PP) Z C2 1 pF Y R2 24.9 Ω VOS C3 2.5 pF
VOS(SS) VOS(SS) A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse frequency = 500 kHz, duty cycle = 50 ± 5%. B. C1, C2 and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%. C. R1 and R2 are metal film, surface mount, ±1%, and located within 2 cm of the D.U.T. D. The measurement of VOS(PP) is made on test equipment with a –3 dB bandwidth of at least 1 GHz. Figure 3. Test Circuit and Definitions for the Common-Mode Output Voltage Y IOS 0 V or VCC + Z VTest -1 V to 3.4 V - Figure 4. Short-Circuit Test Circuit 6 SN65MLVD047 www.ti.com SLLS606A – MARCH 2004 – REVISED JULY 2005 PARAMETER MEASUREMENT INFORMATION (continued) Y D C1 1 pF C3 0.5 pF R1 Output 50 Ω Z C2 1 pF VCC VCC/2 Input 0V tpLH tpHL VSS 0.9VSS VP(H) Output 0V VP(L) 0.1V SS 0 V SS tf tr A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, frequency = 500 kHz, duty cycle = 50 ± 5%. B. C1, C2, and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%. C. R1 is a metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T. D. The measurement is made on test equipment with a –3 dB bandwidth of at least 1 GHz. Figure 5. Driver Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal R1 24.9 Ω Y 0 V or VCC C1 1 pF D Z Input C4 Output 0.5 pF C2 1 pF C3 2.5 pF R2 24.9 Ω EN or EN VCC VCC/2 0V EN EN tpZH tpHZ ∼ 0.6 V 0.1 V 0V Output With D at VCC Output With D at 0 V tpZL tpLZ 0V -0.1 V ∼ -0.6 V A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, frequency = 500 kHz, duty cycle = 50 ± 5%. B. C1, C2, C3, and C4 includes instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%. C. R1 and R2 are metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T. D. The measurement is made on test equipment with a –3 dB bandwidth of at least 1 GHz. Figure 6. Driver Enable and Disable Time Circuit and Definitions 7 SN65MLVD047 www.ti.com SLLS606A – MARCH 2004 – REVISED JULY 2005 PARAMETER MEASUREMENT INFORMATION (continued) Y 0 V or VCC Z 1.62 kΩ , ±1% VY, or VZ Figure 7. Driver Maximum Steady State Output Voltage VCC CLOCK INPUT VCC/2 0V 1/f0 Period Jitter IDEAL OUTPUT 0 V VY -VZ VCC PRBS INPUT 0V ACTUAL OUTPUT 0 V VY -VZ VCC/2 1/f0 Peak to Peak Jitter VY -VZ tc(n) tjit(per) = tc(n) -1/f0 0V OUTPUT VY -VZ tjit(pp) Cycle to Cycle Jitter OUTPUT 0V VY - VZ tc(n) tc(n+1) tjit(cc) = | tc(n) - tc(n+1) | A. All input pulses are supplied by an Agilent 8304A Stimulus System. B. The measurement is made on a TEK TDS6604 running TDSJIT3 application software C. Period jitter and cycle-to-cycle jitter are measured using a 100 MHz 50 ±1% duty cycle clock input. D. Peak-to-peak jitter is measured using a 200 Mbps 215– 1 PRBS input. Figure 8. Driver Jitter Measurement Waveforms 8 SN65MLVD047 www.ti.com SLLS606A – MARCH 2004 – REVISED JULY 2005 DEVICE INFORMATION PIN ASSIGNMENTS D PACKAGE (TOP VIEW) EN 1A 2A VCC GND 3A 4A EN 1 2 3 4 5 6 7 8 PW PACKAGE (TOP VIEW) 16 15 14 13 12 11 10 9 1Z 1Y 2Y 2Z 3Z 3Y 4Y 4Z 1 2 3 4 5 6 7 8 EN 1A 2A VCC GND 3A 4A EN 16 15 14 13 12 11 10 9 1Z 1Y 2Y 2Z 3Z 3Y 4Y 4Z DEVICE FUNCTION TABLE INPUTS (1) (1) OUTPUTS (1) D EN EN Y Z L H L L H H H L H L OPEN H L L H X L or OPEN X Z Z X X H or OPEN Z Z H = high level, L = low level, Z = high impedance, X = Don't Care EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS DRIVER INPUT AND POSITIVE DRIVER ENABLE VCC DRIVER OUTPUT NEGATIVE DRIVER ENABLE VCC VCC 360 kΩ 400 Ω D or EN 7V 400 Ω Y or Z 360 kΩ EN 7V 9 SN65MLVD047 www.ti.com SLLS606A – MARCH 2004 – REVISED JULY 2005 TYPICAL CHARACTERISTICS RMS SUPPLY CURRENT vs INPUT FREQUENCY RMS SUPPLY CURRENT vs FREE-AIR TEMPERATURE 65 VCC = 3.3 V, TA = 25
C, EN = VCC, EN = GND, RL = 50
, All Inputs 75 70 I CC − Supply Current − mArms ICC − Supply Current − mArms 80 65 60 50 62 60 25 50 75 100 f − Input Frequency − MHz 125 −40 −15 10 35 60 TA − Free-Air Temperature − °C Figure 9. Figure 10. DIFFERENTIAL OUTPUT VOLTAGE MAGNITUDE vs INPUT FREQUENCY DRIVER PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 600 85 1.54 TA = 25
C, RL = 50
VCC = 3.6 V VCC = 3.3 V 580 1.52 t pd − Propagation Delay Time − ns VYZ − Differential Output Voltage Magnitude − mV 63 61 55 560 540 VCC = 3 V 520 VCC = 3.3 V, f = 500 kHz, RL = 50
tPHL 1.5 tPLH 1.48 1.46 1.44 1.42 1.4 1.38 1.36 500 25 50 75 100 f − Input Frequency − MHz Figure 11. 10 64 VCC = 3.3 V, f = 50 MHz, EN = VCC, EN = GND, RL = 50
125 1.34 −40 −15 10 35 60 TA − Free-Air Temperature − °C Figure 12. 85 SN65MLVD047 www.ti.com SLLS606A – MARCH 2004 – REVISED JULY 2005 TYPICAL CHARACTERISTICS (continued) DRIVER TRANSITION TIME vs FREE-AIR TEMPERATURE PEAK-TO-PEAK JITTER vs DATA RATE 100 1.7 VCC = 3.3 V, f = 500 kHz, RL = 50
90 80 tf t jit(p-p) − Peak-To-Peak Jitter − ps t r or tf − Rising or Falling Transition Time − ns 1.8 1.6 tr 1.5 1.4 1.3 1.2 −40 −15 10 35 60 70 60 50 40 30 20 10 85 VCC = 3.3 V, TA = 25
C, All Inputs = 215−1 PRBS NRZ, (See Figure 8) 50 100 TA − Free-Air Temperature − °C Figure 14. PERIOD JITTER vs CLOCK FREQUENCY CYCLE-TO-CYCLE JITTER vs CLOCK FREQUENCY 9 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 250 10 VCC = 3.3 V, TA = 25
C, All Inputs = Clock (See Figure 8) t jit(c-c) − Cycle-To-Cycle Jitter − ps t jit(per) − Period Jitter − ps 0.8 200 Figure 13. 1 0.9 150 Data Rate − Mbps 8 VCC = 3.3 V, TA = 25
C, All Inputs = Clock (See Figure 8) 7 6 5 4 3 2 1 25 50 75 100 f − Clock Frequency − MHz Figure 15. 125 0 25 50 75 100 125 f − Clock Frequency − MHz Figure 16. 11 SN65MLVD047 www.ti.com SLLS606A – MARCH 2004 – REVISED JULY 2005 APPLICATION INFORMATION Multipoint Configuration The SN65MLVD047 is designed to allow multipoint communication on a shared bus. Multipoint is a bus configuration with multiple drivers and receivers present. An example is shown in Figure 17. The figure shows transceivers interfacing to the bus, but a combination of drivers, receivers, and transceivers is also possible. Termination resistors need to be placed on each end of the bus, with the termination resistor value matched to the loaded bus impedance. Figure 17. Multipoint Architecture Multidrop Configuration Multidrop configuration is similar to multipoint configuration, but only one driver is present on the bus. A multidrop system can be configured with the driver at one end of the bus, or in the middle of the bus. When a driver is located at one end, a single termination resistor is located at the far end, close to the last receiver on the bus. Alternatively, the driver can be located in the middle of the bus, to reduce the maximum flight time. With a centrally located driver, termination resistors are located at each end of the bus. In both cases the termination resistor value should be matched to the loaded bus impedance. Figure 18 shows examples of both cases. D Zt Zt Zt D Figure 18. Multidrop Architectures With Different Driver Locations Unused Channel The SN65MLVD047 is designed to allow multipoint communication on a standard bus. A 360-kΩ pull-down resistor is built in every LVTTL input. The unused driver inputs and outputs may be left floating. Live Insertion/Glitch Free Power Up/Down During a live insertion event or a power cycle the outputs of the SN65MLVD047 leave the high impedance state and possibly glitch the bus. Specifically when the VCC applied to the device is between 1.3 and 2.0 VDC the output state (high or low) of the device reflects the input level at the corresponding A pin. 12 SN65MLVD047 www.ti.com SLLS606A – MARCH 2004 – REVISED JULY 2005 APPLICATION INFORMATION (continued) Note: Channel 1: VCC, Channel 2: Differential Bus Voltage The output state of the part during this voltage range is independent of the EN and EN pins. In order to insure that data is not corrupted during a live insertion event or the power cycling of an individual node on a multipoint bus it is important to isolate the outputs of the device from the bus until the VCC has reached at least 2.0 VDC. At this voltage level the device output state accurately reflects the logic conditions as defined in the Device Function Table. 13 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN65MLVD047D ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 MLVD047 SN65MLVD047DR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 MLVD047 SN65MLVD047PW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 MLVD047 SN65MLVD047PWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 MLVD047 SN65MLVD047PWRG4 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 MLVD047 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of