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SN65MLVD206B
SLLSEX9A – DECEMBER 2016 – REVISED FEBRUARY 2020
SN65MLVD206B Multipoint-LVDS Line Driver and Receiver (Transceiver)
With IEC ESD Protection
1 Features
3 Description
•
Compatible with the M-LVDS standard TIA/EIA899 for multipoint data interchange
Low-voltage differential 30-Ω to 55-Ω line driver
and receiver for signaling rates(1) up to
200 Mbps, clock frequencies up to 100 MHz
– Type-2 receiver provides an offset threshold to
detect open-circuit and idle-bus conditions
Bus I/O Protection
– ±8-kV HBM
– ±8-kV IEC 61000-4-2 Contact discharge
Controlled driver output voltage transition times for
improved signal quality
–1-V to 3.4-V Common-mode voltage range
allows data transfer with 2 V of ground noise
Bus pins high impedance when disabled or VCC ≤
1.5 V
100-Mbps Device Available (SN65MLVD204B)
Improved Alternatives to SN65MLVD206
The SN65MLVD206B device is a multipoint lowvoltage differential signaling (M-LVDS) line driver and
receiver which is optimized to operate at signaling
rates up to 200 Mbps. This device has a robust 3.3-V
driver and receiver in the standard SOIC footprint for
demanding industrial applications. The bus pins are
robust to ESD events, with high levels of protection to
human-body model and IEC contact discharge
specifications.
The signaling rate of a line is the number of voltage
transitions that are made per second expressed in the bps of
the unit (bits per second).
The SN65MLVD206B M-LVDS transceiver is part of
the TI extensive M-LVDS portfolio.
1
•
•
•
•
•
•
•
(1)
The device combines a differential driver and a
differential receiver (transceiver), which operates from
a single 3.3-V supply. The transceiver is optimized to
operate at signaling rates up to 200 Mbps.
The SN65MLVD206B has enhancements over similar
devices. Improved features include a controlled slew
rate on the driver output to help minimize reflections
from unterminated stubs, resulting in better signal
integrity. The same footprint definition was
maintained, allowing for an easy drop-in replacement
for a system performance upgrade. The devices are
characterized for operation from –40°C to 85°C.
Device Information(1)
2 Applications
•
•
•
•
•
Low-power, high-speed, and short-reach
alternative to TIA/EIA-485
Backplane or cabled multipoint data and clock
transmission
Cellular base stations
Central office switches
Network switches and routers
PART NUMBER
SN65MLVD206B
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
spacer
Simplified Schematic, SN65MLVD206B
D
DE
RE
A
R
B
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN65MLVD206B
SLLSEX9A – DECEMBER 2016 – REVISED FEBRUARY 2020
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
4
4
4
4
5
5
6
6
7
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Electrical Characteristics – Driver .............................
Electrical Characteristics – Receiver ........................
Electrical Characteristics – BUS Input and Output ...
Switching Characteristics – Driver ............................
Switching Characteristics – Receiver......................
Typical Characteristics ............................................
Parameter Measurement Information .................. 8
Detailed Description ............................................ 16
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagrams .....................................
Feature Description.................................................
Device Functional Modes........................................
16
16
16
17
Application and Implementation ........................ 19
9.1 Application Information............................................ 19
9.2 Typical Application ................................................. 19
10 Power Supply Recommendations ..................... 24
11 Layout................................................................... 24
11.1 Layout Guidelines ................................................. 24
11.2 Layout Example .................................................... 28
12 Device and Documentation Support ................. 30
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support .......................................
Receiving Notification of Documentation Updates
Support Resources ...............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
30
30
30
30
30
30
13 Mechanical, Packaging, and Orderable
Information ........................................................... 30
4 Revision History
Changes from Original (December 2016) to Revision A
Page
•
Deleted all references in the text, tables, and figures for devices SN65MLVD201B, SN65MLVD203B and
SN65MLVD207B .................................................................................................................................................................... 1
•
Removed pin numbers from Simplified Schematic. ............................................................................................................... 1
•
Deleted the D 14-Pin Package from the Pin Configuration and Functions ............................................................................ 3
•
Removed from Thermal Information 14-pin D, 201B, 203B, and 207B.................................................................................. 4
•
Removed IOZ, IO(OFF), CY, CZ, CYZ, and CY/Z in Driver Electrical Characteristics ..................................................................... 5
•
Removed Type-1 VIT+, VIT-, and VHYS...................................................................................................................................... 6
•
Removed CA, CB, CAB, and CA/B from Receiver Electrical Characteristics ............................................................................. 6
•
In the Bus Input and Output electrical characteristics, changed CA and CB from 5pF to 12pF.............................................. 6
•
In the Bus Input and Output electrical characteristics, changed CAB from 4pF to 7pF. ......................................................... 6
•
Changed the TYP value for t,,r,, and t,,f,, From: 2 ns To: 1.5 ns in the //Switching Characteristics – Driver// table ............. 7
•
Removed all "Y" and "Z" labels from the Parameter Measurement Information images ....................................................... 8
•
Removed Type-1 Receiver Input Threshold Test Voltages table........................................................................................... 8
•
Deleted "0.2 V Type 1" from Period Jitter in Figure 13 ....................................................................................................... 15
•
Removed Type-1 receivers exhibit 25 mV ... from Detailed Description Overview. ............................................................ 16
•
Removed pin numbers from Functional Block Diagram ....................................................................................................... 16
•
Removed Table on Type-1 receiver .................................................................................................................................... 17
•
Changed A/Y or B/Z to A or B in the Driver Output image .................................................................................................. 18
•
Changed text From: "signal of 540 V" To: "signal of 540 mV" in the Driver Output Voltage ............................................... 20
2
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SLLSEX9A – DECEMBER 2016 – REVISED FEBRUARY 2020
5 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
R
1
8
VCC
RE
2
7
B
DE
3
6
A
D
4
5
GND
Not to scale
Pin Functions
PIN
NAME
NO.
A
6
B
D
DE
TYPE
DESCRIPTION
I/O
Differential I/O
7
I/O
Differential I/O
4
Input
Driver input
3
Input
Driver enable pin; High = Enable, Low = Disable
GND
5
Power
NC
—
NC
R
1
Output
RE
2
Input
VCC
8
Power
Supply ground
No internal connection
Receiver output
Receiver enable pin; High = Disable, Low = Enable
Power supply, 3.3 V
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
–0.5
4
V
D, DE, RE
–0.5
4
V
A, B
–1.8
4
V
R
–0.3
4
V
–1.8
4
V
Supply voltage range, VCC (2)
Input voltage range
Output voltage range
A, B
Continuous power dissipation
See the Thermal Information table
Storage temperature, Tstg
(1)
(2)
UNIT
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
6.2 ESD Ratings
Contact discharge, per IEC 61000-4-2
V(ESD)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
Charged device model (CDM), per JEDEC specification JESD22C101, all pins
VALUE
UNIT
A, and B
±8000
V
A, and B
±8000
V
All pins except A
and B
±4000
V
All pins
±1500
V
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
VCC
Supply voltage
3
3.3
3.6
V
VIH
High-level input voltage
2
VCC
V
VIL
Low-level input voltage
0
0.8
V
–1.4
3.8
V
VCC
V
200
Mbps
85
°C
Voltage at any bus terminal VA
or
VB
|VID|
Magnitude of differential input voltage
RL
Differential load resistance
1/tUI
Signaling rate
TA
Operating free-air temperature in D package
30
–40
UNIT
Ω
50
6.4 Thermal Information
SN65MLVD206B
THERMAL METRIC (1)
D (SOIC)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
112.2
RθJC(top)
Junction-to-case (top) thermal resistance
56.7
RθJB
Junction-to-board thermal resistance
52.8
ψJT
Junction-to-top characterization parameter
10.3
ψJB
Junction-to-board characterization parameter
52.3
(1)
4
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over recommended operating conditions (unless otherwise noted) (1)
PARAMETER
ICC
Supply current
PD
(1)
TEST CONDITIONS
Driver only
RE and DE at VCC, RL = 50 Ω, All others open
Both disabled
RE at VCC, DE at 0 V, RL = No Load, All others open
Both enabled
RE at 0 V, DE at VCC, RL = 50 Ω, All others open
Receiver only
RE at 0 V, DE at 0 V, All others open
Device power dissipation
MIN
TYP MAX
13
RL = 50 Ω, Input to D is a 50-MHz 50% duty cycle square
wave, DE = high, RE = low, TA = 85°C
UNIT
22
1
4
16
24
4
13
mA
100
mW
All typical values are at 25°C and with a 3.3-V supply voltage.
6.6 Electrical Characteristics – Driver
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
(3)
|VAB|
Differential output voltage magnitude
Δ|VAB|
Change in differential output voltage magnitude
between logic states
VOS(SS)
Steady-state common-mode output voltage
ΔVOS(SS)
Change in steady-state common-mode output
voltage between logic states
VOS(PP)
Peak-to-peak common-mode output voltage
VA(OC)
Maximum steady-state open-circuit output voltage
VB(OC)
Maximum steady-state open-circuit output voltage
See Figure 3
See Figure 4
See Figure 8
MIN (1) TYP (2)
MAX
UNIT
480
650
mV
–50
50
mV
0.8
1.2
V
–50
50
mV
150
mV
0
2.4
V
0
2.4
V
1.2 VSS
V
µA
VP(H)
Voltage overshoot, low-to-high level output
VP(L)
Voltage overshoot, high-to-low level output
IIH
High-level input current (D, DE)
VIH = 2 V to VCC
0
10
IIL
Low-level input current (D, DE)
VIL = GND to 0.8 V
0
10
µA
|IOS|
Differential short-circuit output current magnitude
See Figure 5
24
mA
(1)
(2)
(3)
See Figure 6
–0.2 VSS
V
The algebraic convention in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
All typical values are at 25°C and with a 3.3-V supply voltage.
Measurement equipment accuracy is 10 mV at –40°C
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6.7 Electrical Characteristics – Receiver
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN TYP (1) MAX
UNIT
VIT+
Positive-going differential input voltage
threshold (2)
Type 2
VIT-
Negative-going differential input voltage
threshold (2)
Type 2
VHYS
Differential input voltage hysteresis, (VIT+ – VIT–)
Type 2
VOH
High-level output voltage (R)
IOH = –8 mA
VOL
Low-level output voltage (R)
IOL = 8 mA
0.4
V
IIH
High-level input current (RE)
VIH = 2 V to VCC
–10
0
µA
IIL
Low-level input current (RE)
VIL = GND to 0.8 V
–10
0
µA
IOZ
High-impedance output current (R)
VO = 0 V or 3.6 V
–10
15
µA
MAX
UNIT
(1)
(2)
150
See Figure 10 and Table 1
mV
50
mV
0
mV
2.4
V
All typical values are at 25°C and with a 3.3-V supply voltage.
Measurement equipment accuracy is 10 mV at –40°C
6.8 Electrical Characteristics – BUS Input and Output
over recommended operating conditions unless otherwise noted
PARAMETER
Receiver or transceiver with driver disabled
input current
IA
Receiver or transceiver with driver disabled
input current
IB
IAB
Receiver or transceiver with driver disabled
differential input current (IA – IB)
IA(OFF)
Receiver or transceiver power-off input current
IB(OFF)
Receiver or transceiver power-off input current
TEST CONDITIONS
MIN
TYP (1)
VA = 3.8 V,
VB = 1.2 V,
0
32
VA = 0 V or 2.4 V,
VB = 1.2 V
–20
20
VA = –1.4 V,
VB = 1.2 V
–32
0
VB = 3.8 V,
VA = 1.2 V
0
32
VB = 0 V or 2.4 V,
VA = 1.2 V
–20
20
VB = –1.4 V,
VA = 1.2 V
–32
0
VA = VB,
1.4 ≤ VA ≤ 3.8 V
–4
4
VA = 3.8 V,
VB = 1.2 V,
0 V ≤ VCC ≤ 1.5 V
0
32
VA = 0 V or 2.4 V,
VB = 1.2 V,
0 V ≤ VCC ≤ 1.5 V
–20
20
VA = –1.4 V,
VB = 1.2 V,
0 V ≤ VCC ≤ 1.5 V
–32
0
VB = 3.8 V,
VA = 1.2 V,
0 V ≤ VCC ≤ 1.5 V
0
32
VB = 0 V or 2.4 V,
VA = 1.2 V,
0 V ≤ VCC ≤ 1.5 V
–20
20
VB = –1.4 V,
VA = 1.2 V,
0 V ≤ VCC ≤ 1.5 V
–32
0
–4
4
µA
µA
µA
µA
µA
IAB(OFF)
Receiver input or transceiver power-off
differential input current (IA – IB)
VA = VB, 0 V ≤ VCC ≤ 1.5 V, –1.4 ≤ VA ≤ 3.8 V
CA
Transceiver with driver disabled input
capacitance
VA = 0.4 sin (30E6πt) + 0.5 V (2), VB = 1.2 V
12
pF
CB
Transceiver with driver disabled input
capacitance
VB = 0.4 sin (30E6πt) + 0.5 V (2), VA = 1.2 V
12
pF
CAB
Transceiver with driver disabled differential
input capacitance
VAB = 0.4 sin (30E6πt)V (2)
7
pF
CA/B
Transceiver with driver disabled input
capacitance balance, (CA/CB)
(1)
(2)
6
0.99
1.01
µA
pF
All typical values are at 25°C and with a 3.3-V supply voltage.
HP4194A impedance analyzer (or equivalent)
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6.9 Switching Characteristics – Driver
over recommended operating conditions unless otherwise noted
PARAMETER
MIN TYP (1) MAX
TEST CONDITIONS
UNIT
tpLH
Propagation delay time, low-to-high-level output
2
2.5
3.5
ns
tpHL
Propagation delay time, high-to-low-level output
2
2.5
3.5
ns
tr
Differential output signal rise time
tf
1.5
ns
Differential output signal fall time
1.5
ns
tsk(p)
Pulse skew (|tpHL – tpLH|)
30
tsk(pp)
Part-to-part skew
tjit(per)
Period jitter, rms (1 standard deviation) (3)
tjit(pp)
Peak-to-peak jitter
(3) (5)
tPHZ
Disable time, high-level-to-high-impedance output
tPLZ
Disable time, low-level-to-high-impedance output
tPZH
Enable time, high-impedance-to-high-level output
tPZL
Enable time, high-impedance-to-low-level output
(1)
(2)
(3)
(4)
(5)
(6)
See Figure 6
150
ps
0.9
ns
1
2
ps
160
210
ps
4
7
ns
4
7
ns
4
7
ns
4
7
ns
(2)
100-MHz clock input (4)
15
200 Mbps 2
–1 PRBS input
(6)
See Figure 7
All typical values are at 25°C and with a 3.3-V supply voltage.
Part-to-part skew is defined as the difference in propagation delays between two devices that operate at the same V/T conditions.
Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers.
tr = tf = 0.5 ns (10% to 90%), measured over 30K samples.
Peak-to-peak jitter includes jitter due to pulse skew (tsk(p)).
tr = tf = 0.5 ns (10% to 90%), measured over 100K samples.
6.10 Switching Characteristics – Receiver
over recommended operating conditions unless otherwise noted
PARAMETER
MIN TYP (1) MAX
TEST CONDITIONS
UNIT
tPLH
Propagation delay time, low-to-high-level output
2
6
10
ns
tPHL
Propagation delay time, high-to-low-level output
2
6
10
ns
tr
Output signal rise time
2.3
ns
tf
Output signal fall time
tsk(p)
Pulse skew (|tpHL – tpLH|)
tsk(pp)
Part-to-part skew (2)
CL = 15 pF, See Figure 11
tjit(per)
Period jitter, rms (1 standard deviation) (3)
100-MHz clock input (4)
tjit(pp)
Peak-to-peak jitter
(3) (5)
35
650
ps
tPHZ
Disable time, high-level-to-high-impedance output
6
10
ns
tPLZ
Disable time, low-level-to-high-impedance output
6
10
ns
tPZH
Enable time, high-impedance-to-high-level output
10
15
ns
tPZL
Enable time, high-impedance-to-low-level output
10
15
ns
(1)
(2)
(3)
(4)
(5)
(6)
CL = 15 pF, See Figure 11
Type 2 CL = 15 pF, See Figure 11
15
Type 2 200 Mbps 2
2.3
ns
750
ps
1
ns
1
–1 PRBS input
See Figure 12
400
(6)
ps
All typical values are at 25°C and with a 3.3-V supply voltage.
Part-to-part skew is defined as the difference in propagation delays between two devices that operate at the same V/T conditions.
Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers.
VID = 400 mVpp, Vcm = 1 V, tr = tf = 0.5 ns (10% to 90%), measured over 30K samples.
Peak-to-peak jitter includes jitter due to pulse skew (tsk(p))
VID = 400 mVpp, Vcm = 1 V, tr = tf = 0.5 ns (10% to 90%), measured over 100K samples.
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6.11 Typical Characteristics
594
592
590
VOD (mV)
588
586
584
582
580
578
576
3
3.1
3.2
3.3
VCC (V)
3.4
3.5
3.6
D001
TA = 25°C
Figure 1. Differential Output Voltage vs Supply Voltage
7 Parameter Measurement Information
VCC
IA
A
II
D
IB
VAB
VA
B
VI
VOS
VB
VA + VB
2
Copyright © 2016, Texas Instruments Incorporated
Figure 2. Driver Voltage and Current Definitions
3.32 kΩ
A
VAB
D
B
49.9 Ω
+
_
-1 V ≤ Vtest 10 µF) and the value of capacitance found above (0.004 µF). Place the smallest value of
capacitance as close as possible to the chip.
3.3 V
0.1 µF
0.004 µF
Figure 17. Recommended M-LVDS Bypass Capacitor Layout
9.2.3.3 Driver Input Voltage
The input stage accepts LVTTL signals. The driver operates with a decision threshold of approximately 1.4 V.
9.2.3.4 Driver Output Voltage
The driver outputs a steady state common mode voltage of 1 V with a differential signal of 540 mV under
nominal conditions.
20
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9.2.3.5 Termination Resistors
As shown earlier, an M-LVDS communication channel employs a current source driving a transmission line which
is terminated with two resistive loads. These loads serve to convert the transmitted current into a voltage at the
receiver input. To ensure good signal integrity, the termination resistors should be matched to the characteristic
impedance of the transmission line. The designer should ensure that the termination resistors are within 10% of
the nominal media characteristic impedance. If the transmission line is targeted for 100-Ω impedance, the
termination resistors should be between 90 Ω and 110 Ω. The line termination resistors are typically placed at the
ends of the transmission line.
9.2.3.6 Receiver Input Signal
The M-LVDS receivers herein comply with the M-LVDS standard and correctly determine the bus state. These
devices have Type-1 and Type-2 receivers that detect the bus state with as little as 50 mV of differential voltage
over the common mode range of –1 V to 3.4 V.
9.2.3.7 Receiver Input Threshold (Failsafe)
The MLVDS standard defines a Type-1 and Type-2 receiver. Type-1 receivers have their differential input voltage
thresholds near zero volts. Type-2 receivers have their differential input voltage thresholds offset from 0 V to
detect the absence of a voltage difference. The impact to receiver output by the offset input can be seen in
Table 5 and Figure 18.
Table 5. Receiver Input Voltage Threshold Requirements
RECEIVER TYPE
OUTPUT LOW
OUTPUT HIGH
Type 1
–2.4 V ≤ VID ≤ –0.05 V
0.05 V ≤ VID ≤ 2.4 V
Type 2
–2.4 V ≤ VID ≤ 0.05 V
0.15 V ≤ VID ≤ 2.4 V
200
Type 1
Type 2
Differential Input Voltage (mV)
High
150
100
High
50
0
Low
-50
-100
Low
Transition Regions
Figure 18. Expanded Graph of Receiver Differential Input Voltage Showing Transition Region
9.2.3.8 Receiver Output Signal
Receiver outputs comply with LVTTL output voltage standards when the supply voltage is within the range of 3 V
to 3.6 V.
9.2.3.9 Interconnecting Media
The physical communication channel between the driver and the receiver may be any balanced paired metal
conductors meeting the requirements of the M-LVDS standard, the key points which will be included here. This
media may be a twisted pair, twinax, flat ribbon cable, or PCB traces.
The nominal characteristic impedance of the interconnect should be between 100 Ω and 120 Ω with variation no
more than 10% (90 Ω to 132 Ω).
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9.2.3.10 PCB Transmission Lines
As per SNLA187, Figure 19 depicts several transmission line structures commonly used in printed-circuit boards
(PCBs). Each structure consists of a signal line and a return path with uniform cross-section along its length. A
microstrip is a signal trace on the top (or bottom) layer, separated by a dielectric layer from its return path in a
ground or power plane. A stripline is a signal trace in the inner layer, with a dielectric layer in between a ground
plane above and below the signal trace. The dimensions of the structure along with the dielectric material
properties determine the characteristic impedance of the transmission line (also called controlled-impedance
transmission line).
When two signal lines are placed close by, they form a pair of coupled transmission lines. Figure 19 shows
examples of edge-coupled microstrips, and edge-coupled or broad-side-coupled striplines. When excited by
differential signals, the coupled transmission line is referred to as a differential pair. The characteristic impedance
of each line is called odd-mode impedance. The sum of the odd-mode impedances of each line is the differential
impedance of the differential pair. In addition to the trace dimensions and dielectric material properties, the
spacing between the two traces determines the mutual coupling and impacts the differential impedance. When
the two lines are immediately adjacent; for example, if S is less than 2 × W, the differential pair is called a tightlycoupled differential pair. To maintain constant differential impedance along the length, it is important to keep the
trace width and spacing uniform along the length, as well as maintain good symmetry between the two lines.
Single-Ended Microstrip
Single-Ended Stripline
W
W
T
H
T
H
H
§ 5.98 H ·
ln ¨
¸
1.41 © 0.8 W T ¹
87
Z0
Hr
Z0
Edge-Coupled
§ 1.9 > 2 H T @ ·
ln ¨
¸
¨
Hr © >0.8 W T @ ¸¹
60
Edge-Coupled
S
S
H
H
Differential Microstrip
Zdiff
Differential Stripline
§
2 u Z0 u ¨ 1 0.48 u e
¨
©
0.96 u
s
H
·
¸
¸
¹
Zdiff
Co-Planar Coupled Microstrips
W
G
§
2 u Z0 u ¨ 1 0.347 u e
¨
©
s
H
·
¸
¸
¹
Broad-Side Coupled Striplines
W
W
S
2.9 u
G
S
H
H
Figure 19. Controlled-Impedance Transmission Lines
22
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9.2.4 Application Curves
VCC = 3.3 V
TA = 25°C
VCC = 3.3 V
Figure 20. Driver Fall Time
TA = 25°C
Figure 21. Driver Rise Time
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10 Power Supply Recommendations
The M-LVDS driver and receivers in this data sheet are designed to operate from a single power supply. Both
drivers and receivers operate with supply voltages in the range of 3 V to 3.6 V. In a typical application, a driver
and a receiver may be on separate boards, or even separate equipment. In these cases, separate supplies
would be used at each location. The expected ground potential difference between the driver power supply and
the receiver power supply would be less than ±1 V. Board level and local device level bypass capacitance should
be used and are covered Supply Bypass Capacitance.
11 Layout
11.1 Layout Guidelines
11.1.1 Microstrip vs. Stripline Topologies
As per SLLD009, printed-circuit boards usually offer designers two transmission line options: Microstrip and
stripline. Microstrips are traces on the outer layer of a PCB, as shown in Figure 22.
Figure 22. Microstrip Topology
On the other hand, striplines are traces between two ground planes. Striplines are less prone to emissions and
susceptibility problems because the reference planes effectively shield the embedded traces. However, from the
standpoint of high-speed transmission, juxtaposing two planes creates additional capacitance. TI recommends
routing M-LVDS signals on microstrip transmission lines if possible. The PCB traces allow designers to specify
the necessary tolerances for ZO based on the overall noise budget and reflection allowances. Footnotes 1 (1), 2 (2),
and 3 (3) provide formulas for ZO and tPD for differential and single-ended traces. (1) (2) (3)
Figure 23. Stripline Topology
(1)
(2)
(3)
24
Howard Johnson & Martin Graham.1993. High Speed Digital Design – A Handbook of Black Magic. Prentice Hall PRT. ISBN number
013395724.
Mark I. Montrose. 1996. Printed Circuit Board Design Techniques for EMC Compliance. IEEE Press. ISBN number 0780311310.
Clyde F. Coombs, Jr. Ed, Printed Circuits Handbook, McGraw Hill, ISBN number 0070127549.
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Layout Guidelines (continued)
11.1.2 Dielectric Type and Board Construction
The speeds at which signals travel across the board dictates the choice of dielectric. FR-4, or equivalent, usually
provides adequate performance for use with M-LVDS signals. If rise or fall times of TTL/CMOS signals are less
than 500 ps, empirical results indicate that a material with a dielectric constant near 3.4, such as Rogers™ 4350
or Nelco N4000-13 is better suited. Once the designer chooses the dielectric, there are several parameters
pertaining to the board construction that can affect performance. The following set of guidelines were developed
experimentally through several designs involving M-LVDS devices:
• Copper weight: 15 g or 1/2 oz start, plated to 30 g or 1 oz
• All exposed circuitry should be solder-plated (60/40) to 7.62 μm or 0.0003 in (minimum).
• Copper plating should be 25.4 μm or 0.001 in (minimum) in plated-through-holes.
• Solder mask over bare copper with solder hot-air leveling
11.1.3 Recommended Stack Layout
Following the choice of dielectrics and design specifications, you must decide how many levels to use in the
stack. To reduce the TTL/CMOS to M-LVDS crosstalk, it is a good practice to have at least two separate signal
planes as shown in Figure 24.
Layer 1: Routed Plane (MLVDS Signals)
Layer 2: Ground Plane
Layer 3: Power Plane
Layer 4: Routed Plane (TTL/CMOS Signals)
Figure 24. Four-Layer PCB Board
NOTE
The separation between layers 2 and 3 should be 127 μm (0.005 in). By keeping the
power and ground planes tightly coupled, the increased capacitance acts as a bypass for
transients.
One of the most common stack configurations is the six-layer board, as shown in Figure 25.
Layer 1: Routed Plane (MLVDS Signals)
Layer 2: Ground Plane
Layer 3: Power Plane
Layer 4: Ground Plane
Layer 5: Ground Plane
Layer 4: Routed Plane (TTL Signals)
Figure 25. Six-Layer PCB Board
In this particular configuration, it is possible to isolate each signal layer from the power plane by at least one
ground plane. The result is improved signal integrity; however, fabrication is more expensive. Using the 6-layer
board is preferable, because it offers the layout designer more flexibility in varying the distance between signal
layers and referenced planes, in addition to ensuring reference to a ground plane for signal layers 1 and 6.
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Layout Guidelines (continued)
11.1.4 Separation Between Traces
The separation between traces depends on several factors; however, the amount of coupling that can be
tolerated usually dictates the actual separation. Low noise coupling requires close coupling between the
differential pair of an M-LVDS link to benefit from the electromagnetic field cancellation. The traces should be
100-Ω differential and thus coupled in the manner that best fits this requirement. In addition, differential pairs
should have the same electrical length to ensure that they are balanced, thus minimizing problems with skew and
signal reflection.
In the case of two adjacent single-ended traces, one should use the 3-W rule, which stipulates that the distance
between two traces must be greater than two times the width of a single trace, or three times its width measured
from trace center to trace center. This increased separation effectively reduces the potential for crosstalk. The
same rule should be applied to the separation between adjacent M-LVDS differential pairs, whether the traces
are edge-coupled or broad-side-coupled.
W
Differential Traces
MLVDS
Pair
S=
Minimum spacing as
defined by PCB vendor
W
t2W
Single-Ended Traces
TTL/CMOS
Trace
W
Figure 26. 3-W Rule for Single-Ended and Differential Traces (Top View)
You should exercise caution when using autorouters, because they do not always account for all factors affecting
crosstalk and signal reflection. For instance, it is best to avoid sharp 90° turns to prevent discontinuities in the
signal path. Using successive 45° turns tends to minimize reflections.
11.1.5 Crosstalk and Ground Bounce Minimization
To reduce crosstalk, it is important to provide a return path to high-frequency currents that is as close as possible
to its originating trace. A ground plane usually achieves this. Because the returning currents always choose the
path of lowest inductance, they are most likely to return directly under the original trace, thus minimizing
crosstalk. Lowering the area of the current loop lowers the potential for crosstalk. Traces kept as short as
possible with an uninterrupted ground plane running beneath them emit the minimum amount of electromagnetic
field strength. Discontinuities in the ground plane increase the return path inductance and should be avoided.
11.1.6 Decoupling
Each power or ground lead of a high-speed device should be connected to the PCB through a low inductance
path. For best results, one or more vias are used to connect a power or ground pin to the nearby plane. Ideally,
via placement is immediately adjacent to the pin to avoid adding trace inductance. Placing a power plane closer
to the top of the board reduces the effective via length and its associated inductance.
26
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Layout Guidelines (continued)
VCC
Via
GND
Via
4 mil
TOP signal layer + GND fill
VDD 1 plane
Buried capacitor
GND plane
Signal layer
6 mil
>
Board thickness
approximately 100 mil
2 mil
GND plane
Signal layers
VCC plane
4 mil
Signal layer
GND plane
Buried capacitor
VDD 2 plane
BOTTOM signal layer + GND fill
>
6 mil
Typical 12-Layer PCB
Figure 27. Low Inductance, High-Capacitance Power Connection
Bypass capacitors should be placed close to VDD pins. They can be placed conveniently near the corners or
underneath the package to minimize the loop area. This extends the useful frequency range of the added
capacitance. Small-physical-size capacitors, such as 0402, 0201, or X7R surface-mount capacitors should be
used to minimize body inductance of capacitors. Each bypass capacitor is connected to the power and ground
plane through vias tangent to the pads of the capacitor as shown in Figure 28(a).
An X7R surface-mount capacitor of size 0402 has about 0.5 nH of body inductance. At frequencies above 30
MHz or so, X7R capacitors behave as low-impedance inductors. To extend the operating frequency range to a
few hundred MHz, an array of different capacitor values like 100 pF, 1 nF, 0.03 μF, and 0.1 μF are commonly
used in parallel. The most effective bypass capacitor can be built using sandwiched layers of power and ground
at a separation of 2 to 3 mils. With a 2-mil FR4 dielectric, there is approximately 500 pF per square inch of PCB.
Many high-speed devices provide a low-inductance GND connection on the backside of the package. This center
pad must be connected to a ground plane through an array of vias. The via array reduces the effective
inductance to ground and enhances the thermal performance of the small Surface Mount Technology (SMT)
package. Placing vias around the perimeter of the pad connection ensures proper heat spreading and the lowest
possible die temperature. Placing high-performance devices on opposing sides of the PCB using two GND
planes (as shown in Figure 19) creates multiple paths for heat transfer. Often thermal PCB issues are the result
of one device adding heat to another, resulting in a very high local temperature. Multiple paths for heat transfer
minimize this possibility. In many cases the GND pad makes the optimal decoupling layout impossible to achieve
due to insufficient pad-to-pad spacing as shown in Figure 28(b). When this occurs, placing the decoupling
capacitor on the backside of the board keeps the extra inductance to a minimum. It is important to place the VDD
via as close to the device pin as possible while still allowing for sufficient solder mask coverage. If the via is left
open, solder may flow from the pad and into the via barrel. This will result in a poor solder connection.
(a)
(b)
VDD
0402
IN±
IN+
0402
Figure 28. Typical Decoupling Capacitor Layouts
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11.2 Layout Example
At least two or three times the width of an individual trace should separate single-ended traces and differential
pairs to minimize the potential for crosstalk. Single-ended traces that run in parallel for less than the wavelength
of the rise or fall times usually have negligible crosstalk. Increase the spacing between signal paths for long
parallel runs to reduce crosstalk. Boards with limited real estate can benefit from the staggered trace layout, as
shown in Figure 29.
Layer 1
Layer 6
Figure 29. Staggered Trace Layout
28
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Layout Example (continued)
This configuration lays out alternating signal traces on different layers; thus, the horizontal separation between
traces can be less than 2 or 3 times the width of individual traces. To ensure continuity in the ground signal path,
TI recommends having an adjacent ground via for every signal via, as shown in Figure 30. Note that vias create
additional capacitance. For example, a typical via has a lumped capacitance effect of 1/2 pF to 1 pF in FR4.
Signal Via
Signal Trace
Uninterrupted Ground Plane
Signal Trace
Uninterrupted Ground Plane
Ground Via
Figure 30. Ground Via Location (Side View)
Short and low-impedance connection of the device ground pins to the PCB ground plane reduces ground
bounce. Holes and cutouts in the ground planes can adversely affect current return paths if they create
discontinuities that increase returning current loop areas.
To minimize EMI problems, TI recommends avoiding discontinuities below a trace (for example, holes, slits, and
so on) and keeping traces as short as possible. Zoning the board wisely by placing all similar functions in the
same area, as opposed to mixing them together, helps reduce susceptibility issues.
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12 Device and Documentation Support
12.1 Documentation Support
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
Rogers is a trademark of Rogers Corporation.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
30
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN65MLVD206BD
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
MF206B
SN65MLVD206BDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
MF206B
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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