SN54ABT16470, SN74ABT16470
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS085E – FEBRUARY 1991 – REVISED MAY 1997
D
D
D
D
D
D
D
D
SN54ABT16470 . . . WD PACKAGE
SN74ABT16470 . . . DGG OR DL PACKAGE
(TOP VIEW)
Members of the Texas Instruments
Widebus Family
State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
1OEAB
1CLKAB
1CLKENAB
GND
1A1
1A2
VCC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
VCC
2A7
2A8
GND
2CLKENAB
2CLKAB
2OEAB
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
Typical VOLP (Output Ground Bounce) < 1 V
at VCC = 5 V, TA = 25°C
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB
Layout
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
description
The ’ABT16470 are 16-bit registered transceivers
that contain two sets of D-type flip-flops for
temporary storage of data flowing in either
direction. The ’ABT16470 can be used as two 8-bit
transceivers or one 16-bit transceiver. Separate
clock (CLKAB or CLKBA) and output-enable
(OEAB or OEBA) inputs are provided for each
register to permit independent control in either
direction of data flow.
To avoid false clocking of the flip-flops, clock
enable (CLKEN) should not be switched from high
to low while CLK is high.
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1OEBA
1CLKBA
1CLKENBA
GND
1B1
1B2
VCC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
VCC
2B7
2B8
GND
2CLKENBA
2CLKBA
2OEBA
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT16470 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT16470 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
Copyright 1997, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54ABT16470, SN74ABT16470
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS085E – FEBRUARY 1991 – REVISED MAY 1997
FUNCTION TABLE†
INPUTS
CLKENAB
CLKAB
H
X
OUTPUT
B
OEAB
A
X
X
X
Z
X
H
X
Z
L
L
L
X
L
↑
L
L
B0‡
L
L
↑
L
H
H
† A-to-B data flow is shown: B-to-A flow is similar but uses
CLKENBA, CLKBA, and OEBA.
‡ Output level before the indicated steady-state input
conditions were established
2
POST OFFICE BOX 655303
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SN54ABT16470, SN74ABT16470
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS085E – FEBRUARY 1991 – REVISED MAY 1997
logic symbol†
1OEBA
1CLKENBA
1CLKBA
1OEAB
1CLKENAB
1CLKAB
2OEBA
2CLKENBA
2CLKBA
2OEAB
2CLKENAB
2CLKAB
1A1
56
54
55
1
3
2
29
31
30
28
26
27
1EN3
G1
1C5
2EN4
G2
2C6
7EN9
G7
7C11
8EN10
G8
8C12
5
6D
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
2A3
2A4
2A5
2A6
2A7
2A8
5D
1
4
52
6
51
8
49
9
48
10
47
12
45
13
44
14
43
15
42
12D
2A2
1
1
11D
1
10
16
41
17
40
19
38
20
37
21
36
23
34
24
33
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
POST OFFICE BOX 655303
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3
SN54ABT16470, SN74ABT16470
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS085E – FEBRUARY 1991 – REVISED MAY 1997
logic diagram (positive logic)
1OEBA
1CLKENBA
1CLKBA
1OEAB
1CLKENAB
56
54
55
1
3
2
1CLKAB
1A1
C1
5
1D
52
1B1
C1
1D
To Seven Other Channels
2OEBA
2CLKENBA
2CLKBA
2OEAB
2CLKENAB
29
31
30
28
26
27
2CLKAB
2A1
C1
15
1D
C1
1D
To Seven Other Channels
4
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42
2B1
SN54ABT16470, SN74ABT16470
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS085E – FEBRUARY 1991 – REVISED MAY 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Current into any output in the low state, IO: SN54ABT16470 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74ABT16470 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
recommended operating conditions (see Note 3)
SN54ABT16470
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
IOH
IOL
High-level output current
∆t/∆v
Input transition rise or fall rate
High-level input voltage
SN74ABT16470
MIN
MAX
MIN
MAX
4.5
5.5
4.5
5.5
2
2
0.8
Input voltage
0
Low-level output current
Outputs enabled
TA
Operating free-air temperature
NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.
–55
VCC
–24
V
V
0.8
0
UNIT
VCC
–32
V
V
mA
48
64
mA
10
10
ns/V
85
°C
125
–40
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
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5
SN54ABT16470, SN74ABT16470
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS085E – FEBRUARY 1991 – REVISED MAY 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.5 V,
II = –18 mA
IOH = –3 mA
VCC = 5 V,
VCC = 4
4.5
5V
VOL
VCC = 4
4.5
5V
MIN
MIN
–1.2
MAX
SN74ABT16470
MIN
–1.2
MAX
–1.2
2.5
2.5
IOH = –3 mA
IOH = –24 mA
3
3
3
2
2
IOH = –32 mA
IOL = 48 mA
2*
VI = VCC or GND
IOZH‡
IOZL‡
VCC = 5.5 V,
VCC = 5.5 V,
VO = 2.7 V
VO = 0.5 V
Ioff
VCC = 0,
VCC = 5.5 V,
VO = 5.5 V
VI or VO ≤ 4.5 V
VCC = 5.5 V,
VO = 2.5 V
Outputs high
A or B ports
ICEX
IO§
0.55
0.55*
0.55
A or B ports
VCC = 5.5 V,
IO = 0,
VI = VCC or GND
Outputs high
Outputs low
Ci
Control inputs
Cio
A or B ports
±1
±100
±100
±100
50
50
50
µA
–50
–50
–200
VI = 2.5 V or 0.5 V
VO = 2.5 V or 0.5 V
50
–50
–200
–50
µA
–50
µA
±100
µA
50
µA
–200
mA
2
2
2
35
35
35
2
2
2
0.5
0.5
0.5
Outputs disabled
VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
∆ICC¶
mV
±1
50
–100
V
±1
±100
–50
V
V
100
Control inputs
UNIT
2
0.55
IOL = 64 mA
VCC = 5
5.5
5V
V,
ICC
SN54ABT16470
2.5
Vhys
II
TA = 25°C
TYP†
MAX
mA
mA
3
pF
8.5
pF
* On products compliant to MIL-PRF-38535, this parameter does not apply.
† All typical values are at VCC = 5 V.
‡ The parameters IOZH and IOZL include the input leakage current.
§ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
VCC = 5 V,,
TA = 25°C
SN74ABT16470
MIN
MAX
MIN
MAX
MIN
MAX
0
150
0
150
0
150
UNIT
fclock
tw#
Clock frequency
Pulse duration, CLKAB or CLKBA high or low
3.3
3.3
3.3
ns
tsu
th
Setup time, data before CLKAB↑ or CLKBA↑
4
4
4
ns
1
1
1
ns
Hold time, data after CLKAB↑ or CLKBA↑
# This parameter is characterized, but not production tested.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
SN54ABT16470
POST OFFICE BOX 655303
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MHz
SN54ABT16470, SN74ABT16470
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS085E – FEBRUARY 1991 – REVISED MAY 1997
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
TA = 25°C
MIN
TYP
SN54ABT16470
MAX
150
CLK
A or B
OE
A or B
OE
A or B
CLKEN
A or B
CLKEN
A or B
MIN
MAX
150
SN74ABT16470
MIN
UNIT
MAX
150
MHz
1.4
3.1
4.8
1.4
5.1
1.4
4.9
1.3
3.2
4.6
1.3
5.1
1.3
4.9
1
3.1
4.3
1
5
1
4.9
1.2
3.6
5.8
1.2
6.9
1.2
6.8
1.9
3.7
4.9
1.9
6
1.9
5.5
1.6
3.3
4.8
1.6
5.4
1.6
5.3
1
3.4
4.6
1
5.8
1
5.7
1.2
3.9
6
1.2
7.3
1.2
7.2
1.7
3.9
5.2
1.7
6.2
1.7
5.8
1.5
3.6
5.3
1.5
5.5
1.5
5.4
ns
ns
ns
ns
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SN54ABT16470, SN74ABT16470
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS085E – FEBRUARY 1991 – REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
500 Ω
From Output
Under Test
S1
7V
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7V
Open
3V
LOAD CIRCUIT
Timing Input
1.5 V
0V
tw
tsu
3V
th
3V
1.5 V
Input
1.5 V
0V
Data Input
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
3V
1.5 V
Input
1.5 V
0V
VOH
1.5 V
Output
1.5 V
VOL
VOH
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
1.5 V
0V
tPZL
tPLZ
Output
Waveform 1
S1 at 7 V
(see Note B)
tPLH
tPHL
Output
3V
Output
Control
tPHL
tPLH
1.5 V
Output
Waveform 2
S1 at Open
(see Note B)
1.5 V
3.5 V
VOL + 0.3 V
VOL
tPHZ
tPZH
1.5 V
VOH – 0.3 V
VOH
≈0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
8
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PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN74ABT16470DGGR
Package Package Pins
Type Drawing
TSSOP
DGG
56
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
24.4
Pack Materials-Page 1
8.6
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
15.6
1.8
12.0
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74ABT16470DGGR
TSSOP
DGG
56
2000
367.0
367.0
45.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name
Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
SN74ABT16470DL
DL
SSOP
56
20
473.7
14.24
5110
7.87
Pack Materials-Page 3
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